STATCOM - Final Slides for Lecture

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Transcript of STATCOM - Final Slides for Lecture

STATCOMDr. Biswarup Das Department of Electrical Engineering IIT Roorkee

12-pulse inverter using delta/open and star/open connection of six-pulse units.

12-pulse waveforms created from two sets of six-pulse waveforms

True 48 pulse configuration

True 48 pulse STATCOM waveform

Diagram of quasi-48 pulse STATCOM

Voltage waveforms of two six-pulse converters (V1Y, V1) and four phase-shifted 12-pulse converters (Va1, Va2, Va3, Va4)

Quasi-48-pulse STATCOM waveforms.

Multi-pulse STATCOM For true 48 pulse, 8 zig-zag transformers with tertiary winding are needed In quasi 48 pulse, ordinary transformers are sufficient Transformer complexity and cost is more in true 48 pulse than in quasi 48 pulse Indirect control of multi-pulse STATCOM

Multi-level inverters Diode clamped Flying capacitor Cascaded H-bridge

H-Bridge Multilevel InverterBasic Module Output voltage

Constraint: S1 S2; S3 S4

Types of H-bridge Multilevel Inverters1. 2. 3. 4. Cascade H-Bridge Hybrid H-Bridge Quasilinear New Hybrid (Trinary)

Cascade H-Bridge multilevel Inverter

All DC source voltages are of equal ratings

Level Number= 2S+1Where, S= Number of stages

Cascade H-bridge Inverter

a) Circuit diagram

b) waveform showing 9-level converter phase voltage

Cascade H-bridge Inverter For an M-level inverter (M-1)/2 Full Bridge Inverters (FBI) are required The output phase voltage is synthesized by the sum of all inverter outputs

3- stage Cascade H-bridge

Possible combinations for 3-stage Cascade H-bridge Inverter

Vout VDC 1V 1V 1V -3V N N N -2 V -1 V 0V 0 0 N P N P 0 N P 0 0 P N 0 P N P N 0 0 0 1V P 0 0 N P P 0 P 0 P N P 0 0 P P P N 2V 3V N N 0 N N P 0 0 N N 0 N N P N 0 N 0 0 N N P N N N 0 0 0 P P P P 0 P P P P 0 P

Cascade seven level 3 phase inverter

Waveform of cascade seven level inverter

Hybrid (binary) H-Bridge Multilevel Inverter

Level Number = 2s+1 1

(a) 3-stage BMVSI (b) output waveform

Possible combinations for 3-stage Hybrid H-bridge InverterVout VDC -7 -6 -5 -4 -3 -2 -1 0 1 2 3

1V 2V 4V

N N N

0 P N 0 N N 0 0 N N N N

P N N 0 0 N P P 0 P N N 0 0 P N P 0 N P N P 0 N P 0 0 P N P N P 0 N N 0 N 0 N 0 0 N 0 0 0 P 0 P 0 P P4 0 0 P P 0 P 5 N P P 6 0 P P 7 P P P

Binary seven level 3 phase inverter

Waveforms of binary seven level inverter

Advantages Stage with higher DC link voltage has Lower number of commutations Lower associated switching loss

Higher DC link voltage consists of lower switch frequency component (IGCT) Lower DC link voltage consists of higher switching frequency components (IGBT)

Quasi-linear multilevel inverter

3 stage quasi-linear inverter: a) circuit diagram b) waveform

Possible combinations for 3-stage Quasilinear inverterVDC -9 -8 -7 -6 Vout -5 -4 -3 -2 -1

1V 2V 6V0 0 0 0

N N N1 P N 0 P 0 0

0 N N2 0 P 0

P N N 0 N N3 P N P N 0 P

0 0 N4 0 N P

P N 0 P N N5 P N N 0 P P

0 P N6 0 0 P

P N P N N 07 P N 0 P P P

0 N 08 0 P P

P N N 0 0 09 P P P

Terniary multilevel inverter

3-Stage New Hybrid Inverter

Possible combinations for 3-stage Terniary InverterVout VDC -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1

1V 3V 9V 00 0 0

N N N 1P 0 0

0 N N 2N P 0

P N N 30 P 0

N 0 N 4P P 0

0 0 N 5N N P

P 0 N 60 N P

N P N 7P N P

0 P N 8N 0 P

P P N 90 0 P

N N 0 10P 0 P

0 N 0 11N P P

P N 0 120 P P

N 0 0 13P P P

V K(max)

V out (max)

Level number

Cascade Hybrid Quasi-linear

VDC 2 S - 1 VDC 2 * (3 S-2) VDC

S VDC (2S-1) VDC (3S 1) VDC

2S + 1 2S+1 - 1 2*3S-1 + 1

New Hybrid

3S-1 VDC

((3S-1)/2) VDC

3S

Reference1. Y. S. Lai and F. S. Shyu, Topology for hybrid multilevel inverter, IEE proc.-Electr. Power Appl., Vol. 149, No. 6, November 2002. Page(s): 449-458.

Cascaded multilevel inverter

Solution procedure

Chain-link converter based STATCOM

Basic circuit

Voltage waveform of a 3 link (7 level) chain converter

(2N+1) level output phase voltage waveform of a CLS with N links per phase.

References1. J. D. Ainsworth et al., Static VAr compensator (STATCOM) based on single-phase chain circuit converters, IEE Proc. Generation, Transmission, Distribution, Vol. 145. No. 4, July I998, pp: 381-386. 2. Nikunj M. Shah, Vijay K. Sood and Venkat Ramachandran, EMTP Simulation of a ChainLink STATCOM, IEEE TRANSACTIONS ON POWER DELIVERY,VOL. 23, NO. 4,OCTOBER 2008, pp: 2148-2159.

Basic indirect control scheme (Fig. HG_5.35)

Direct control scheme (Fig. HG_5.36)

Operating V-I characteristics of STATCOM (Fig. HG_5.37)

Loss Vs. output characteristics of a 48 pulse, 100 MVAR STATCOM (Fig. HG_5.38)

Combined characteristics of a STATCOM-FC (Fig. HG_5.39)

Combined characteristics of a STATCOM-fixed reactor (Fig. HG_5.40)

Combined characteristics of a STATCOM-TSC-TCR SVC (Fig. HG_5.41)

Loss Vs. output characteristics of different static VAR generator systems (Fig. HG_5.42)

General control scheme of a static VAR generator (Fig. HG_5.43)

Implementation of the slope in the V-I characteristics of a STATCOM (Fig. HG_5.44)

V-I characteristics of a SVC and STATCOM (Fig. HG_5.45)

VAR reserve control

Diagrammatic representation of the concept of VAR reserve control (Fig. HG_5.56)

Equal area criterion to demonstrate improvement of transient stability with shunt compensation (Fig. HG_5.5

Improvement of transient stability by STATCOM and SVC; a) STATCOM and b) SVC (Fig. HG_5.62)

VS

VR

jX P+jQ

VR

(V

2 s

2QX )

V

4 s

4QXV 2

2 s

4P X

2

2

Voltage stability limit of a radial line without any compensation

VS

VR

jX P+jQSTATCOM

Voltage stability limit of a radial line with shunt compensation