SNDR Improvement Algorithms in Binary and Ternary ®â€‌®£DAC SNDR...

SNDR Improvement Algorithms in Binary and Ternary ®â€‌®£DAC SNDR Fourth-order CT DSM with Second-order
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Transcript of SNDR Improvement Algorithms in Binary and Ternary ®â€‌®£DAC SNDR...

  • SNDR Improvement Algorithms in Binary and Ternary ΔΣDAC Jun-ya Kojima, Nene Kushita, Masahiro Murakami, Anna Kuwana, Haruo Kobayashi

    1.Objective

    Modulator output

    Analog output Digital input

    Digital ΔΣ modulator

    Quantizer

    Limit cycle problem for small input

    Removal of analog signal by LPF sharply

    Goal ・Limit cycle reduction

    ・Relax LPF requirement

    Analog output = Signal + Limit cycle

    Signal

    ⇒ Difficult

    Measurement & audio applications

    Limit cycle

    Limit cycle reduction using digital dither

    Development of high-Resolution,

    high-Linearity ΔΣ DAC

     Approach

    2.Background

    t181d024@gunma-u.ac.jpDivision of Electronics and Informatics, Gunma University

    1.Objective Demand for better digital-to-analog converter (DAC)

    Problem

    Manufacturing variations

    among DAC circuit elements

    Purpose of this work

    DSP algorithms

    to suppress the variation effects

    for binary and ternary DACs

    High resolutionConventional

    2.Background

    ΔΣ digital modulator

    Quantizer

    Feedback

    Integrator +

    − Analog

    LPF∑ Multi-bit

    DAC

    Analog outputDigital input

    Digital Analog

    Signal

    Δ:Difference Σ:Integral

    Noise

    transfer

    Power spectrum

    ΔΣ Digital to Analog Converter (Low Pass)

    Measurement & audio applications

    < Using >

     ΔΣ Digital-to-Analog Converter (ΔΣDAC) →Required

     Mostly digital circuit

     High-resolution ,High-linearity

     DC signal , low frequency signal generation

     Purpose

     Improve linearity (High resolution)

    3. Introduction to Ternary

    +8

    0 0

    +8

    -8

    Ternary⇒ +, - and 0 valueBinary⇒ + and 0 value

    Forces

    0 +1 +10-1

    Binary unit cell 1-bit Ternary unit cell 1.5-bit

    TernaryBinary

    9 Level 17 Level

    8 current sources

    Higher resolution for given current sources

    Smaller number of current sources for given resolution

    Reasons for Ternary Usage

    4. DWA*Algorithm (* Data-Weighted Averaging)

    Positive Voltage

    negative Voltage

    Conventional DWA type I DWA type II

    Unit cell mismatch

    ⇒ Accumulation

    𝑒𝑖 Improve linearity

    ⇒ Averaging

    Distribute unit cell mismatch

    ( Back and forth )

    6.Pointer 1 Pointer 2 Pointers 4 Pointers

    5. Binary, Ternary DWA Overview

    Signal Band Value Number (N) of

    Signal Bands DWA type

    LP Binary 1 I

    Ternary 1 I

    HP Binary 1 II

    Ternary 1 I

    BP Binary 2 II

    Binary 4 II

    Ternary 2 I

    Ternary 4 I

    New Findings

    Reference [1] R. Schreier, G.C Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE press (2009).[2] Y. Geerts, M.

    Steyaert, W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters, Kulwer Academic Publisher (2002).

    [3] M. Murakami, H. Kobayashi, et. al., "I-Q Signal Generation Techniques for Communication IC Testing and ATE

    Systems", IEEE International Test Conference (Nov. 2016).

    [4] A. Motozawa, H. Hagiwara, Y. Yamada, H. Kobayashi, et. al., "Multi-BP ΔΣ Modulation Techniques and Their

    Applications", IEICE Tran, vol. J90-C, no.2, pp.143-158 (Feb. 2007). [5] I. Jang, et. al., "A 4.2mW 10MHz BW 74.4dB

    SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC", VLSI Circuits Symp

    (June 2017).

    7.Conclusion

    In case HP, BP ΔΣ DACs with ternary unit cells, DWA

    type I with pointers alternately used is effective.

    < ΔΣ DA modulator >

    Segmented DAC with ternary unit cells

    ● High-pass (HP) ΔΣ DAC (N=1)

    σ = 0.1%

    0

    20

    40

    60

    80

    100

    120

    0 1 2 3 4 5 6 7

    SN D

    R (

    d B

    )

    OSR (2n)

    ● Band-pass (BP) ΔΣ DAC (N=2)

    σ = 0.1%

    0

    20

    40

    60

    80

    100

    120

    0 1 2 3 4 5 6 7

    SN D

    R (

    d B

    )

    OSR (2n)

    σ = 0.1%

    ● Band-pass (BP) ΔΣ DAC (N=4)

    0

    20

    40

    60

    80

    100

    120

    0 1 2 3 4 5 6 7

    SN D

    R (

    d B

    )

    OSR (2n)

    It is high linearity when DWA type l is used.

    < DWA type I >

    < DWA type II >

    < DWA type II >

    Noise shape