SLPS393A –OCTOBER 2013–REVISED JANUARY 2015 ...SLPS393A –OCTOBER 2013–REVISED JANUARY 2015 7...

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CSD17571Q2SLPS393A –OCTOBER 2013–REVISED JANUARY 2015

CSD17571Q2 30V N-Channel NexFET™ Power MOSFETs1 Features

Product Summary1• Low Qg and Qgd TA = 25°C TYPICAL VALUE UNIT• Low Thermal Resistance VDS Drain-to-Source Voltage 30 V• Avalanche Rated Qg Gate Charge Total (4.5 V) 2.4 nC

Qgd Gate Charge Gate-to-Drain 0.6 nC• Pb-Free Terminal PlatingVGS = 4.5 V 24 mΩ• RoHS Compliant RDS(on) Drain-to-Source On-ResistanceVGS = 10 V 20 mΩ• Halogen Free

VGS(th) Threshold Voltage 1.6 V• SON 2 mm × 2 mm Plastic Package

Ordering Information(1)2 ApplicationsDevice Media Qty Package Ship

• Optimized for Load Switch Applications SON 2 x 2 mm Tape andCSD17571Q2 7-Inch Reel 3000 Plastic Package Reel• Storage, Tablets, and Handheld Devices(1) For all available packages, see the orderable addendum at• Optimized for Control FET Applications

the end of the data sheet.

3 Description Absolute Maximum RatingsThis 30 V, 20 mΩ, SON 2×2 NexFET™ power

TA = 25°C VALUE UNITMOSFET is designed to minimize losses in powerVDS Drain-to-Source Voltage 30 Vconversion and load management applications, whileVGS Gate-to-Source Voltage ±20 Voffering excellent thermal performance for the size of

Continuous Drain Current (Package Limit) 22 Athe package. IDContinuous Drain Current(1) 7.6 A

Top View IDM Pulsed Drain Current, TA = 25°C(2) 39 APD Power Dissipation(1) 2.5 W

TJ, Operating Junction and –55 to 150 °CTstg Storage Temperature Range

Avalanche Energy, single pulseEAS 7.2 mJID = 12 A, L = 0.1 mH, RG = 25 Ω

(1) RθJA = 50 on 1 in² Cu (2 oz.) on 0.060" thick FR4 PCB(2) Pulse duration 10 μs, duty cycle ≤2%

RDS(on) vs VGS Gate Charge

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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CSD17571Q2SLPS393A –OCTOBER 2013–REVISED JANUARY 2015 www.ti.com

Table of Contents1 Features .................................................................. 1 6 Device and Documentation Support.................... 7

6.1 Trademarks ............................................................... 72 Applications ........................................................... 16.2 Electrostatic Discharge Caution................................ 73 Description ............................................................. 16.3 Glossary .................................................................... 74 Revision History..................................................... 2

7 Mechanical, Packaging, and Orderable5 Specifications......................................................... 3Information ............................................................. 85.1 Electrical Characteristics........................................... 37.1 Q2 Package Dimensions .......................................... 85.2 Thermal Information .................................................. 37.2 Q2 Tape and Reel Information................................ 105.3 Typical MOSFET Characteristics.............................. 4

4 Revision History

Changes from Original (October 2013) to Revision A Page

• Updated Figure #8.................................................................................................................................................................. 6

2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: CSD17571Q2

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CSD17571Q2www.ti.com SLPS393A –OCTOBER 2013–REVISED JANUARY 2015

5 Specifications

5.1 Electrical CharacteristicsTA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTATIC CHARACTERISTICSBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA 30 VIDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 μAIGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nAVGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 1.3 1.6 2 V

VGS = 4.5 V, IDS = 5 A 24 29 mΩRDS(on) Drain-to-Source On-Resistance VGS = 10 V, IDS = 5 A 20 24 mΩgƒs Transconductance VDS = 15 V, IDS = 5 A 43 SDYNAMIC CHARACTERISTICSCISS Input Capacitance 360 468 pFCOSS Output Capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 101 131 pFCRSS Reverse Transfer Capacitance 9 12 pFRg Series Gate Resistance 3.8 7.6 ΩQg Gate Charge Total (4.5 V) 2.4 3.1 nCQgd Gate Charge – Gate-to-Drain 0.6 nCVDS = 15 V, IDS = 5 AQgs Gate Charge Gate-to-Source 0.9 nCQg(th) Gate Charge at Vth 0.6 nCQOSS Output Charge VDS = 15 V, VGS = 0 V 3.4 nCtd(on) Turn On Delay Time 5.3 nstr Rise Time 19 nsVDS = 15 V, VGS = 4.5 V, IDS = 5 A

RG = 2 Ωtd(off) Turn Off Delay Time 8 nstƒ Fall Time 2.6 nsDIODE CHARACTERISTICSVSD Diode Forward Voltage IDS = 5 A, VGS = 0 V 0.8 1 VQrr Reverse Recovery Charge 2.3 nCVDD = 15 V, IF = 5 A, di/dt = 300 A/μstrr Reverse Recovery Time 11 ns

5.2 Thermal InformationTA = 25°C unless otherwise specified

THERMAL METRIC MIN TYP MAX UNITRθJC Junction-to-Case Thermal Resistance (1) 6.2 °C/WRθJA Junction-to-Ambient Thermal Resistance (1) (2) 65

(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s boarddesign.

(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.

Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 3



GATE Source

DRAIN

N-Chan

M0164-01

GATE Source

DRAIN

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Max RθJA = 65 when Max RθJA = 235 whenmounted on 1 inch2 mounted on minimum(6.45 cm2) of 2 oz. pad area of 2 oz.(0.071 mm thick) Cu. (0.071 mm thick) Cu.

5.3 Typical MOSFET CharacteristicsTA = 25°C unless otherwise specified

Figure 1. Transient Thermal Impedance




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Typical MOSFET Characteristics (continued)TA = 25°C unless otherwise specified

Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics

Figure 4. Gate Charge Figure 5. Capacitance

Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage




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Typical MOSFET Characteristics (continued)TA = 25°C unless otherwise specified

Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage

Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching

Figure 12. Maximum Drain Current vs Temperature





6 Device and Documentation Support

6.1 TrademarksNexFET is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

6.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

6.3 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.



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M0165-01

D

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7 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

7.1 Q2 Package Dimensions

DIM MILLIMETERS INCHESMIN NOM MAX MIN NOM MAX

A 0.700 0.750 0.800 0.028 0.030 0.032A1 0.000 0.050 0.000 0.002b 0.250 0.300 0.350 0.010 0.012 0.014C 0.203 TYP 0.008 TYPD 2.000 TYP 0.080 TYP

D1 0.900 0.950 1.000 0.036 0.038 0.040D2 0.300 TYP 0.012 TYPE 2.000 TYP 0.080 TYPE1 0.900 1.000 1.100 0.036 0.040 0.044E2 0.280 TYP 0.0112 TYPE3 0.470 TYP 0.0188 TYPe 0.650 BSC 0.026 TYPK 0.280 TYP 0.0112 TYPK1 0.350 TYP 0.014 TYPK2 0.200 TYP 0.008 TYPK3 0.200 TYP 0.008 TYPK4 0.470 TYP 0.0188 TYPL 0.200 0.25 0.300 0.008 0.010 0.012





7.1.1 Recommended PCB Pattern

For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing ThroughPCB Layout Techniques.

7.1.2 Recommended Stencil Pattern

Note: All dimensions are in mm, unless otherwise specified.



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2.00 ±0.05 Ø 1.50 ±0.10

1.7

5 ±

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Ø 1.00 ±0.25

M0168-01

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10° Max

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2.30 ±0.05

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7.2 Q2 Tape and Reel Information

Notes: 1. Measured from centerline of sprocket hole to centerline of pocket2. Cumulative tolerance of 10 sprocket holes is ±0.203. Other material available4. Typical SR of form tape Max 109 OHM/SQ5. All dimensions are in mm, unless otherwise specified.




PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

CSD17571Q2 ACTIVE WSON DQK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 1751

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated

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1 Features2 Applications3 DescriptionTable of Contents4 Revision History5 Specifications5.1 Electrical Characteristics5.2 Thermal Information5.3 Typical MOSFET Characteristics

6 Device and Documentation Support6.1 Trademarks6.2 Electrostatic Discharge Caution6.3 Glossary

7 Mechanical, Packaging, and Orderable Information7.1 Q2 Package Dimensions7.1.1 Recommended PCB Pattern7.1.2 Recommended Stencil Pattern

7.2 Q2 Tape and Reel Information

SLPS393A –OCTOBER 2013–REVISED JANUARY 2015 ...SLPS393A –OCTOBER 2013–REVISED JANUARY 2015 7...

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