Sidewall Image Transfer Technology

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Sidewall Image Transfer Technology. Bobby Schneider. Outline. What is Sidewall Image Transfer (SIT)? Methods A, B, C What has this been used for? 0.026 μ m² SRAM cell SIT & the future. What is Sidewall Image Transfer?. A processing method - PowerPoint PPT Presentation

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Sidewall Image Transfer Lithography

Sidewall Image Transfer Technology

Bobby SchneiderOutlineWhat is Sidewall Image Transfer (SIT)?Methods A, B, CWhat has this been used for?0.026 m SRAM cellSIT & the future

What is Sidewall Image Transfer?A processing methodSIT uses optical lithography to obtain sub-resolution linewidths! (e.g. 20 nm)

Will be used in next-gen CMOS processing22 nm and beyondUseful for making finFETs

Pattern photoresist (PR)

Deposit a thin conformal film (e.g. 30 nm)

Do a short anisotropic etch

Strip the PRSidewall Image Transfer Method A(The easiest method)Microlithography: science and technologyBy Kazuaki Suzuki, Bruce W. Smith SIT forms closed loopsNot flatSIT Design ConsiderationUses two masks Collar (makes closed loops)Trim (to define lines)Collar maskResultTrim maskPitchLine-widthSidewall Image Transfer Method B(Furukawa et al.)Width defined by HF etch duration(e.g. 20 nm)Si Substrate SiO2Poly-SiSi3N4Tungsten (W)Sidewall Image Transfer Method B(Furukawa et al.)Width defined by HF etch duration(e.g. 20 nm)Si Substrate SiO2Poly-SiSi3N4Tungsten (W)Sidewall Image Transfer Method B(Furukawa et al.)Si Substrate SiO2Poly-SiSi3N4Tungsten (W)SIT Method B Result(Furukawa et al.)Si Substrate SiO2Poly-SiSi3N4Tungsten (W)Small pitch(40 nm pitch possible)Narrow line-width(12 nm width possible)No feetSidewall Image Transfer Method C(Furukawa et al.)Si Substrate SiO2Poly-SiSi3N4Photoresist (PR)Germanium (Ge)Sidewall Image Transfer Method C(Furukawa et al.)Si Substrate SiO2Poly-SiSi3N4Photoresist (PR)Germanium (Ge)Sidewall Image Transfer Method C(Furukawa et al.)Si Substrate SiO2Poly-SiSi3N4Photoresist (PR)Germanium (Ge)SIT Method C Result(Furukawa et al.)Small pitch(40 nm pitch possible)Narrow line-width(12 nm width possible)Si Substrate SiO2Poly-SiSi3N4Photoresist (PR)Germanium (Ge)No feetHow has SIT been used?

the smallest FinFET SRAM cell size of 0.063 m reported to date using optical lithography. (Basker et al. 2010)

How has SIT been used? (Ctd.)

How has SIT been used? (Ctd.)FinFET PerformanceSIT & The FutureCMOS Transitions to 22 and 15 nmDavid Lammers, News Editor -- Semiconductor International, 1/1/2010Scott Thompson, a former Intel technology manager who now teaches at the University of Florida at Gainesville, believes Intel will adopt a tri-gate structure at some point, while the rest of the industry will shy away from the manufacturing challenges of finFETs.

I believe most people in the industry would agree that finFET processing is more difficult. Lithography is a huge challenge, though people can overcome that with sidewall image transfer.-Bruce Doris, manager of advanced device integration at IBM's Albany, N.Y., R&D centerTakeawaysThings to remember:Sidewall image transfer (SIT) uses optical lithography to achieve very narrow linewidths12 nm linewidths achieved, 40 nm pitch2 masks: Collar & TrimLinewidth controlled by etch distance of sidewallSIT will possibly be used at the 15 nm node of CMOS by Intel

Thank you!Thats all.