SEQUENTIAL LOGIC - University of California,...

Digital Integrated Circuits © Prentice Hall 1995Sequential Logic

SEQUENTIAL LOGIC


Sequential Logic

FF’s

LOGIC

tp,comb

φ

InOut

2 storage mechanisms• positive feedback

• charge-based


Positive Feedback: Bi-Stability

Vi1

Vo1=Vi2Vo2

Vi1 Vo2

Vo1

Vi2

= V

o1

Vi2

= V

o1

Vi1 = Vo2

A

C

B


Meta-StabilityV

i2 =

Vo1

Vi1 = Vo2

C

Vi2

= V

o1

Vi1 = Vo2

B

δ δ

Gain should be larger than 1 in the transition region


SR-Flip Flop

S

R

QS

R Q

S R Q Q

0101

0011

Q100

Q010

S

R

Q

Q

QS

R Q

S R Q Q

1010

1100

Q101

Q011

Q

Q


JK- Flip Flop

S

R

Q

Q Q

J

K

φ

QJ

K Q

Jn Kn Qn+1

0011

0101

Qn01Qn

(b)

(c)

Q

(a)φ


Other Flip-Flops

QJ

K Qφ

T

φQJ

K Qφφ

D

Q

Qφ

T Q

Qφ

D

Toggle Flip-Flop Delay Flip-Flop


Race Problem

Q

Qφ

D

1

t

t

tloop

φ

Signal can race around during φ = 1


Master-Slave Flip-Flop

S

R

Q

Q Q

QS

R

Q

Q

J

K

φ

MASTER SLAVE

QJ

K Qφ

PRESET

CLEAR

SI

RI


Propagation Delay Based Edge-Triggered

φ

In XN2

N1

Out

φ

In

X

Out

tpLH

= Mono-Stable Multi-Vibrator


Edge Triggered Flip-Flop

φ

S

R

Q

Q

Q

J

K

Q

QJ

KQ

>φ


Flip-Flop: Timing Definitions

DATA

STABLE

DATASTABLE

In

Out

t

t

t

φ

tsetup thold

tpFF


Maximum Clock Frequency

FF’s

LOGIC

tp,comb

φ


CMOS Clocked SR- FlipFlop

VDD

Q

Q

RS

φφM1 M3

M4M2

M6

M5 M7

M8


Flip-Flop: Transistor Sizing

0.0 1.0 2.0 3.0 4.0 5.00.0

2.0

4.0

VQ

(1.8/1.2)(3.6/1.2)(7.2/1.2)


6 Transistor CMOS SR-Flip Flop

VDD

QQ

φ

M1 M3

M4M2

M5R

φ

S


Charge-Based Storage

D

D

φ

φ

In

φ

φ

(a) Schematic diagram

(b) Non-overlapping clocks

Pseudo-static Latch


Master-Slave Flip-Flop

φ

φ

φ

φ D

InA

B

φ

φ

Overlapping Clocks Can Cause

• Race Conditions

• Undefined Signals


2 phase non-overlapping clocks

φ2

φ1

φ1

φ2 D

In

φ1

φ2

tφ12


2-phase dynamic flip-flop

φ2φ1

DIn

Input Sampled

Output Enable

φ1

φ2


Flip-flop insensitive to clock overlap

DIn

φ

φ φ

φ

VDDVDD

M1

M3

M4

M2 M6

M8

M7

M5

φ− section φ− section

CL1 CL2

X

C2MOS LATCH


C2MOS avoids Race Conditions

DIn

1

M1

M3

M2 M6

M7

M5

1

DIn

VDDVDD

M1

M4

M2 M6

M8

M5

0 0

VDDVDD

(a) (1-1) overlap (b) (0-0) overlap

X X


PipeliningR

EG

φ

RE

G

φR

EG

φ

log.

RE

G

φ

RE

G

φ

RE

G

φ

.

RE

G

φ

RE

G

φ

logOut Out

a

b

a

b

Non-pipelined version Pipelined version


Pipelined Logic using C2MOS

InF Out

φ

φ

VDD

φ

φ

VDD

φ

φ

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?


Example

1

φ

φ

VDD

φ

φ

VDDVDD

Number of a static inversions should be even


NORA CMOS Modules

φ

φ

VDDVDD

PDN

φ

In1In2In3

φ

VDD

PUN

φ

φ

Out

φ

φ

VDD

Out

VDD

PDN

φ

In1In2In3

φ

VDD

In4

In4

VDD

(a) φ-module

(b) φ-module

Combinational logic Latch


Doubled C2MOS Latches

φ

VDD

Out

φ

VDD

Doubled n-C2MOS latch

Inφ

VDD

Outφ

VDD

Doubled n-C2MOS latch

In


TSPC - True Single Phase Clock Logic

φ

VDD

Outφ

VDD

φ

VDD

φ

VDD

InStaticLogic

PUN

PDN

Including logic into

the latch

Inserting logic between

latches


Master-Slave Flip-flops

φ

VDD

D

VDD

φ

VDD

D

φ

VDD

φ

VDD

D

VDD

φ

φ

Dφ

VDD

φ

VDD

D

VDD

φ

φD

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY


Schmitt Trigger

In Out

Vin

Vout VOH

VOL

VM– VM+

•VTC with hysteresis

•Restores signal slopes


Noise Suppression usingSchmitt Trigger

VM+

VM–

VoutVin

t tt0 t0 + tp


CMOS Schmitt TriggerVDD

Vin Vout

M1

M2

M3

M4

X

Moves switching thresholdof first inverter


Schmitt TriggerSimulated VTC

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

0.0

1.0

2.0

3.0

4.0

5.0

VX (V

)

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

0.0

2.0

4.0

6.0

Vou

t (V

)

VM-

VM+


CMOS Schmitt Trigger (2)

In

VDD

VDD

Out

M1

M2

M3

M4

M5

M6

X


Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T


Transition-Triggered Monostable

DELAY

td

In

Outtd


Monostable Trigger (RC-based)

VDD

InOutA B

C

R

In

B

Out t

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.


Astable Multivibrators (Oscillators)

0 1 2 N-1

0 1 2 3 4 5

t (nsec)

-1.0

1.0

3.0

5.0

V (

Vol

t)

V1 V3 V5

Ring Oscillator

simulated response of 5-stage oscillator


Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pH

L (n

sec)

propagation delay as a functionof control voltage


Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC

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