RMO4C-2 A Low-Noise 40-GS/s Continuous-Time Bandpass ӣ ADC Centered at 2 GHz Theo...

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Transcript of RMO4C-2 A Low-Noise 40-GS/s Continuous-Time Bandpass ӣ ADC Centered at 2 GHz Theo...

  • RMO4C-2A Low-Noise 40-GS/sContinuous-Time Bandpass ADCCentered at 2 GHz Theo Chalvatzis and Sorin P. Voinigescu The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of TorontoToronto, Canada

    RFIC - San Francisco June 11-13, 2006

  • OutlineMotivationADC system level architectureCircuit designMeasurementsConclusion

    RFIC - San Francisco June 11-13, 2006

  • MotivationDirect sampling receiver for 2-GHz CDMA basestationTransistor fT of 150..250 GHz and low-BVCEO naturally point to 1-bit digitization of RF signalContinuous-Time Bandpass topology offers:Higher resolution and lower power than other ADC typesLow complexity (simple layout is important at 40 GHz!)LNA as input stage

    RFIC - San Francisco June 11-13, 2006

  • System Level Architecture2-GHz Gm-LC BPF 1-bit quantizer as DFFRZ pulse DACsLoop design in s-domainDAC(s) the TF of RZ DACLNA & BPF1BPF2

    RFIC - San Francisco June 11-13, 2006

  • New Loop Filter TopologyMOS-HBT cascode provides:Linearity and low-noise with no degenerationLower power supply (VGS
  • New RZ DAC TopologyDAC with RZ pulse for immunity against loop delayHigher switching speed due to MOS-HBT cascodeHigh gm/ITAIL ratio (due to HBT)

    RFIC - San Francisco June 11-13, 2006

  • New 40-GHz Quantizer TopologyMOS-HBT MSM flip-flop:3 latches to compensate for metastabilityMOS on clock path to improve speed with low supply HBT on data path for high gainMin swing at quantizer input: 10mVpp3 stages needed for full logic swing (300mVpp) at DAC input

    RFIC - San Francisco June 11-13, 2006

  • 40-GHz Bandwidth Clock DistributionExternal clock distributed to 3 latches and 2 DACsEF-MOS-HBT cascode for increased bandwidth and large capacitive load drive

    RFIC - San Francisco June 11-13, 2006

  • Fabrication and Characterization of loop filter breakout and ADC

    RFIC - San Francisco June 11-13, 2006

  • ADC Die PhotographADC and filter breakout fabricated in STMs 0.13m SiGe BiCMOS:HBT fT/fmax=150/160 GHz2m finger width n-MOSFET fT/fmax=80/90 GHzTotal power dissipation 1.6W from 2.5V

    1.52x1.58mm2

    RFIC - San Francisco June 11-13, 2006

  • Loop Filter MeasurementsLinearity and noise measured on a filter test structureOptimum bias point for maximum linearity: 0.4mA/m

    RFIC - San Francisco June 11-13, 2006

  • ADC S-parametersQ=17 and BW3dB=120MHzADC stable up to 65GHzS22
  • ADC Spectrum MeasurementsNo idle tones present in-band Inset shows > 35dB/dec noise shapingSingle-tone at 2-GHz ONSingle-tone at 2-GHz OFF

    RFIC - San Francisco June 11-13, 2006

  • ADC SNDR MeasurementsSNDR measured with Spectrum AnalyzerResolution BW lowered until noise floor remained constant (RBW < 50 KHz)Measurements taken for bandwidths between 1 MHz and 120 MHz

    RFIC - San Francisco June 11-13, 2006

  • ADC SNDR vs BW MeasurementsSNDR=55dB over 60 MHzSNDR=52dB over 120 MHz

    RFIC - San Francisco June 11-13, 2006

  • ADC SFDR Two-Tone MeasurementsTwo-tone test with 2 GHz RF inputs at 10 MHz spacingPIN= -30dBmSFDR=61dB

    RFIC - San Francisco June 11-13, 2006

  • ADC 40-Gb/s Eye Diagram Jitter Measurements2-GHz input sinusoidFeedback turned-offJitterRMS=375fsJitter does not affect ADC resolution

    RFIC - San Francisco June 11-13, 2006

  • ADC PerformanceFigure of Merit (FOM) definition (lower better):

    RFIC - San Francisco June 11-13, 2006

    Sheet1

    Center Frequency2 GHz

    Clock Rate40 GHz

    OSR333

    SNDR55dB/60MHz

    52dB/120MHz

    SFDR61 dB

    Power Supply2.5 V

    Power Dissipation1.6 W

    FOM18 pJ/bit

    Sheet2

    Sheet3

    Sheet1

    RefProcessFs (GHz)Fc (GHz)BW (MHz)SNDR (dB)FOM (pJ/bit)

    [2] (BP)Si3.80.950.2491473

    [3] (BP)InP3.20.82541400

    [4] (BP)InP416047.4135

    [6] (LP)InP8-62.557.424

    This workSiGe BiCMOS402605526

    4021205218

    Sheet2

    Sheet3

  • ConclusionFirst mm-wave sampling ADC in any technology (> 2xFs)Direct RF A/D Conversion at 2-GHz with 9-bit resolution over 60 MHz11 bits over 60 MHz possible in this topology with:Improved filter linearityHigher filter QBest FOM among all ADCs with clocks > 1 GHz40-48 GS/s design scalable to 3.5/5/12 GHz

    RFIC - San Francisco June 11-13, 2006

  • AcknowledgementsEric Gagnon and Morris Repeta for system performance specificationsNortel Networks for funding supportSTMicroelectronics for chip fabricationECTI for lab accessCMC for CAD tools

    RFIC - San Francisco June 11-13, 2006