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  • IBM Research

    © 2009 IBM Corporation

    1

    Reliability of advanced CMOS devices and circuits

    James H. Stathis IBM Thomas J. Watson Research Center Yorktown Heights, NY

  • IBM Research

    © 2009 IBM Corporation2

    p substrate, doping α*NA L/α xd/α

    GATE n+ source

    n+ drain

    WIRINGVoltage, V / α

    W/α tox/α

    CMOS Scaling Rules

    SCALING: Voltage: V/α Oxide:Oxide: ttox ox //αα Wire width: W/α Gate width: L/α Diffusion: xd /α Substrate: αNA

    RESULTS: Higher Density: ~α2

    Higher Speed: ~α Power/ckt: ~1/α2

    Power Density:Power Density: ~Constant~Constant

    R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).

    tox scaling required for short channel control

  • IBM Research

    © 2009 IBM Corporation3

    p substrate, doping α*NA L/α xd/α

    GATE n+ source

    n+ drain

    WIRINGVoltage, V / α

    W/α tox/α

    CMOS Scaling Rules

    SCALING: Voltage: V/α Oxide:Oxide: ttox ox //αα Wire width: W/α Gate width: L/α Diffusion: xd /α Substrate: αNA

    RESULTS: Higher Density: ~α2

    Higher Speed: ~α Power/ckt: ~1/α2

    Power Density:Power Density: ~Constant~Constant

    R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).

    11Å

    tox scaling required for short channel control

  • IBM Research

    © 2009 IBM Corporation4

    p substrate, doping α*NA L/α xd/α

    GATE n+ source

    n+ drain

    WIRINGVoltage, V / α

    W/α tox/α

    CMOS Scaling Rules

    SCALING: Voltage: V/α Oxide:Oxide: ttox ox //αα Wire width: W/α Gate width: L/α Diffusion: xd /α Substrate: αNA

    RESULTS: Higher Density: ~α2

    Higher Speed: ~α Power/ckt: ~1/α2

    Power Density:Power Density: ~Constant~Constant

    R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).

    Approaching atomistic and quantum-mechanical boundaries Atoms are not scalable!

    11Å

    tox scaling required for short channel control

  • IBM Research

    © 2009 IBM Corporation5

    Device Scaling

    Conventional bulk device or partially-depleted SOI (PDSOI) – Aggressive gate dielectric

    scaling for improved short channel control

    – Increased random doping fluctuations due to width and length scaling

    – Spacer thickness decreasing • Becoming comparable to old

    gate dielectric thickness (~10nm)

    50-65

    65-80

    80-100

    120-130

    170-180

    Device Pitch (nm)

    15

    22

    11

    32

    45

    Node

    Extension

    Si substrate

    Extension

    BOX

    Halo

    Poly Gate

    NiSi

    Band- edge gate

    NiSi

    Gate Oxide

    tSi

    NiSi Extension

    Embedded Stressor

    SOI

  • IBM Research

    © 2009 IBM Corporation6

    CMOS Scaling: Oxide electric field increasing

    Field driven wearout

    increasing

    4 6 8 10

    100 65 nm

    45 nm

    350 nm

    - Δ V m

    ax (

    m V)

    Eoxide (MV/cm)

    estimated NBTI at 10 years

    source: IEDM and VLSI Eox = (Vgate / telectrical) = (CV/ε)

    1980 1985 1990 1995 2000 2005 0

    1

    2

    3

    4

    5

    6

    7

    8

    9

    10

    Fi el

    d (M

    V /c

    m )

    year published

  • IBM Research

    © 2009 IBM Corporation7

    Major MOSFET oxide failure mechanisms

    Bias/Temperature Instability – NBTI

    – PBTI

    Dielectric Breakdown

  • IBM Research

    © 2009 IBM Corporation8

    Negative-bias-temperature instability

  • IBM Research

    © 2009 IBM Corporation9

    VDD

    0v VDD

    pFET on-state

    Negative-bias-temperature instability

    Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate.

  • IBM Research

    © 2009 IBM Corporation10

    Thermal activation (~0.2eV)VDD

    0v VDD

    pFET on-state

    Negative-bias-temperature instability

    Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate.

  • IBM Research

    © 2009 IBM Corporation11

    Believed to be caused by an electrochemical reaction with a hydrogen related species in the oxide, reacting with holes in the pfet channel. First described by Miura and Matukura. Jpn. J. Appl. Phys., vol. 5, p. 180, 19661966.

    Thermal activation (~0.2eV)VDD

    0v VDD

    pFET on-state

    Negative-bias-temperature instability

    Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate.

  • IBM Research

    © 2009 IBM Corporation12

    Negative-bias-temperature instability (NBTI)

    Basic features:

    – PFET threshold voltage shift • negative threshold voltage (Vt) shift • interface states and positive oxide charge

    drive current reduction circuit speed reduction

    – Power law time dependence

    – Nitrided oxide has larger shift and shallower slope • Nitridation of gate oxide makes it worse

    “The Negative Bias Temperature Instability in MOS Devices: A Review”, J.H. Stathis and S. Zafar, Microelectronics Reliability, 46, 270-286 (2006).

    0 4x104 8x104 0.00

    0.01

    0.02

    nitrided oxide SiO2-Δ

    V t (

    V )

    time (sec)

    (a)

    101 102 103 104 105 10-4

    10-3

    10-2

    10-1

    (b)

    nitrided oxide SiO2

    -Δ V

    t ( V

    )

    time (sec)

  • IBM Research

    © 2009 IBM Corporation13

    “PBTI” in high-k NFET

    “PBTI” is a Vt shift observed under positive bias (i.e., in n-FET) – Not seen in SiO2/poly under normal

    use conditions

    – Charge trapping in high-k layer

    -3 -2 -1 0 1 2 3 10-3

    10-2

    10-1

    SiO2/HfO2/TiN (tHfO2= 2.2 nm)

    SiON/poly-Si (tSiON= 1.3 nm)

    SiON/poly-Si (tSiON= 1.3 nm)

    NBTI

    2.2nm

    ab s( Δ

    V t ) a

    t 1 00

    s (V

    )

    Vg-VT (V)

    PBTI

    0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.00

    0.02

    0.04

    0.06

    0.08

    0.10

    0.12

    0.14

    0.16

    Vg = 1.8 V

    Vg = 2.2 V

    ΔV t @

    Q in

    j = 1

    03 C

    /c m

    2 ( V

    )

    HfO2 Thickness, tHfO2 (nm)

    A. Kerber et al., to be published, IEEE Trans. Dev. and Mater. Reliab.

    S. Pae et al., IRPS 2008.

  • IBM Research

    © 2009 IBM Corporation14

    NBTI and PBTI in SRAM

    Static noise margin analysis (butterfly curve)

    VDD

    PR PL

    NRNL

    BL BR

    WL

    ‘0’ ‘1’

    NBTI

    PBTI

    ‘1’ ‘1’

    ‘1’

    AXL AXRVRVL

  • IBM Research

    © 2009 IBM Corporation15

    Effect of PBTI on SRAM

    Vt increase in both nfets – SNM better than asymmetric case – Not worst-case

    Vt increase in one nfet – Worst case degradation,

    SNM decreases

    J.C. Lin, et al., IRPS 2007.

    Initial SNM

  • IBM Research

    © 2009 IBM Corporation16

    Effect of combined NBTI & PBTI

    Relative sensitivity: – SRAM cell is ~2x more

    sensitive to PBTI compared to NBTI

    Symmetric degradation of cells leads to little increase in failure probability – Worst case is asymmetric

    PBTI degradation

    0 0.5 1 1.5 2 2.5 0.8

    1

    1.2

    1.4

    1.6

    1.8

    2

    2.2

    WPR:WNL

    ( δ S

    N M

    / δ V t

    ,P R

    ):( δS

    N M

    / δ V t

    ,N L)

    Typical design corner

    (Δ SN

    M / Δ

    V t ,P

    B TI

    ) :

    (Δ SN

    M / Δ

    V t ,N

    B TI

    )

    WPL,PR : WNL,NR 0 0.5 1 1.5 2 2.5

    0.8

    1

    1.2

    1.4

    1.6

    1.8

    2

    2.2

    WPR:WNL

    ( δ S

    N M

    / δ V t

    ,P R

    ):( δS

    N M

    / δ V t

    ,N L)

    Typical design corner

    (Δ SN

    M / Δ

    V t ,P

    B TI

    ) :

    (Δ SN

    M / Δ

    V t ,N

    B TI

    )

    WPL,PR : WNL,NR

    0 20 40 60 80 1000.1

    1

    10

    100

    1,000

    ΔVt,NL [mV]

    # of

    fa ul

    ty c

    el ls

    in 1

    00 M

    B m

    em or

    y

    ΔVt,PR=0

    ΔVt,PR=50mV

    ΔVt,PR=100mV

    Worst case

    Sym. effect

    T=85oC and Vdd=0.9V

    0 20 40 60 80 1000.1

    1

    10

    100

    1,000

    ΔVt,NL [mV]

    # of

    fa ul

    ty c

    el ls

    in 1

    00 M

    B m

    em or

    y

    ΔVt,PR=0

    ΔVt,PR=50mV

    ΔVt,PR=100mV

    Worst case