Problem for Problems for Discrete Transistor...

Problem for Problems for Discrete Transistor Amplifiers

ECE 65, Winter2013, F. Najmabadi

F. Najmabadi, ECE65, Winter 2013, Problems for Discrete Amplifiers (2/42)

Exercise 1: Find the amplifier parameters of the circuit below. (Si BJT with β = 200, VA = 150 V, ignore Early effect in bias calculations).

This is a common collector amplifier (emitter follower) . o Input at the base, output at the emitter.

It has a emitter-degeneration bias with a voltage divider.

When Rsig & vsig are not given, it implies that vsig = vi and Rsig = 0


Bias circuit Thevenin form of the Voltage divider

V 95.49k 18k 22

k 22

k 90.9k 18||k 22

=×+

=

==

BB

B

V

R

Real circuit

Exercise 1 (cont’d): β = 200, VA = 150 V.


Bias Calculations

A 3.20/ mA 05.4

107.0)1/(109.9 4.95

4.95 :KVLBE33

µβ

β

==≈=

+++×=

++=−

CB

CE

EE

EEBEBB

IIII

IIRIVRI

V 7.0 and 0 V, 7.0: Activein is BJT Assume

≥>= CECBE VIV

V 0.7 V 5 10104 9

9 :KVLCE

0

33

=>=××+=

+=−−

DCE

CE

EECE

VVV

RIV

V 95.4k 9.9 == BBB VR

k 28.1 r

k 0.3710x 4

150r

mA/V 156 1026104.05

3o

3

3

===

==≈

=××

==

mB

T

-C

A

-

-

T

Cm

gIVIVVIg

βπ

Thevenin form of the Voltage divider



11511

15115196510156)||||(

965k100||k1||k8.38)||||()||||(1

)||||(

3

≈+

=

=××=

Ω==+

=

−

i

o

LEom

LEo

LEom

LEom

i

o

vv

RRrgRRr

RRrgRRrg

vv

k 28.1 k, 8.38 mA/V, 156 === πom rrg

[ ][ ] k 9.9k194k3.1 ||k9.9

)||||( || ≈+=

+=

i

LEoBi

RRRrrRR βπ

Ω==+

= 4.6||||

||ββππ rR

RRrRR E

sigBEo


Signal circuit (IVC = 0)

Amplifier Parameters Emitter Follower

1==×+

=i

o

i

o

sigi

i

sig

o

vv

vv

RRR

vv


Ω==

4.6k9.9

o

i

RR

k 28.1k 8.38mA/V 156

===

π

o

m

rrg

Hz 39.31047.0)10100(6.4 2

1

)( 21

Hz 2.341047.0)0109.9( 2

1

)( 21

632

22

631

11

=×××+

=

+=

=××+×

=

+=

−

−

π

π

π

π

p

cLop

p

csigip

f

CRRf

f

CRRf

Hz 6.374.32.34 21 =+=+≈ ppp fff


Amplifier Cut-off frequency 2 caps: 2 poles


This is a common emitter amplifier with RE . o Input at the base, output at the collector.

It has a emitter-degeneration bias with a voltage divider.



Bias calculations Thevenin form of the Voltage divider

A 2.14/ mA 84.2

5107.0)1/(100.5 2.22

2.22 :KVLBE3

µβ

β

==≈=

+++×=

++=−

CB

CE

EE

EEBEBB

IIII

IIRIVRI


≥>= CECBE VIV

V 0.7 V 5.10 )51010(1084.215

15 :KVLCE

0

33

=>=+××+=

++=−−

DCE

CE

EECECC

VVV

RIVRI

k 83.1 r

k 8.5210 84.2

150r

mA/V 10.9 1026102.84

3o

3

3

===

=×

=≈

=××

==

mB

T

-C

A

-

-

T

Cm

gIVIVVIg

βπ

Exercise 2 (cont’d): β = 200, VA = 150 V

Bias circuit Caps open

V 22.215k 9.5k 34

k 9.5

k 0.5k 9.5||k 34

=×+

=

==

BB

B

V

R


k 83.1 k, 8.52 mA/V, 10.9

===

πo

m

rrg

Amplifier Parameters CE amplifier with RE

k 8.4104k ||k 0.5)/1](/)||[(1

||

==

++

+=

i

EoLC

EBi

RrRrRR

RrRRπ

πβ

64.1

0.990kk 100||k 1||)/1](/)||[(1

)||(

−=

==+++

−=

i

o

LC

EoLCEm

LCm

i

o

vv

RRrRrRRRg

RRgvv

π

k 0.1

||1 ||

=≈

+++≈

Co

sigBE

EoCo

RR

RRRrRrRR

π

β

59.1)64.1(100800,4

800,4−=−×

+=×

+=

i

o

sigi

i

sig

o

vv

RRR

vv




k 0.1 k 8.4 == oi RR

Amplifier Cut-off frequency (2 caps: 2 poles)

Hz 8.1510100)1010010( 2

1

)( 21

Hz 91.6107.4)100108.4( 2

1

)( 21

9332

22

631

11

=×××+

=

+=

=××+×

=

+=

−

−

π

π

π

π

p

cLop

p

csigip

f

CRRf

f

CRRf

Hz 7.228.159.6 21 =+=+≈ ppp fff

k 83.1r k 8.52rmA/V 10.9

o ===

π

mg




This is a PNP common emitter amplifier (no RE ). o Input at the base, output at the collector (RE is shorted

out for signal because of the by-pass capacitor)

It has a emitter-degeneration bias with two voltage sources (RB = ∞)


Exercise 3 (cont’d). β = 200, VA = 150 V.

Bias circuit (Signal = 0, Caps open)

A 0.5/ mA 0.1

100103.2 3 :KVLBE 3

µβ ==≈=

++×=−

CB

CE

BEBE

IIII

IVI


≥>= ECCEB VIV

V 0.7 V 4.1 10106.46

3103.2103.23 :KVLCE

0

33

33

=>=××−=

−×++×=−−

DEC

EC

CECE

VVV

IVI

k 26.5 r

k 15010150r

mA/V 38.5 1026

10

3-o

3-

-3

===

==≈

=×

==

mB

T

C

A

T

Cm

gIVIVVIg

βπ


3.85)k 100||k 3.2||k 150(1038.5

)||||(

3 −=×−=

−=

−

i

o

LComi

o

vv

RRrgvv

k 26.5 k, 150 mA/V, 38.5 === πom rrg

Amplifier Parameters 1) CE amplifier with no RE 2) No voltage divider biasing: no RB

RB is open circuit, RB = ∞

k 27.2k 3.2||k 150 ||

===

o

oCo

RrRR

k 26.5 || === ππ rrRR Bi


3.85−=≈×+

=i

o

i

o

sigi

i

sig

o

vv

vv

RRR

vv

isig RR <<




k 26.5r k 150r

mA/V 38.5

o

===

π

mg

Hz 1451298.150321 =++=++≈ pppp ffff


k 27.2 k 26.5

==

o

i

RR

Amplifier Cut-off frequency 1) 2 caps: 2 poles 2) no coupling capacitors at the input

0)( 2

1

11 =

+=

csigip CRR

fπ

Hz 1291047)5.26||10(2.3 2

1

]/)||(/1[|| 21

633

3

=×××

=

+=

−π

βπ

p

EsigBmEp

f

CRRgRf

Hz 8.1510100)1010(2.3 2

1)( 2

1

9532

22

=××+×

=

+=

−π

π

p

cLop

f

CRRf


This is a MOS common source amplifier (no RS ). o Input at the gate, output at the drain (RS is shorted

out for the signal because of the by-pass capacitor)

It has a source-degeneration bias with a voltage divider.

Exercise 4: Find the amplifier parameters of this circuit. (µnCox = 100 µA/V2, (W/L) = 6/0.1, Vt = 0.5 V, λ = 0.1 V-1. Assume capacitors are large and ignore channel width modulation in biasing. )


V 353.18.110033

100V 0 G =+

=⇒=kk

kIG

Assume Saturation

232 10x3 5.0 OVOVoxnD VVL

WCI −== µ

V 803.0=+= tOVGS VVV

Saturation ⇒> OVDS VV

mA 275.010x3 23 == −OVD VI

V 550.0=−= GSGS VVV

V 249.18.1 =−= DDD IRV

V 699.0=−= SDDS VVV

V 303.0=OVV

DStOVDSGSG IRVVIRVV ++=+=

233 103 102 5.0353.1 OVOV VV −×××++=

0853.06 2 =−+ OVOV VV

GS-KVL:

Exercise 4 (cont’d): µnCox = 100 µA/V2, (W/L) = 6/0.1, Vt = 0.5 V, λ = 0.1 V-1.


k 3.3610 752.01.0

11r

mA/V 1.82 0.303

10 0.275 2 2

3o

3

=××

==

=××

==

-D

-

OV

Dm

I

VIg

λ


32.3)k 50||k 2||k 3.36(101.82

)||||(

3 −=×−=

−=

−

i

o

LDomi

o

vv

RRrgvv

Amplifier Parameters This is a CS amplifier with no RS

k 90.1k 2||k 3.36 ||

===

o

Doo

RRrR

k 8.24== Gi RR

k 8.24k33||k100 ==GR

Exercise 4 (cont’d): µnCox = 100 µA/V2, (W/L) = 6/0.1, Vt = 0.5 V, λ = 0.1 V-1.


19.3k 1k 8.24

k 8.24−=×

+=×

+=

i

o

i

o

sigi

i

sig

o

vv

vv

RRR

vv

Exercise 4 (cont’d):


Hz 1684.757.307.61321 =++=++≈ pppp ffff

k 9.1 k 8.24

==

o

i

RR

Amplifier Cut-off frequency 1) 3 caps: 3 poles

Hz 7.6110100)1010(24.8 2

1

0)( 2

1

9331

11

=××+×

=

=+

=

−π

π

p

csigip

f

CRRf

Hz 4.75107.4]579||10[2 2

1)]/()||[(|| 2

1

633

3

=×××

=

+=

−π

π

p

SomLDoSp

f

CrgRRrRf

Hz 7.3010100)105010(1.9 2

1

)( 21

9432

22

=×××+×

=

+=

−π

π

p

cLop

f

CRRf

k 3.36mA/V 1.82

==

o

m

rg



This is a common collector amplifier (emitter follower). o Input at the base, output at the emitter.

It is biased with a current source! o No emitter degeneration: no RE (RE = ∞) and no RB (RB = ∞)



V 72.0100 3

−=++=

E

EBEB

VVVI


≥>= CECBE VIV

k 21.1 r

k 9.34104.3

150r

mA/V 165 1026104.3

3o

3

3

===

=×

=≈

=××

==

mB

T

-C

A

-

-

T

Cm

gIVIVVIg

βπ

A 5.21/mA 3.4

µβ ==≈=

CB

CE

IIII

V 0.7 V 72.44 0 =>=−= DECE VVV


EV


k 21.1 k, 9.34 mA/V, 165 === πom rrg

1104.281

104.28

104.28)||||(

k9.25k100||||k9.34||||)||||(1

)||||(

3

3

3

≈×+

×=

×=

=∞=+

=

i

o

LEom

LEo

LEom

LEom

i

o

vv

RRrgRRr

RRrgRRrg

vv

Ω=+

≈ 111||

||β

π sigBEo

RRrRR

[ ]M 2.5k9.25201k2.1

)||||)(1( || =×+=

++=

i

LEoBi

RRRrrRR βπ


Signal circuit (IVC short, ICS open))

Amplifier Parameters 1) Emitter Follower 2) Biased with an ICS (RE = ∞ ) 3) No voltage divider biasing:

RB is open circuit, RB = ∞

1=≈×+

=i

o

i

o

sigi

i

sig

o

vv

vv

RRR

vv


Signal circuit

k 21.1rk 9.34rmA/V 165

o

===

π

mg

Hz 34.31047.0)11110100( 2

1][ 2

1

632

22

=××+×

=

+=

−π

π

p

coLp

f

CRRf

Ω==

111 M 2.5

o

i

RR


Hz 34.32 == pp ff

Amplifier Cut-off frequency 1) 1 cap: 1 pole 2) no coupling capacitors at the input

0)( 2

1

11 =

+=

csigip CRR

fπ


Exercise 6: Find the bias point and the amplifier parameters of the circuit below. (µpCox (W/L) = 400 µA/V2, Vtp = − 4 V, λ = 0.01 V-1. Ignore channel width modulation in biasing).

This is a PMOS common drain amplifier. o Input at the gate, output at the source.

It has a source-degeneration bias with two voltage sources.


Exercise 6 (Cont’d): µpCox (W/L) = 400 µA/V2, Vtp = − 4 V,λ = 0.01 V-1

Assume Saturation:

092

09104005.010

||101013

2

264

44

=−+

=−+×××

++×=+×=−

OVOV

OVOV

tpOVDSGD

VVVV

VVIVISG-KVL:

5.0 2OVoxpD V

LWCI µ=

V 9.5=+= tOVSG VVV


mA 71.0104005.0 26 =××= −OVD VI

V 9.5 0 =→−= SSSG VVV

V 9.10)5( =−−= SSD VV

V 9.1=OVV

k 141100.7101.0

11

mA/V 0.747 0.303

100.71 2 2

3

3

=××

==

=××

==

−

−

Do

OV

Dm

Ir

VIg

λ

SV



Signal circuit

87.038.61

38.66.38)||||(

k54.8k100||k10||k 141||||

88.0)||||(1

)||||(

=+

=

===

=+

=

i

o

LSom

LSo

LSom

LSom

i

o

vv

RRrgRRr

RRrgRRrg

vv

Amplifier Parameters Common collector Amp.


k 2.1k 34.1||k 101 ||

===

∞==

mSo

Gi

gRR

RR

87.0==×+

=i

o

i

o

sigi

i

sig

o

vv

vv

RRR

vv

k 141 mA/V, 0.747 == om rg

Amplifier Cut-off frequency 1) 1 cap: 1 pole 2) no coupling capacitors at the input


Signal circuit


k 141mA/V 0.747

==

o

m

rg

k 2.1

=∞=

o

i

RR

Hz 39.31047.0)102.110( 2

1

][ 21

635

2

=×××+

=

+=

−π

π

p

coLp

f

CRRf


Exercise 7: Find the bias point and the amplifier parameters of the circuit below. (µnCox (W/L) = 800 µA/V2, Vt = 1 V, λ = 0.01 V-1. Ignore channel width modulation in biasing).

This is a NMOS common gate amplifier. o Input at the source, output at the drain.

It has a source-degeneration bias with a voltage divider.


Bias circuit

054

05108005.010

10106

2

264

44

=−+

=−+×××

×++=×+==−

OVOV

OVOV

DtOVDGSG

VVVV

IVVIVVGS-KVL:

Assume Saturation: 5.0 2OVoxnD V

LWCI µ=

V 0.2=+= tOVGS VVV


mA 40.0108005.0 26 =××= −OVD VI

V 74415101015 44

=−−=×++×=

DS

DDSD

VIVI

V 0.1=OVV

Exercise 7 (Cont’d): µnCox (W/L) = 800 µA/V2, Vt = 1 V, λ = 0.01 V-1.

GV

V 615M8.1M2.1

M2.1=×

+=GV

DS-KVL:

k 250100.401.0

11r

mA/V 0.800 1

100.4 2 2

3o

3

=××

==

=××

==

−

−

D

OV

Dm

I

VIg

λ


69.7)||k 10||k 250(108.0

)||||(

3 =∞×=

=

−

i

o

LSomi

o

vv

RRrgvv


Signal circuit (IVC short)

Amplifier Parameters 1) CG amplifier 2) Biased with two voltage sources (RG = 0)

11.469.7k 1k 15.1

k 15.1=×

+=×

+=

i

o

sigi

i

sig

o

vv

RRR

vv

k 250mA/V 0.800

==

o

m

rg

k 15.1k 1.30||k 10

/)||(1 ||

==

+=

i

m

oLDSi

Rg

rRRRR

k 77.9k 432||k 10

)]||(1([ ||

==

+=

o

sigSmoDo

RRRgrRR


Hz 74021 =+≈ ppp fffk 250mA/V 0.80

==

o

m

rg


Signal circuit (IVC short) Amplifier Cut-off frequency

2 caps: 2 poles

Hz 74010100)1010(1.15 2

1

0)( 2

1

9331

11

=××+×

=

=+

=

−π

π

p

csigip

f

CRRf

010100)10(9.77 2

1

)( 21

932

22

=××∞+×

=

+=

−π

π

p

cLop

f

CRRf

k 77.9 k 15.1

==

o

i

RR


Exercise 8: Design a common emitter amplifier with RE with vo / vi = 5 when driving a 100 kΩ load and a bias point of IC = 4 mA and VCE = 6 V. The circuit should have a cut-off frequency of 50~Hz for Rsig = 100 Ω. A 16 V power supply is available. Use a Si BJT with β = 200, β min = 100, VA = 150 V, ignore Early effect in bias calculations.

Prototype of the circuit is shown.

Problem specification gives

We should find RC , RE , RB1 , RB2 , Cc1 , and Cc2

k 100 , 100 V, 16 =Ω== LsigCC RRV

* See Exercise 4 of BJT lecture slides for bias design

mA, 4 V, 6 k, 100 , 100 V, 16 ===Ω== CCELsigCC IVRRV


Exercise 8 (Cont’d):

k 30.1

k 5.37104

150

mA/V 154 1026104

3

3

3

===

=×

=≈

=××

==

mB

Tπ

-C

Ao

-

-

T

Cm

gIVr

IVr

VIg

β

1. Bias point (IC = 4 mA & VCE = 6 V) gives the SSM parameters as well as a relationship between RC and RE through CE-KVL:

k 5.2104

616)(

3 =×

−=+

+≈−++=

−EC

ECCCECC

EECECCCC

RR

RRIVVIRVIRV

2. Amp gain of vo / vi = 5 also gives another relationship between RC and RE:

CE-KVL:

5)/1](/)||[(1

)||( =+++

=πrRrRRRg

RRgvv

EoLCEm

LCm

i

o

Solution can be simplified by noting RC + RE = 2.5k and thus RC < 2.5k: 1) Since RC << RL = 100 k, then RC || RL ≈ RC 2) Since RC << ro = 37.5 k, we can drop the 3rd term in the denominator of the gain formula:

5.32555

51

+=+=

=+

≈

Em

EC

Em

Cm

i

o

Rg

RR

RgRg

vv

k 09.2 411

k 5.25.325

=Ω=

=++

C

E

EE

RR

RR

A 0.20/ µβ == CB II



3102.73.631316

)/1](/)||[(1)||( −×++

=+++

=πrRrRRRg

RRgvv

EoLCEm

LCm

i

o

In fact, because gm terms are large:

Note that the (open-loop gain) is independent of BJT parameters!

E

C

Em

Cm

Em

Cm

i

o

RR

RgRg

RgRg

vv

=≈+

≈1

For discrete BJT amplifiers (RC << ro ), dropping the third term is a very good approximation because gm terms are actually large:

k 09.2 , 411 =Ω= CE RR

k 30.1 k, 5.37 mA/V, 154 === πom rrg

A. 20 mA, 4 V, 6 k, 100 , 100 V, 16 µ====Ω== BCCELsigCC IIVRRV


Exercise 8 (Cont’d): A. 20 mA, 4 V, 6 k, 100 , 100 V, 16 µ====Ω== BCCELsigCC IIVRRV

1. Bias point (IC = 4 mA & VCE = 6 V) and requirements of good bias give RB1 and RB2 through BE-KVL. However, it is easier to find RB and VBB (Thevenin equivalent) first.

2. Resistors RB1 and RB2 are found from:

BE-KVL:

Dividing the above equations gives RB1 :

k 89.4k 4.27

2

1

==

B

B

RR

k 09.2 , 411 =Ω= CE RR

k 4.154111011.04111011.0)1( 0.1

)1(

min

min

=××=××=+≤

+<<

B

EB

EB

RRR

RRβ

β

V 43.2114 10 4 0.710 4.15 1020 336

=××++×××=

++=

BB

--BB

EEBEBBBB

VV

RIVRIV

152.016

2.43

k 15.4||

21

2

21

2121

==+

=

=+

==

BB

B

CC

BB

BB

BBBBB

RRR

VV

RRRRRRR

The 2nd condition for stable bias is RE IE ≥ 1 V:

V 1 64.1114 10 4 3 >=××= -EE RI



Coupling capacitors Cc1 and Cc2 are found from specification of cut-off frequency (50 Hz). We need to compute Ri and Ro first.

Can choose either capacitor and compute the other one. A good design guideline is to keep capacitors small.

k 15.4 ,k 89.4 ,k 4.27 ,k 09.2 , 411 21 ====Ω= BBBCE RRRRR

k 95.3k 81.6 ||k 15.4)/1](/)||[(1

||

==

++

+=

i

EoLC

EBi

RrRrRR

RrRRπ

πβ

k 09.2M 1.74 ||

||1 ||

=≈=

+++=

CCo

sigBE

EoCo

RRR

RRRrRrRR

π

β

k 30.1 k, 5.37 mA/V, 154 === πom rrg

Amplifier Cut-off frequency (2 caps: 2 poles)

23

22

13

11

10102 21

)( 21

1005.4 21

)( 21

ccLop

ccsigip

CCRRf

CCRRf

××=

+=

××=

+=

ππ

ππ

5010102 2

11005.4 2

1

Hz 50

23

13

21

=××

+××

=+≈

cc

ppp

CC

fff

ππ




We can choose either capacitor and compute the other one. A good design guideline is to keep capacitors small. Since the coefficient of CC1 is 25 times smaller than that CC1, a reasonable choice is to assign 80% of fp to CC1 :

k 15.4 ,k 89.4 ,k 4.27 ,k 09.2 , 411 21 ====Ω= BBBCE RRRRRk 30.1 k, 5.37 mA/V, 154 === πom rrg

nF 156 502.010102 2

1

F 982.0 508.01005.4 2

1

Hz 50

12

3

11

3

21

=→×=××

=→×=××

=+≈

cc

cc

ppp

CC

CC

fff

π

µπ

Design Commercial Value Value (5%)

nF 156F 982.0

411k 09.2k 89.4k 4.27

2

1

2

1

==

Ω====

C

C

E

C

B

B

CCRRRR

µnF 160

F 1 390

k 2k 7.4

k 27

1

2

1

==

Ω====

Cw

C

E

C

B

B

CCRRRR

µ




This is a two-stage amplifier. o Stage 1 is a common emitter amplifier with RE o Stage 2 is a common collector amplifier (emitter follower).

Both stages have source-degeneration bias with a voltage divider. o Each stage is independently biased because of the 470 nF

coupling capacitor between stages.


Stage 1 Bias Thevenin form of the Voltage divider

V 37.215k 2.6k 33

k 2.6

k 22.5k 2.6||k 33

1

1

=×+

=

==

BB

B

V

R

Exercise 9 (cont’d) : β = 200, VA = 150 V


A 9.15/ mA 18.3

5007.0)1/(1022.5 2.37

:KVLBE

111

11

1113

111111

µβ

β

==≈=

+++×=

++=−

CB

CE

EE

EEBEBBBB

IIII

IIRIVRIV


111 ≥>= CECBE VIV

V 0.7 V 05.7 )500102(1018.315

15 :KVLCE

01

331

11111

=>=+×××+=

++=−−

DCE

CE

EECECC

VVV

RIVRI

k 64.1

k 2.4710 18.3

150

mA/V 122 1026103.18

1

1

11

31

11

3

31

1

===

=×

==

=××

==

mB

Tπ

-C

Ao

-

-

T

Cm

gIVr

IVr

VIg

β


Stage 2 Bias Thevenin form of the Voltage divider

V 25.815k 18k 22

k 22

k 90.9k 22||k 18

2

2

=×+

=

==

BB

B

V

R



A 36/ mA 20.7

107.0)1/(109.9 8.25

8.25 :KVLBE

222

22

23

223

22222

µβ

β

==≈=

+++×=

++=−

CB

CE

EE

EEBEBB

IIII

IIRIVRI


222 ≥>= CECBE VIV

V 0.7 V 80.7 101020.715

15 :KVLCE

02

332

222

=>=××+=

+=−−

DCE

CE

EECE

VVV

RIV

k 722.0

k 8.2010 20.7

150

mA/V 277 1026107.20

2

2

22

32

22

3

32

2

===

=×

==

=××

==

mB

Tπ

-C

Ao

-

-

T

Cm

gIVr

IVr

VIg

β



12621

26226294510277)||||(

)||||(1)||||(

2

2

32222

2222

2222

2

2

≈+

=

=××=

+=

−

i

o

LEom

LEom

LEom

i

o

vv

RRrgRRrg

RRrgvv

[ ][ ] k 41.9k 189722 ||k 90.9

)||||( ||

2

2222222

=+=+=

i

LEoBi

RRRrrRR βπ

Stage 2: Emitter Follower For Gain & Ri , start from the load side because we need to know RL

k 41.9 21 == iL RR

k 100 2 == LL RR

k 90.9k 722.0

k 8.20mA/V 277

2

2

2

2

====

B

π

o

m

Rrrg



k 95.497.2k ||k 22.5)/1](/)||[(1

||

1

11111

11111

==

++

+=

i

EoLC

EBi

RrRrRR

RrRRπ

πβ

25.30.62

201046.0500101221

1065.110122

046.0)/1](/)||[(k 1.65k 41.9||k 2||

)/1](/)||[(1)||(

3

33

1

1

11111

11

1111111

111

1

1

−=−=+××+×××

−=

=+==

+++−=

−

−

i

o

EoLC

LC

EoLCEm

LCm

i

o

vv

rRrRRRR

rRrRRRgRRg

vv

π

π

Stage 1: CE amplifier with RE k 41.9 21 == iL RR

k 22.5k 64.1k 2.47mA/V 122

1

1

1

1

====

B

π

o

m

Rrrg



Stage 2: Emitter Follower

For Ro , start from the source side because we need to know Rsig

k 0.2 12 == osig RR

100 1 Ω== sigsig RR

k 2

||1 ||

11

1111

11111

=≈

+++=

Co

sigBE

EoCo

RR

RRRrRrRR

π

β

Stage 1: CE amplifier with RE

Ω==+

= 8.119.11||k 1||

||2

22222 β

π sigBEo

RRrRR

k 22.5k 64.1k 2.47mA/V 122

1

1

1

1

====

B

π

o

m

Rrrg

k 90.9k 722.0

k 8.20mA/V 277

2

2

2

2

====

B

π

o

m

Rrrg



k 0.2 k 95.4

25.3/ k 41.9

100

1

1

11

21

1

==

−===

Ω==

o

i

io

iL

sigsig

RR

vvRRRR

k 22.5k 64.1k 2.47mA/V 122

1

1

1

1

====

B

π

o

m

Rrrg

k 90.9k 722.0

k 8.20mA/V 277

2

2

2

2

====

B

π

o

m

Rrrg

Ω==

===

==

8.11 k 41.9

1/ k 100

k 0.2

2

2

22

2

12

o

i

io

LL

osig

RR

vvRRRR

19.31)25.3(98.0

11.8 k, 4.95

2

2

1

1

21

−=×−×=××+

=

Ω====

i

o

i

o

sigi

i

sig

o

ooii

vv

vv

RRR

vv

RRRR



k 0.2 k 41.9 11.8

k 4.95

1

2

==

Ω==

o

i

o

i

RRRR

Hz 3.527.299.1571.6321 =++=++≈ pppp ffff

Amplifier Cut-off frequency 3 caps: 3 poles

Hz 71.6)( 2

1

11 =

+=

csigip CRR

fπ

Hz 9.15)( 2

1 2

2 =+

=cLo

p CRRf

π

Hz 7.2910470)(2

1

)(21

912

1,,

=××+

=

+=

−

−

oipj

cjjojipj

RRf

CRRf

π

π

Coupling cap at the input:

Coupling cap at the output:

Coupling cap between stages:



This is a two-stage amplifier. Both stages are common emitter amplifier with RE.

Both stages have source-degeneration bias with two power supplies (no voltage divider). o There are NO coupling capacitors and the second stage is

biased from VC1.

A 3.33/mA 65.6

510)1/(106.3 510106.351.3

3 5107.0106.31083.3106.3 15

3 510)(106.3 15

222

22

223

223

22333

22213

µβ

β

==≈=

++×=+×=

−++×+×××=

−+++×=−

CB

CE

EEEB

EB

EBEBC

IIII

IIIIII

IVII



A 2.19/mA 83.3

3 6007.0)1/( 100 03 600 100 0

111

11

111

111

µβ

β

==≈=

−+++=−++=

CB

CE

EE

EBEB

IIII

IIIVI

V 7.0 and 0 V, 7.0: Activein are sBJTboth Assume

111 ≥>= CECBE VIV

BE1-KVL:

BE2-KVL:

CE2-KVL:

0.7 V 63.43 510105.1 15

02

2223

=>=−++×=

DCE

ECEC

VVIVI

CE1-KVL:

0.7 V 79.13 600)(106.3 15

01

11213

=>=−+++×=

DCE

ECEBC

VVIVII



k 36.1

k 2.3910 83.3

150

mA/V 147 1026103.83

1

1

11

31

11

3

31

1

===

=×

==

=××

==

mB

Tπ

-C

Ao

-

-

T

Cm

gIVr

IVr

VIg

β

V 63.4A 2.19

mA 83.3

1

1

1

===

CE

B

C

VII

µV 79.1

A 3.33mA 65.6

2

2

2

===

CE

B

C

VII

µ

k 782.0

k 6.2210 65.6

150

mA/V 256 10261065.6

2

2

22

32

22

3

32

2

===

=×

==

=××

==

mB

Tπ

-C

Ao

-

-

T

Cm

gIVr

IVr

VIg

β



For Gain & Ri , start from the load side because we need to know RL

k 8.92 21 == iL RR

k 100 2 == LL RR

∞====

2

2

2

2

k 782.0k 6.22mA/V 256

B

π

o

m

Rrrg

k 8.9292.8k ||)/1](/)||[(1

||

2

22222

22222

=∞=

++

+=

i

EoLC

EBi

RrRrRR

RrRRπ

πβ

88.2132379

108.05101056211048.110562

108.0)/1](/)||[(k 1.48k 100||k 5.1||

)/1](/)||[(1)||(

3

33

1

1

22222

22

2222222

222

2

2

−=−=+××+×××

−=

=+==

+++−=

−

−

i

o

EoLC

LC

EoLCEm

LCm

i

o

vv

rRrRRRR

rRrRRRgRRg

vv

π

π




k 108k 108 ||)/1](/)||[(1

||

1

11111

11111

=∞=

++

+=

i

EoLC

EBi

RrRrRR

RrRRπ

πβ

71.53.89

510127.0600101471

1047.310147

127.0)/1](/)||[(k47.3k 8.92||k 6.3||

)/1](/)||[(1)||(

3

33

1

1

11111

11

1111111

111

1

1

−=−=+××+×××

−=

=+==

+++−=

−

−

i

o

EoLC

LC

EoLCEm

LCm

i

o

vv

rRrRRRR

rRrRRRgRRg

vv

π

π

Stage 1: CE amplifier with RE k 8.92 21 == iL RR

∞====

1

1

1

1

k 36.1k 2.39mA/V 147

B

π

o

m

Rrrg

∞====

2

2

2

2

k 782.0k 6.22mA/V 256

B

π

o

m

Rrrg

∞====

1

1

1

1

k 36.1k 2.39mA/V 147

B

π

o

m

Rrrg



For Ro , start from the source side because we need to know Rsig

k 6.3 12 == osig RR

100 1 Ω== sigsig RR

k 6.3

||1 ||

11

1111

11111

=≈

+++=

Co

sigBE

EoCo

RR

RRRrRrRR

π

β


k 5.1

||1 ||

21

2222

22222

=≈

+++=

Co

sigBE

EoCo

RR

RRRrRrRR

π

β


∞====

2

2

2

2

k 782.0k 6.22mA/V 256

B

π

o

m

Rrrg

∞====

1

1

1

1

k 36.1k 2.39mA/V 147

B

π

o

m

Rrrg



k 6.3 k 108

71.5/ k 8.92

100

1

1

11

21

1

==

−===

Ω==

o

i

io

iL

sigsig

RR

vvRRRR

k 5.1 k 8.92

88.2/ k 100

k 6.3

2

2

22

2

12

==

−===

==

o

i

io

LL

osig

RR

vvRRRR

4.16)88.2()71.5(1

k 5.1 k, 108

2

2

1

1

21

=−×−×=××+

=

====

i

o

i

o

sigi

i

sig

o

ooii

vv

vv

RRR

vv

RRRR

Amplifier Cut-off frequency: only Coupling cap at the output:

Hz 7.15)( 2

1 2

=+

=cLo

p CRRf

π

Problem for Problems for Discrete Transistor...

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Transcript of Problem for Problems for Discrete Transistor...