Negative Biased TemperatureNegative Biased Temperature Instability (NBTI) and Hot

Carrier Effect (HCE)( )

Hamed AbrishamiHamed Abrishami

NBTI

Its an aging effect

Threshold voltage of PMOS transistors increase by time. (|Vth| increases) Causes drive current (ID), transconductance (gm) and

mobility () decrease

PMOS transistors speed decreases over time

Degrades the switching speeds of logic cells and the circuit performance

NBTI

( )D ox GS th

th D

WI C V VL

V I

DDd

D

D d

CVtI

I t

= D d

B.C. Paul, et al., Electron Devices Letter, 2005

NBTI

Created under negative bias condition (VGS=VDD) Highly dependent on temperature Created by trap generation at the Si/SiO2 interface Why Traps

Some of the Si bonds remain dangling at the semiconductor-oxide interface

They act as traps, resulting in poor device characteristicsThey act as traps, resulting in poor device characteristics Transistors are annealed in hydrogen ambient so that the

gas diffuses into the oxide and passivates the interfaceI t ti f h l ith h d i t d Si t Interaction of holes with hydrogen-passivated Si atoms breaks Si-H bonds and creates traps

00HSihHSi ++ +

NBTI

Si, Si/SiO2 interface, SiO2 bulk and oxide defect structure

Dit: interface trap

From Dieter K. Schroders slides

Interface traps

From Dieter K. Schroders slides

Reaction and Diffusion

Reaction: Interaction of holes with passivated Si atoms can break the Si-H bond leaving behind the i t f tinterface trap

Diffusion: Associated H atom diffuses away from the Si/oxide interfacethe Si/oxide interface

Static vs. Dynamic NBTI

There are two phases of NBTI depending on the bias conditions: Phase 1 (static NBTI): Voltage gate source is negative

(VGS= -VDD) Interface traps accumulating over the stress timeInterface traps accumulating over the stress time H diffusing toward the gate Threshold voltage increases over the time

S. Bhardwaj, et al., CICC 2006

Static vs. Dynamic NBTI

Phase 2 (recovery time): VGS is zero Holes are not present in the channel No new interface traps are generated No new interface traps are generated H diffuses back and anneals broken Si-H bonds Number of interface traps reduced NBTI degradation is recovered

Dynamic NBTI: PMOS Dynamic NBTI: PMOS transistor undergoes alternating stress (VGS=-VDD)alternating stress (VGS VDD) and recovery (VGS=0) periods

S. Bhardwaj, et al., CICC 2006

Dynamic NBTI

Duty cycle of input signals has an important rule in NBTI ff tNBTI effect Here we define duty cycle

as the percentage of theas the percentage of the time that signal is zero

More NBTI impact by scaling down CMOSscaling down CMOS technology

R. Vattikonda, et al., DAC 2006

Frequency Independence

f f

Vdd

freq = f1

T n cycles V

freq = f2

T1

n1 cycles Vdd

freq f2

T2n2 cycles

Number of interface traps for both cases are the same

T2

Trap generation is independent of frequency

S. Kumar, et al., ICCAD 2006

Frequency Independence

15DCDC

freq = f9

12

15DC

freq = ffreq = 0 1fAC freq = f

q

6

9 freq ffreq = 0.1ffreq = 0.01f

Vth(mV)

0

3

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 100000 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

time (s)

Vth degradation same for all three casesS. Kumar, et al., ICCAD 2006

NBTI solutions (gate sizing)

1. Increase width of PMOS transistors in a gate Can cause degradation on falling delay by increasing

diff ion p it n ediffusion capacitance

2. Increase the size of the whole gate Area increase Area increase Power consumption increase

3 Find the critical path of the circuit and apply 1 or 23. Find the critical path of the circuit and apply 1 or 2 Less power consumption increase Less area increaseLess area increase

Gate Sizing

Change in the gate delay can be approximated by this equation thV

V V

Our objective is to minimize the total area which can be

represented by ixi, i = 1, . . . , n

0 0gs thV V

i i

xi is the gate size i is an arbitrary constant multiplier for gate i depending

th bj ti f th ti i tion the objective of the optimization

B. C. Paul, et al., TCAD 2007

Gate Sizing

Problem formulation for optimization problem

o Li and Ui represent the lower bound and upper bound of the size of gate i, respectively.

o p is the set of possible paths in a circuitD t th d l f t i i tho Di represents the delay of gate i in a path p.

B. C. Paul, et al., TCAD 2007

Gate Sizing

Threshold voltages of the transistors in all individual gates will be different due to the NBTI d di th i it hi ti itidepending on their switching activities.

The proposed algorithm first calculates the threshold voltage degradation of all transistors in athreshold voltage degradation of all transistors in a circuit depending on their switching activities and then sizes the circuit to ensure the performance forthen sizes the circuit to ensure the performance for a desired period of time (e.g., ten years).

B. C. Paul, et al., TCAD 2007

Gate Sizing

B. C. Paul, et al., TCAD 2007

NBTI solutions (input vector)

Applying an input vector which minimizes the NBTI Applying an input vector which minimizes the NBTI effect in standby mode This technique is the same as minimum input leakage This technique is the same as minimum input leakage

vector to overcome subthreshold leakage power One can find the best vector which minimizes the

leakage power and maintains less than certain amount of NBTI degradation during standby mode

Define a Mathematical program the same as sizing Define a Mathematical program the same as sizing problem Objective is to minimize the subthreshold leakage Constraint is not to exceed a specific amount of NBTI

degradation It can be another way around: minimizing NBTI It can be another way around: minimizing NBTI

degradation while maintaining less than certain amount on subthreshold leakage power

NBTI Effect on SRAM

Static Noise margin (SNM) It is the most important

p mete in the SRAMparameter in the SRAM Decreases due to NBTI Maximum square in the Maximum square in the

butterfly curve

NBTI Effect on SRAM

Since one PMOS is under stress and the other one i i th his in the recovery phase, can flip the data which is saved in the SRAM aftersaved in the SRAM after a while

Change in SNM isChange in SNM is noticeable after 105second (1.16 day) Flip the value every day

S.V. Kumar, et al., ISQED 2006

Adaptive Body Biasing

Body biasing can be used to control the change in the threshold voltage

( )0 | 2 | | 2 |th T F SB FV V V = + + Use a higher voltage than VDD for the body of the

PMOS transistor According to the above equation Vth decreases and

compensates for increase due to NBTI effectTh li d l h b d d i l The applied voltage to the body can adaptively change by monitoring the NBTI effect

Adaptive Body Biasing

In these figure the body biasing effect is not considered in |Vthp|. The Adaptive Body Biasing (ABB) effect is considered in drive current and frequencyin drive current and frequency.

Drive current degradation Ring Oscillator frequency degradationDrive current degradationwith and without ABB

Ring Oscillator frequency degradation

Z. Qi, et al, GLSVLSI 2008

Soft-Edge Flip-Flop

Soft-Edge Flip-Flop (SEFF) is used to create a transparency window for setup time (decreases

t ti )setup time)

NBTI causes degradation in h bi i l i ithe combinational circuit

performance Data is not captured in flip flop Data is not captured in flip-flop Timing failure

Transparency window can be Transparency window can be used to compensate for performance degradationp g

K. Duraisami, et al.,GLSVLSI 2009Timing of a Regular FF (Top)and of a SEFF (Bottom)

NBTI Effect on Sequential Circuit

Setup time and hold time change Over-design the sequential circuit to overcome the problem

C ll l l i i Cell level sizing Considers flip-flop as a logic cell and up-sizes all the transistors Drawbacks

area increase power consumption increase

Uniform PMOS transistor sizingg Drawbacks

falling transition time increase area increase power consumption increase

Selective Transistor-Level Sizing (STLS)

Selective Transistor-Level Sizing (STLS)

Over-design the circuit that after desired period of time, e.g., three years, meets the timing requirements

Analyze the internal structure of the flip-flip Analyze the internal structure of the flip-flip Modify sizes of the NMOS and PMOS transistors to

compensate for the effect Keep minimization of area and power consumption in mind

area power Sizing Technique area increase consumption increase

cell level sizing +26% +19.8%

uniform PMOS transistor-level sizing +14% +11.52%

selective transistor-l l i i +8.3% +7.64%level sizing +8.3% +7.64%

H. Abrishami, et al, GLSVLSI 2008Master-slave FF over-design

Hot Carrier Effect

L di i d hi h b t t d i i ll Lower dimensions and higher substrate doping in small geometry technologies would result in large vertical and horizontal electric fields in the channel region which in turn give g grise to electrons and holes with high kinetic energies

These electrons and holes may be injected into the gate oxide and can cause permanent changes in the oxide interfaceand can cause permanent changes in the oxide interface charge distribution. This is called Hot Carrier Effect (HCE), or sometimes hot electron effect because this injection happens more often for electrons due to smaller barrier height of electrons as compared to holes

Hot Carrier Effect

A sizeable increase in the threshold voltage of the affected transistors and a corresponding decrease in their drain current driving capability are undesirable results of such hotcurrent driving capability are undesirable results of such hot carrier injections in the gate oxide

Causing performance degradation The hot carrier effect is exacerbated as the technology

moves toward smaller device dimensions and higher clock frequenciesfrequencies

HCE vs NBTI

Hot Electron Effect or Channel Hot Carrier (CHC) causes the generation of the interface traps at the Si SiO2 i t f th d i d b t NBTISi-SiO2 interface near the drain end but NBTI causes the interface traps at the whole Si-SiO2interfaceinterface

Vth degradation cannot be recovered The effect is mostly considered at NMOS transistors The effect is mostly considered at NMOS transistors

HCE

HCE of NMOS under various L and bias conditions

Vgs and L dependence Vds and L dependence

W. Wang, et al.