NANOCHIP - Applied Materials · 2014-07-28 · 5 Volume 9, Issue 2, 2011 Nanochip Technology...

volume 9, issue 2, 2011

INTEGRATING ATOMIC LAYER DEPOSITION HIGH-κ DIELECTRICS

IN THIS ISSUE• Advanced Transistors—Scaling with New Materials and New Architecture

• Spike Anneals for 32nm and Beyond

• Nano-Porous Dielectrics for 28nm Applications

NANOCHIPTechnology Journal

3 Advanced Transistors —

Scaling with New Materials and New Architecture

10 Optimizing Spike Anneals

for 32nm and Beyond

15 Integrating Atomic Layer Deposition High-κ Dielectrics

at the ≤22/20nm Logic Technology Node

20 Extending Oxynitride Gate Technology

for Advanced DRAM

25 Improving Tungsten Chemical Mechanical Planarization

for Next-Generation Applications

29 A High Productivity ALD-Like Conformal Oxide Liner

for ≤20nm Technology Nodes

35 Optimizing Nano-Porous Dielectrics

for ≤28nm Applications

43 Enhancing Dielectric Etch Uniformity

for 28nm Copper Dual Damascene

Table of Contents

This is an exciting time in our industry, spurring the technical advances highlighted

in this issue. With planar transistor scaling facing a growing number of limitations,

we seek a new degree of freedom by going three-dimensional, while continuing to

pursue solutions that extend planar scaling to its ultimate extent. The 2x nanometer

era requires bold changes in device architectures, introducing a significant increase in

complexity throughout the manufacturing flow.

At the 2x nanometer node, logic devices require high-k/metal gate architecture,

introducing additional process steps and much more stringent process requirements.

Equivalent oxide thickness scaling and gate leakage challenges drive the need for atomic layer deposition

(ALD) of high-k dielectric gate stacks. Turning attention to source/drain regions, we discuss solutions to

thermal pattern loading effects in rapid thermal processing (RTP), which is particularly critical in the formation

of shallower junctions without compromise to activation.

As DRAM devices scale below the 3x nanometer node, a new deep plasma process is required to enable

higher-dose nitridation without increasing leakage current or the magnitude of transistor threshold voltage.

Tungsten CMP applications in memory now require real-time process control for greater precision and flatness

uniformity, and benefit from dual-wafer polishing with its significantly lower cost of consumables.

Scaling is also driving breakthroughs in the interconnect. We discuss a third-generation low-k dielectric with

uniform porosity, which boosts mechanical strength over previous generations and lowers the dielectric

constant to 2.2. We also discuss a new tuning parameter for achieving etch depth uniformity and CD control

needed for uniform resistance of copper interconnect lines.

I expect these articles will interest you, and I am encouraged by our ongoing engagements as we all innovate to

enhance the technical expertise, productivity, and efficiency of our industry.

Front Cover: To extend Moore’s law to the 2x nm node and beyond, logic devices require high-k/metal gates; the high-k dielectric is actually a stack of several layers, with atomic layer deposition (ALD) used to deposit the ultra-thin high-k layer. Integrating the ALD process on a single platform with low-temperature radical oxidation, nitridation, and post-nitridation anneal chambers enables the high-k dielectric to be optimized, minimizing queue-time between each step and keeping the wafer in a controlled vacuum environment for the entire sequence. This avoids contamination and prevents degradation of the interfaces in this critical core of the transistor.

Corporate Vice

President and CTO,

Silicon Systems Group

A MESSAGE FROM KLAUS SCHUEGRAF

3 Advanced Transistors —

Scaling with New Materials and New Architecture

10 Optimizing Spike Anneals

for 32nm and Beyond

15 Integrating Atomic Layer Deposition High-κ Dielectrics

at the ≤22/20nm Logic Technology Node

20 Extending Oxynitride Gate Technology

for Advanced DRAM

25 Improving Tungsten Chemical Mechanical Planarization

for Next-Generation Applications

29 A High Productivity ALD-Like Conformal Oxide Liner

for ≤20nm Technology Nodes

35 Optimizing Nano-Porous Dielectrics

for ≤28nm Applications

43 Enhancing Dielectric Etch Uniformity

for 28nm Copper Dual Damascene

Table of Contents

3 Volume 9, Issue 2, 2011 Nanochip Technology Journal Applied Materials, Inc.

ADVANCED TRANSISTORSScaling with New Materials and New Architecture

KEYWORDS

Transistor

3D

FinFET

QWFET

HKMG

Isolation

Channel

Gate Stack

Source/Drain

Epitaxial Growth

RTP Anneal

Shallow Junction

Strain Engineering

Classic transistor scaling has given way to modern scaling

and related performance enhancement based on new

materials in strain engineering and high-κ metal gate

schemes. Next-generation devices will incorporate an

even wider range of new materials and three-dimensional

transistor architectures to sustain Moore’s Law; these

trends are posing challenges that are driving development

of new process capabilities in transistor fabrication.

Over the past 40 years, transistors have undergone

steady miniaturization in accordance with Moore’s

Law. Until the 130nm node, referred to as the classic

or Denard era, scaling followed a set of simple rules

to shrink gate length, gate dielectric thickness, and

junction depth by a factor 1/k (k~1.4).[1] The 90nm node

transistor to the present, referred to as the modern

MOSFET (metal oxide semiconductor field effect

transistor) era, has seen the non-classical adoption of

new materials to sustain scaling. For the 22nm node

and beyond, we expect an even greater adoption of new

materials and architectures.

The classic era efficiently provided for the needs of that

time in higher circuit speeds and higher densities. But

the modern era imposes multiple demands for lower

active and passive power, and higher speed and packing

density. Many innovations in new materials have been

responses to these multiple demands. Strain engineering

through epitaxial source-drain structures increased

carrier mobility in the channel and enabled higher

speeds.[2] At the 45nm node, high-κ metal gates

substantially reduced active power via leakage from gate

to channel.[3] The 3D FinFET (fin field effect transistor)

transistor at the 22nm node is a new architecture that

substantially reduces passive power or active power

while enabling advanced transistor scaling.[4] New

substrates, such as FDSOI (fully depleted silicon-on-

insulator), are designed for lower operating power and

higher performance benefits.[5] New channel materials

incorporated in a QWFET architecture (quantum well

field effect transistor) can offer a step function im-

provement in transistor performance with substantially

higher carrier mobilities and lower operating voltages.[6]

Structural building blocks of a MOSFET transistor are

transforming radically (Figure 1). This review examines

the evolution of each to meet today’s and tomorrow’s

needs.

Figure 1

Modern MOSFET (32nm)

Classic MOSFET (130nm)

Poly

Source

Spac

er

Drain

SiON

Silicide

Spac

er

Hig

h-κ

EpiSource

EpiDrain

SiON Liner

Metal

WF Metal

(b)

(a)

ISOLATIONWhile the active silicon pitch and shallow trench isola-

tion (STI) widths decrease proportionally with scaling,

STI depth is decreasing only incrementally. According

to the 2009 ITRS, STI top width will decrease from

59nm in 2009 to 28nm in 2015, but the trench depth

will decrease only from 353nm to 309nm. As a result,

the STI aspect ratio will grow from 6:1 to 11:1, increasing

the challenge for void-free STI fill. A series of chemical

vapor deposition (CVD) oxide processes has been

Figure 1. (a) Classic

(130nm) MOSFET and

(b) modern (32nm) MOSFET

showing application of

newer materials for strain

engineering and high-κ metal

gate.

4Volume 9, Issue 2, 2011Nanochip Technology JournalApplied Materials, Inc.

Evolving Transistor Technologies

developed to meet fill challenges: from high-density

plasma (HDP) to sub-atmospheric CVD (SACVD),

to high aspect ratio process (HARP) CVD, to today’s

eHARP, and flowable CVD solutions. HDP has good film

quality and low wet etch rate ratio (WERR) as deposited,

while other films require optimized post-deposition

anneal to improve film quality and reduce WERR. HDP

is capable of void-free STI fill up to an aspect ratio of

approximately 5:1. HARP and eHARP are currently

standard films for STI fill, while flowable CVD with its

outstanding bottom-up fill capability will be used for

the n+1 node and beyond.

For 3D FinFET transistors, a critical process step is

recessing the STI oxide to form the “fin” (Figure 2).

Standard wet etching, dry plasma etching, or plasma-

free dry oxide removal processes can be employed.

The latter iterates between growth and sublimation of

ammonium fluorosilicate with each cycle, consuming

a well-controlled amount of oxide (e.g., 20nm). Recent

research on forming a FinFET structure using this recess

etch process after STI showed good electrical results for

Ion

vs. Ioff

performance relative to planar transistors.[7]

The other advantage of this process is that the oxide

removal rate is less dependent on oxide density, reducing

the incidence of foot and void formations that occur in

conventional wet etch or dry etch processes.[7]

Figure 2

(b)

(a)

SiN

Si

Si

Oxide

CHANNELMuch recent research has been directed at new channel materials: SiGe,[8] Ge,[9] III-V compound semiconductors,[10] carbon nanotubes,[11] and grapheme.[12] Among them, III-V and Ge materials are front runners given their greater maturity through adop-tion in optoelectronic and communication devices and in logic devices today. Other candidates face a “bottom up synthesis” challenge requiring a different alignment approach than established etch and patterning.[13]

III-V materials, such as InSb or InAs, can theoretically provide 50-100 times the electron mobility of silicon and Ge provides higher hole mobility than silicon, making them attractive candidates for NMOS and PMOS, respectively.[14] A possible architectural construct for implementing these new channel materials is a QWFET transistor derived from a HEMT (high electron mobility transistor) device.[14] Here the active channel layer is sandwiched between two other material layers and carriers are confined to the active layer (hence the name quantum well). Coulombic scattering, which adversely affects carrier mobility, is virtually eliminated, giving rise to the possibility of exceptionally high carrier mobilities.

Multiple processing challenges exist for heterogeneous integration of III-V materials onto a silicon substrate. The epitaxial growth of a III-V film from a starting silicon lattice can be very challenging owing to a large lattice constant mismatch between the two materials that can introduce crystallographic defects, such as dislocations and anti-phase domains.[15] A composite buffer layer approach is needed, wherein intermediate layers bridge the wide gap in lattice constants via smaller intermediate steps, thereby relaxing strain over the stack so that a final defect-free channel layer can be grown (Figure 3).[16] Coefficient of thermal expansion mismatch issues in subsequent heating and cooling steps also must be addressed. III-V materials form a direct Schottky contact with metal gate in a QWFET and a suitable gate dielectric is needed to reduce the high parasitic gate leakage.[17]

Integration of Ge onto silicon also presents processing challenges. Epitaxial Ge growth on silicon is relatively straight forward compared to III-V growth on silicon, but surface preparation and interface control for defect density prior to high-κ dielectric deposition is critical. Nitridation of the Ge surface[18,19] or annealing in a SiH

4+N

2 chemistry[20] shows improvement in surface

Figure 2. (a) STI structure

post-etch and (b) similar

structure post-STI fill, CMP,

nitride strip, and oxide

recess for fin formation.[7]

5 Volume 9, Issue 2, 2011 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.


A metal gate electrode must be paired with a high-κ

dielectric to address two known issues of Vt (threshold

voltage) pinning and depletion layer formation (4-6Å

increase in electrical thickness) seen with conventional

poly gate. Dual work functions for independent and low

Vt control for NMOS and PMOS transistors are needed

for best performance. Clustered tool metal gate

processing offers optimal conditions for depositing

multiple metal layers (Figure 6) to ensure compositional

and contamination control. Other gate requirements

include low-damage downstream steps, non-reactivity

to high-κ, good adhesion to interface films, and low

resistivity at shrinking device nodes. The smaller critical

dimension (CD) causes more wall scattering and reduces

the volume of conducting metal relative to barrier

metal inside the gate trench, resulting in worsening sheet

resistivity.[25] Metal fill also becomes more challenging

for small gaps. In response, new materials and atomic

layer depositions (ALD) or CVD are likely to be required.

The industry’s convergence on the gate-last HKMG[26]

scheme makes chemical mechanical planarization

(CMP) processes more critical in gate feature size and

height control. Poly open and metal gate CMP processes

face stringent requirements for precise thickness and

uniformity control within die, within wafer, and from

wafer to wafer to minimize variability and ensure

highest transistor performance.[27] Furthermore, HKMG

stacks will be integrated onto 3D FinFET architecture

with high-κ and metal gate surrounding the 3D

channel. Deposition processes that offer outstanding

conformality along all surfaces of the fin (e.g., ALD of

high-κ) are likely to be required.

passivation, but much more development is needed to

obtain the best quality surface. A stable gate dielectric

with low defect densities is difficult to obtain as opposed

to the prior high quality Si/SiO2 interface. In general,

the Ge/GeO2 system is less stable chemically and

electrically than a SiO2/Si system. Ge oxynitride has

better stability than native germanium oxides[21] and

a high quality thin oxynitride has been formed on

germanium by NH3 nitridation of a thermally grown

germanium oxide.[22]

In the future, III-V and Ge channel-based transistors will

be incorporated in 3D transistor architectures, whose

feasibility with silicon has been demonstrated in recent

path-finding studies.[23]

GATE STACK The introduction of the high-κ (dielectric constant) metal

gate (HKMG) has been a key inflection in continued

scaling.[24] As seen in Figure 4, HKMG restores the

stalled electrical thickness scaling while simultaneously

reducing the otherwise rising leakage.[24]

Figure 4

350 250 180 130 90 65 45 32 22 15 11

Technology Node (nm)

TlN

V (

nm

)

Gat

e Le

akag

e (R

el.)

10

1

1000

100

10

1

0.1

0.01

HKMG is composed of two material systems: a high-κ

dielectric stack and a metal gate electrode. The high-κ

dielectric is physically thick (impeding leakage) but

behaves capacitively thin (promoting greater

electrostatics). For example, a 3nm thick HfO2 layer

has the capacitance of a <1nm thin SiO2 film.High-κ

films require an underlying SiON interface layer (IL)

to achieve low interface trap density. This reduces the

average κ value that can be achieved. There must be

good dielectric film stack reliability measured in metrics

such as biased temperature instability, time-dependent

dielectric breakdown, and voltage extended life test.

Also, HfO2 dielectrics can react with metal gate materi-

als and silicon at high temperatures. Mitigation of this

reactivity can require cap metal protection and minimal

exposure to high-temperature steps.

Interface engineering is paramount for good carrier

mobility and precise control is required in formation

of the high-κ/SiON (IL)/Si interface (Figure 5). The

interface needs to be of uniform thickness and free

of unwanted native surface oxidation or carbon

contamination. Interface formation involves precisely

controlled deposition, anneal, and nitridation steps.

A clustered platform integrating all these steps and

processing a wafer through the entire sequence under

continuous vacuum can offer the needed interface

control. Future options to scale electrical thickness

include increasing the κ value of the high-κ dielectric,

reducing the IL thickness, or increasing the IL κ value.

Reliability performance will play a strong role in

determining the eventual course.

Figure 3

In0.53

Ga0.47

As Cap Layer

In0.52

Al0.48

As Top Barrier

In0.7

Ga0.3

As QW

In0.7

Ga0.3

As QW

0.8µm InxAl

1-xAs

0.5µm GaAs

1.3µm

In0.52

Al0.48

As Top Barrier

In0.52

Al0.48

As Bottom Barrier

InP Etch Stop

0.2μm 10nmSi

Figure 5

High-κ

SiON

Silicon Substrate

Metal Gate

Cap Metal

SiON Interface Layer ~0.5nm

Source: Applied Materials Maydan Technology Center

High-κ ~2.5nm

Cap Metal

Metal Electrode

Silicon Substrate

2nm

Figure 3. A composite buffer

layer approach is necessary

for growing defect-free

InGaAs quantum well

structures on silicon.[16]

Figure 4. HKMG has been

a major enabler of sustained

electrical thickness scaling.[24]



A metal gate electrode must be paired with a high-κ

dielectric to address two known issues of Vt (threshold

voltage) pinning and depletion layer formation (4-6Å

increase in electrical thickness) seen with conventional

poly gate. Dual work functions for independent and low

Vt control for NMOS and PMOS transistors are needed

for best performance. Clustered tool metal gate

processing offers optimal conditions for depositing

multiple metal layers (Figure 6) to ensure compositional

and contamination control. Other gate requirements

include low-damage downstream steps, non-reactivity

to high-κ, good adhesion to interface films, and low

resistivity at shrinking device nodes. The smaller critical

dimension (CD) causes more wall scattering and reduces

the volume of conducting metal relative to barrier

metal inside the gate trench, resulting in worsening sheet

resistivity.[25] Metal fill also becomes more challenging

for small gaps. In response, new materials and atomic

layer depositions (ALD) or CVD are likely to be required.

The industry’s convergence on the gate-last HKMG[26]

scheme makes chemical mechanical planarization

(CMP) processes more critical in gate feature size and

height control. Poly open and metal gate CMP processes

face stringent requirements for precise thickness and

uniformity control within die, within wafer, and from

wafer to wafer to minimize variability and ensure

highest transistor performance.[27] Furthermore, HKMG

stacks will be integrated onto 3D FinFET architecture

with high-κ and metal gate surrounding the 3D

channel. Deposition processes that offer outstanding

conformality along all surfaces of the fin (e.g., ALD of

high-κ) are likely to be required.

Figure 6

Metal Gate

High-κ

SiON

Silicon Substrate

Cap Metal

TiAl

TiTiNTaN

TiN

SOURCE/DRAINIn planar transistors, source/drain (S/D) parasitic resistance control and ultra-shallow junction formation are key concerns. In-situ dopant incorporation during epitaxial growth and subsequent dopant activation to the fullest extent (even beyond solid solubility limits) are critical in lowering the resistance of the S/D region (R

SD)

and its extension region (RSDE

). Also, rapid thermal anneal processes (RTP) must maintain an ultra-shallow junction depth within a lower thermal budget, which necessitates lower anneal temperatures and shorter residence times. With the advent of 3D FinFET transis-tors, S/D regions may be grown by selective epitaxy on top of the silicon fins; one such dual-raised S/D approach has been recently demonstrated.[28] Uniform doping across the three-dimensional surfaces of the fins becomes critical for device performance and conformal doping technologies will become enabling solutions. In FDSOI technology, the already thin extension regions can undergo amorphization damage during ion implantation, which degrades R

SDE, and a dopant loss path to buried

oxide can worsen RSD

.[29] Recent studies employing

Figure 5

High-κ

SiON

Silicon Substrate

Metal Gate

Cap Metal

SiON Interface Layer ~0.5nm

Source: Applied Materials Maydan Technology Center

High-κ ~2.5nm

Cap Metal

Metal Electrode

Silicon Substrate

2nm

Figure 5. Precisely

engineered high-κ/IL/Si

interface.

Figure 6. A metal gate

electrode is composed of

multiple metallic layers.



a diffusion-based approach to drive dopants from a faceted p+ epi S/D into the extension regions show a much lower parasitic resistance for PMOSFETs.[30,31]

CONTACT AND SHEETSheet resistivity and interface resistance are the main concerns in contact scaling. Sheet resistivity increases geometrically at smaller CDs owing to a shrinking con-tact area and improved channel conductance.[32] Using trench contacts (large rectilinear openings) instead of plugs (small circular openings) relieves this problem by accommodating more metal and shunting the entire S/D area. Interface resistance from silicide intrinsic resistance and silicide-silicon Schottky barrier height can be reduced through new materials engineering. Nickel silicide and NiPtSi, today’s material choices, have the lowest bulk resistivity among common silicides. Continued junction scaling, however, calls for a thinner silicide layer. It is critical to ensure uniform conversion to the low resistance monosilicide phase, and avoid the resistive NiSi

2 phase, which causes spikes or pipes

that lead to junction leakage.[33,34] This can be achieved by using an optimized PVD process to ensure uniform metal deposition with density and topology, a dry chemistry pre-clean process and advanced anneal steps to obtain the best possible uniformity at the lowest thermal budget. Two key advances are backside rapid thermal annealing to improve uniformity in the conver-sion step and laser millisecond anneal, which reduces nickel diffusion. Laser anneal has also proved useful for reducing leakage variability.[35] Barrier height lowering is attracting active research and dual silicides to optimize for NMOS and PMOS separately are investigated.[36]

In the future, one can expect ALD or CVD of thinner barrier materials, advanced laser anneal technologies, and newer metal choices (e.g., low resistivity tungsten or copper contacts).[37] Integration with 3D FinFET transistors will likely build upon the rectilinear trench contacts; here, a design in which multiple fins share a common contact is promising.[38]

STRAIN ENGINEERINGStrain engineering played a key role in perpetuating Moore’s Law after the 90nm node by reviving the degraded carrier mobility after years of classic scaling. The introduction of strain into the channel reduces carrier scattering, increases mobility, and produces higher drive current performance. Two commonly employed strain approaches are dual stress liners and raised or recessed S/D structures.

The nature of desired strain is dependent on transistor

type. Tensile strain increases electron mobility suiting

NMOS while compressive strain increases hole mobility

suiting PMOS transistors. Dual stress liners employ

stress-tunable silicon nitride films[39] with a tensile

nitride film deposited over the NMOS gate stack and a

compressive nitride film deposited over the PMOS gate

stack, respectively. In the recessed S/D approach,

active silicon regions are etched and replaced with

epitaxially-grown structures that impart strain to the

channel. Si-Ge structures have been implemented for

PMOS transistor S/D regions to transfer compressive

strain to the channel and increase hole mobility.

Similarly Si-C structures are considered potential

candidates for NMOS S/D regions; research efforts

have shown more than 50% higher electron mobility.[40]

Scaling for greater strain to achieve higher drive cur-

rents in future nodes is possible and can be achieved

through higher dopant concentrations, geometrical

depth, and channel proximity of S/D regions. Integrating

strain engineering into FinFET transistors will be an

inevitable extension of this technology. However,

achieving a high-stress state in a free-standing fin

surface will be a challenge calling for novel solutions.[41]

CONCLUSIONTransistor scaling into the next decade will be enabled

by new materials and architectures. The initial wave of

new materials adoption in strain engineering and HKMG

will proliferate throughout the transistor structure. New

architectural constructs, such as 3D FinFET, QWFET,

and FDSOI will increase process complexity and require

innovative and holistic solutions.

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[31] K. Cheng, et al., “Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications,” Electron Devices Meeting, 2009 IEEE International, pp. 1-4, Issue 7-9, Dec. 2009.

[32] M. Tada, et al., “Performance Modeling of Low-κ/Cu Interconnects for 32nm-Node and Beyond,” Electron Devices, IEEE Transactions, Vol. 56, No. 9, pp. 1852-1861, 2009.

[33] Lauwers, et al., “Ni-Based Silicides for 45nm CMOS and Beyond,” J. Materials Science and Engineering, B 114–115, pp. 29–41, 2004.

[34] C. Detavernier, et al., “Kinetic of Agglomeration of NiSi and NiSi

2 Phase Formation,” Mat. Res. Soc.

Symp. Proc., Vol. 745, 2003.

[35] Y. Chen, et al., “Advances on 32nm NiPt Salicide Process,” Advanced Thermal Processing of Semiconductors, 17th International Conference, pp. 1-4, Sept. 29-Oct. 2, 2009.

[36] B. Nishi, et al., “Interfacial Segregation of Metal at NiSi/Si Junctional for Novel Dual Silicide Technology,” IEEE International Electron Devices Meeting Technical Digest, pp. 135-138, 2007.

[37] A. Topol, et al., “Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS,” VLSI Technology, 2006.

[38] K. Kuhn, “Moore’s Law Past 32nm: Future Challenges in Device Scaling,” Proc. of Intl. Workshop on Computational Electronics, pp. 1-6, 2009.

[39] S. Pidin, et al., “A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile and High Compressive Silicon Nitride Films,” IEEE International Electron Devices Meeting Technical Digest, pp. 213-216, 2004.

[40] K.W. Ang, et al., “Enhanced Performance in 50nm N-MOSFETs with Silicon-Carbon Source/Drain Regions,” IEEE International Electron Devices Meeting Technical Digest, pp. 1069-1072, 2004.

[41] Kelin Kuhn, “22nm Device Architecture and Performance Elements,” IEEE International Electron Devices Meeting Short Course, 2008.

AUTHORSBalaji Chandrasekaran is a marketing programs manager in the Silicon Systems Group at Applied Materials. He holds his M.S. in materials science and engineering from Northwestern University and an MBA from the University of California, Berkeley.

Khaled Ahmed is a distinguished member of technical staff in the Silicon Systems Group at Applied Materials. He received his Ph.D. in electrical engineering from North Carolina State University.

Tony Pan is a distinguished member of technical staff in the Silicon Systems Group at Applied Materials. He holds his Ph.D. in materials science and engineering from Cornell University.

Adam Brand is a director of the Transistor Technology group in the Silicon Systems Group at Applied Materials. He received his M.S. in electrical engineering from the Massachusetts Institute of Technology.

ARTICLE [email protected]


OPTIMIZING SPIKE ANNEALSfor 32nm and Beyond

KEYWORDS

Spike Anneal

Low-Temperature Anneal

Rapid Thermal Processing

Pattern Loading Effect

Residence Time

Multi-Point Temperature Control

Rapid thermal processing is becoming increasingly

challenging as shrinking geometries require the reduction

of yield-limiting thermal pattern loading effects (PLE),

smaller thermal budgets, and lower process temperatures.

However, an innovative approach to wafer heating now

minimizes PLE, while new techniques dramatically shorten

spike residence time to meet tight thermal budgets, and

transmission pyrometry enables closed-loop control to

below 75°C for achieving production-worthy repeatability

at process temperatures below 180°C.

Rapid thermal processing (RTP) continues to be an

important process in the VLSI circuit manufacturing

flow. Originally introduced for dopant diffusion and

annealing, the process space has steadily expanded into

a wider temperature processing regime and to lower

thermal budgets. Thermal processes now range from

relatively low temperatures (around 250°C and below)

for contact formation applications to very high tem-

peratures (greater than 1200°C) for substrate defect

anneals. At the same time, tighter thermal budget

requirements have driven the need for very short

annealing times, for example, “spike” annealing used

for diffusion engineering. Although this trend to shorter

anneal times has created some applications that cannot

be performed with traditional RTP (e.g., millisecond

annealing for contact nickel silicide formation), new

RTP processes are being introduced—these range from

thermal processes previously performed in furnaces to

thermal modifications of new materials.

Each application brings with it its own set of unique

challenges. Currently, a major challenge for spike

annealing is to minimize temperature variations arising

from variations in radiant energy absorption within a die.

These effects are generically called pattern effects (or

pattern loading effects, PLE) and result from variations

in optical properties (reflectivity, absorptivity, and dif-

fraction) within the die itself, as well as thermal heat

transfer from the surface to the bulk silicon beneath the

die. PLE is a strong function of the radiative flux incident

upon a surface. Thus, as ramp rates increase to reduce

total thermal budget, so do pattern effects.[1,2]

An additional challenge for spike annealing is the

reduction in thermal budget itself. Heat transfer occurs

in spike annealing primarily through radiation but also

through conduction and convection. Much attention

has focused on increasing the ramp rate of a spike

anneal to reduce the time taken to reach peak

temperature; now the limiting factor in the thermal

budget is the cooling rate of the wafer after the peak

temperature has been reached.

Finally, implementation of nickel and nickel alloy

silicides has been driving lower temperature RTP

processing. To enable this, the main problem to solve

is the temperature measurement itself. The limit today

with traditional optical temperature measurement

techniques is approximately 200°C. Alternative

measurement techniques will have to be employed to

accurately measure lower temperatures.

Here, we address these three aspects of RTP and demon-

strate significant improvement in each. To address PLE,

we explore lamp heating from the back of the substrate

and employ conduction through the bulk as the method

for heating the device. For thermal budget reduction,

we demonstrate increased cooling rates by employing

concepts to improve radiative, conductive, and convec-

tive heat loss. Finally, a novel temperature measurement

technique is tested for low temperature processing.


Pattern-Free, Low-Temperature Spike Anneal

Figure 1. (a) Simulated

temperature map with cold

region colored blue and

(b) measured temperature

range for a 750mm2 chip,

showing close correlation

between the two sets of data.[2]

Figure 2. (a) Checkerboard

wafer with poly/oxide film

stack and oxide film to

create large areas of extreme

reflectivity difference (0.485

vs. 0.816), implant on

backside.

MITIGATING PLESince the 65nm node, PLE in RTP has emerged as a

major yield limiter. Interference effects and reflectivity

variation resulting from layout details of the layers

present at the integration stage of the spike anneal

(e.g., STI, poly, and nitride spacers) lead to significant

temperature differences across each die. This in

turn leads to larger variations in critical transistor

performance parameters.[1,2] Figure 1 shows an ex-

ample of temperature differences across a chip during

a 1000°C, 150°C/s spike anneal. The top image is a

simulation of the temperature variation across a device

using the detailed optical properties of the chip layout to

predict the values. The bottom graph shows the actual

measurements, using temperature-sensitive test struc-

tures like ring-oscillators placed in the marked regions.

The simulation and the measurements match well,

confirming that this phenomenon is well understood.[2]

The temperature difference is a strong function of the

ramp-up rate due to the increased radiative energy flux

from the lamps during spike anneal.[1] Several methods

for mitigating the temperature variation have been

proposed, such as layout modifications to reduce the

variation of optical properties across the wafer, and

the application of absorption layers. Although these

methods can lead to significant improvements, they

also limit the flexibility of chip layout as well as process

flexibility, and certainly add cost.

The studies reported here aimed to devise a more robust

solution to the PLE problem by delivering radiation

solely to the wafer backside. Because the backside of

the wafer has uniform absorptivity and no structures,

radiative heating is very uniform. The heating of the

device region is accomplished by conductive heating

through the substrate. In this manner, a more uniform

temperature distribution is achieved across the device

and no layout modifications or absorption layers are

necessary.

To test the effectiveness of this approach, a patterned

wafer with extreme variation in absorptivity was created

comprising a 20mm checkerboard pattern of highly

reflective and highly absorptive film stacks (Figure 2).

The non-patterned side of the wafer received a BF2

implant at 3keV and dose of 1·1015cm-2, a typical

implant condition used for a spike monitor wafer. The

temperature sensitivity of this implant is 2.7Ohm/s/°C

and the target Rs is 240Ohm/sq for a 1050°C spike

anneal with a ramp rate of 220°C/s. The test wafer was

placed in a RTP chamber first with the patterned side

facing the lamps and then with the non-patterned side

facing them. As the results in Figure 2 demonstrate,

backside heating reduced the pattern-related tempera-

ture variation from more than 120°C to a level below

measurement noise. For a wafer like that shown in

Figure 1, it is, therefore, reasonable to expect a complete

absence of PLE.

Figure 1

(a)

(b)

-10 -7.5 -5 -2.5 0 2.5

�T Simulated (�C)

�T

Mea

sure

d (

�C)

2

0

-2

-4

-6

-8

-10

�T=8�C

R�=0.97

Figure 2

Checkerboard Wafer

Poly (570Å)/Oxide R ~ 0.485

Oxide (1700Å) R ~0.816

(a)



REDUCING RESIDENCE TIME PROFILESExtending spike anneal to next-generation nodes requires

faster ramp-up and cool-down rates to minimize the

spike residence time, generally defined as the time

taken for the wafer to reach the peak temperature

from 50°C below it and back down. The main effect of

shorter residence time is a reduction in lateral diffusion

length of the source/drain regions, which improves

the gate overlap capacitance and Vt roll off while

maintaining high Ion

/Ioff

.[3] While backside heating

eliminates the risk of PLE temperature variations, in

turn facilitating a faster ramp-up rate, accelerating the

cool-down rate is a different challenge. Cooling of the

silicon wafer is enhanced by improving the conductive,

radiative, and convective heat transfers. In these

studies, greater conductive heat loss was achieved by

gradually increasing helium gas flow during the recipe,

such that a 75°C/s cooling rate was obtained (red

profile in Figure 3). Radiative heat loss was increased

by chamber modifications to absorb heat in general.

This approach increased the cool-down rate from

75°C/s to 90°C/s (yellow profile in Figure 3). However,

to further improve cool-down, specifically after the

peak temperature was reached, the distance between

wafer and reflector was dynamically reduced during

the recipe. Wafer motion towards the reflector plate

provided additional convective heat transfer from the

gas exiting the space during the motion. This resulted

in the shortest residence time (green in Figure 3).

Whereas the radiative heat loss decreased strongly

with temperature, the conductive and convective parts

did not.

Figure 2. (b) Pattern-facing

lamps showed large temperature

fluctuation during spike and

extremely large Rs variation

along centerline, measured

on implanted side.

(c) Backside-facing lamps

showed good Rs uniformity.

Figure 2 (continued)

(b) (c)

Pattern to Lamps

Lamps

Reflector

Reflector

Lamps

Pattern to Reflector

>>5C, 3σ

-150 -100 -50 0 50 100 150

Wafer Diameter (mm)

Rs (

Oh

m/s

q)

800

700

600

500

400

300

200

78 80 82 84

Time (s)

Tem

per

atu

re (

°C

)

1100

1000

900

800

700

600

500

<5C, 3σ

-150 -100 -50 0 50 100 150

Wafer Diameter (mm)

Rs (

Oh

m/s

q)

800

700

600

500

400

300

200

88 90 92 94

Time (s)

Tem

per

atu

re (

°C

)

1100

1000

900

800

700

600

500



Figure 3. (a) Time/temperature

profiles of spike anneals

(using three methods to

improve cool-down) used to

calculate diffusion length for

boron based on an intrinsic

diffusion model.

(b) Experimental Rs/X

j plot

with BF2 implant using three

cool-down methods over a

range of temperatures.

Figure 4. (a) Experimental

time/temperature profiles

with actual wafer-level profiles.

(b) Rate of temperature

change calculated for the

same profiles.

Figure 3

(1)+(2)+(3)

(1)+(2)

(1)

6 7 8 9 10 11 12

Time (s)

Tem

per

atu

re (

�C)

1100

1050

1000

950

900

850

800

120

100

80

60

40

20

0

Diff

. Len

gth

(Arb

. Uni

ts)

(a) (b)

T-Res.-1.49s

T-Res.-1.09s

T-Res.-0.78s

Diff. Length-1.49s

Diff. Length-1.09s

Diff. Length-0.78s

Data-0.8s

Data-1.2s

Data-1.5s

Res.Time-0.75s

Res.Time-1.5s

Res.Time-1.2s

100 150 200 250 300 350

Xj @ 5.1018cm-3 (Å)

Rs (

Oh

m/s

q)

1100

1000

900

800

700

600

500

400

As Implanted Xj

BF2, 1keV, 1·1015cm-2

1082.92C, 1.55s

1053.64C, 0.77s

1054.66C, 1.54s1054.61C, 1.12s

1081.47C, 0.75s

Figure 4

4 6 8 10

Time (s)

Tem

per

atu

re (

�C)

600

550

500

450

400

350

300

20

18

16

14

12

10

8

6

4

2

0

Z-P

rofi

le (

mm

)

T1-No Move

T1-10mm/s 0.5s Delay

T1-10mm/s 1s Delay

T1-5mm/s 1s Delay

Profile-No Move

Profile-10mm/s 0.5s Delay

Profile-10mm/s 1s Delay


(a)

4 6 8 10

Time (s)

dT/

dt

(K/s

)

100

50

0

-50

-100

-150

-200

20

18

16

14

12

10

8

6

4

2

0

RR1-No Move

RR1-10mm/s 0.5s Delay

RR1-10mm/s 1s Delay

RR1-5mm/s 1s Delay

Profile-10mm/s 0.5s Delay



(b)

Waf

er D

ista

nce

fro

m R

P (

mm

)

Figure 4 illustrates results of the above experiments

using various dynamic wafer-level movements. All other

conditions remained constant. In all profiles, the lamps

shut off when the temperature reached 575°C and the

wafer-level movement was initiated after that as shown

in the graphs. Compared to the static wafer profile,

slow movement of the wafer toward the reflector

plate increased the cool-down rate approximately

proportionally as would be expected from the increase

in conductive heat transfer (red temperature profile).

However, faster movement produced a significant

increase in the cool-down rate. This effect can be

attributed to convective cooling action and makes

possible significant improvement in sharpening the

spike profile, even in lower temperature regimes.



IMPROVING PYROMETRY FOR LOW- TEMPERATURE RAPID THERMAL ANNEALAs silicide film thickness shrinks with each technology

node, process temperatures and times must be

correspondingly adjusted downward. Temperatures

lower than 250°C are required. Minimizing the thermal

budget while sustaining minimum reaction temperatures

necessitates low-temperature spike anneals.[4]

Achieving a production-worthy process poses a two-

fold challenge. First, temperature measurement with

conventional pyrometry reaches a fundamental limitation

at approximately 200°C due to the decreasing signal-

to-noise ratio between the thermal emission dictated

by the Planck relation and the background radiation.

Therefore, new methods for non-contact temperature

measurement must be developed. Second, to obtain

repeatable results for short processing times, multi-

point temperature control must be implemented for all

possible wafer properties from as low as 50°C.

To address the temperature measurement challenge,

the temperature dependence of the silicon substrate

itself is used to calculate temperature via a transmission

measurement. Figure 5 shows a closed-loop, ultra-low

temperature spike using this transmission pyrometry

method at four locations distributed from the center to

the edge of the wafer.

Figure 5

5 15 25 35 45 55 65

Time (s)

Tem

per

atu

re (

�C)

200

180

160

140

120

100

80

60

40

20

0

WaferSetpoint

CONCLUSIONSeveral recent advances expand the process window

for RTP. Backside heating has proven effective in

overcoming PLE regardless of device structures or

differences in material absorptivity. Dynamically

reducing the distance between wafer and reflection

plate during processing increases the rates of radiative,

conductive, and convective cooling, consistent

with smaller thermal budgets. New temperature

measurement techniques show promise for wafer

processing below the limits imposed by optical

pyrometry, suggesting that further reductions in

chamber processing temperature can be achieved.

REFERENCES[1] I. Ahsan, et al., “Impact of Intra-Die Thermal

Variation on Accurate MOSFET Gate-Length

Measurement,” ASMC, p. 174, 2009.

[2] P. Morin, et al., “Managing Annealing Pattern Effects

in 45nm Low-Power CMOS Technology,” ESSDERC,

2009.

[3] C.I. Li, et al., “Superior Spike Annealing Performance

in 65nm Source/Drain Extension Engineering,” RTP,

p. 163, 2005.

[4] S. Ramamurthy, et al., “Nickel Silicide Formation

Using Low-Temperature Spike Anneal,” Solid State

Technology, p. 37, October 2004.

AUTHORSWolfgang Aderhold is a senior member of the technical

staff in the Anneals and Epitaxy group of the Front End

Products business unit at Applied Materials. He holds

his Ph.D. in electrical engineering from Friedrich-

Alexander Universität, Erlangen, Germany.

Aaron Hunter is a senior director in the Anneals and

Epitaxy group of the Front End Products business unit

at Applied Materials. He received his B.A. in physics

from the University of California at Santa Cruz.

Shankar Muthukrishnan is a global product manager

in the Anneals and Epitaxy group of the Front End


his M.S. in environmental engineering from Texas A&M

University.


PROCESS SYSTEM USED IN STUDYApplied Vantage® Vulcan™ RTP

Figure 5. Temperature profile

for a low-temperature spike.

15 Volume 9, Issue 2, 2011 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.

To characterize the physical nature of the stacks, XPS

was used to accurately determine the thickness of the

interface layer and HfO2. AR-XPS was used to verify the

nitrogen profile in the stack after post high-κ nitridation,

and TEM to measure ALD step coverage. MOSCAP

devices were fabricated with thermal budgets mimicking

both “gate first” and “gate last” process flows to

quantify Jg and EOT values. Short-loop transistors (ring

gates) were used to investigate the impact of scaling on

electron mobility.

INTERFACE LAYER SCALINGThe oxide interface layer (IL) has a low-κ value; hence,

it is advantageous to focus on reducing the thickness

of this layer as it will produce a large effect on overall

EOT. Both rapid thermal oxidation (RTO) and radical

oxidation processes offer a means to scale the IL below

8Å, as measured by XPS.[7] For scaling the IL to 5Å

and below, the focus has been on radical oxidation

(N2O/H

2), which enables scaling it down to 2Å in a

controlled and repeatable fashion with a thermal budget

compatible with both gate first and gate last processes

(Figure 1). MOSCAP results verified equivalent Jg/EOT

performance for both high-temperature RTO and low-

temperature radox processes, confirming that no quality

was lost in using the latter (Figure 2a). In addition, ring

gate devices verified the expected mobility trend for both

processes (Figure 2b).[8] Although there is a decrease in

mobility from IL scaling due to the increasing proximity

of Hf atoms to the channel causing phonon scattering,

the reduction in EOT does boost transistor drive

current as defined by the following approximation,

Idsat∞ C

ox*μ*(V

g-V

t)^2*(W/L),

where Cox

is the gate capacitance, which is inversely

proportional to the EOT. The balance between IL scaling

for EOT reduction and its impact on mobility must be

optimized.

An alternative approach for IL formation is to use an

SC1 chemical treatment, which cleans the surface and

leaves an oxide layer of approximately 4Å. This type

of oxide has a much lower density than a thermally

grown oxide, which can be seen by comparing the large

discrepancy in thickness from optical ellipsometry

versus XPS. Current studies are examining the reliability

of this type of oxide versus thermally grown oxide;

results will be presented at a future date.

At ≤22nm, the dielectric gate stack must attain an EOT less

than 9Å without degrading gate leakage current, gate stack

reliability, or channel carrier mobility. Methods of extending

each unit process in the replacement gate are shown to

meet requirements for 20nm. In addition, process clustering

proves a means of improving gate stack control and quality.

In 2007, Intel announced the “biggest change in transis-

tor technology since the introduction of the polysilicon

gate MOS transistor in the late 1960s”[1,2] with the

industry’s first high-κ/metal gate product at the 45nm

node. From that time until now, other industry logic and

foundry leaders have announced their offerings for

high-κ/metal gate with variations in the integration

approach—gate first and gate last.[3-6] The high-κ

dielectric instantly provided relief to the equivalent oxide

thickness (EOT) scaling speed bump that came about

when SiON hit its limit due to the immense increase

in leakage current.[2] EOT scaling is required for both

performance boost (increase in Cinv

and improvement

to sub-threshold slope) and mitigating short channel ef-

fects, specifically drain induced barrier lowering (DIBL).

However, extending Moore’s Law to the 22nm and 14nm

nodes gives rise to high-κ gate stack scaling challenges.

The gate stack is composed of the interface oxide layer,

typically grown thermally or chemically, and the bulk

high-κ layer, deposited by either chemical vapor

deposition (CVD) or atomic layer deposition (ALD).

With each node, the stack thickness must scale down

to meet ever decreasing EOT targets (Table 1). To

reduce the EOT further, plasma nitridation can be

employed to incorporate a controlled dose of nitrogen

into the entire stack, followed by an anneal to stabilize

the stack. With this process flow, the 22nm Jg/EOT

targets can be met. However, manufacturing the stack

in a repeatable and reliable manner involves an

additional consideration. The dielectric gate stack is the

core of the transistor and is electrically very sensitive to

variation and quality. Both of these perturbations can be

reduced by (a) having a consistent and minimal queue-

time between each step, and (b) keeping the wafer

in a controlled vacuum atmosphere between steps.

Clustering each of the process chambers onto a vacuum

mainframe can satisfy these requirements.

Table 1

Node (nm)

EOT (Å)

IL Thickness (Å)

High-κ Thickness (Å)

32/28 9-12 7-10 20-23

22/20 6-9 4-7 17-20

16/14 4.5-6 0-3 15-18

KEYWORDS

High-κ/Metal Gate

Atomic Layer Deposition

Radical Oxidation

Plasma Nitridation

Process Clustering

INTEGRATING ATOMIC LAYER DEPOSITION HIGH-κ DIELECTRICSat the ≤22/20nm Logic Technology Node

Table 1. Target thickness

values by technology node


Advanced Effective Oxide Thickness Scaling

To characterize the physical nature of the stacks, XPS

was used to accurately determine the thickness of the

interface layer and HfO2. AR-XPS was used to verify the

nitrogen profile in the stack after post high-κ nitridation,

and TEM to measure ALD step coverage. MOSCAP

devices were fabricated with thermal budgets mimicking

both “gate first” and “gate last” process flows to

quantify Jg and EOT values. Short-loop transistors (ring

gates) were used to investigate the impact of scaling on

electron mobility.

INTERFACE LAYER SCALINGThe oxide interface layer (IL) has a low-κ value; hence,

it is advantageous to focus on reducing the thickness

of this layer as it will produce a large effect on overall

EOT. Both rapid thermal oxidation (RTO) and radical

oxidation processes offer a means to scale the IL below

8Å, as measured by XPS.[7] For scaling the IL to 5Å

and below, the focus has been on radical oxidation

(N2O/H

2), which enables scaling it down to 2Å in a

controlled and repeatable fashion with a thermal budget

compatible with both gate first and gate last processes

(Figure 1). MOSCAP results verified equivalent Jg/EOT

performance for both high-temperature RTO and low-

temperature radox processes, confirming that no quality

was lost in using the latter (Figure 2a). In addition, ring

gate devices verified the expected mobility trend for both

processes (Figure 2b).[8] Although there is a decrease in

mobility from IL scaling due to the increasing proximity

of Hf atoms to the channel causing phonon scattering,

the reduction in EOT does boost transistor drive

current as defined by the following approximation,

Idsat∞ C

ox*μ*(V

g-V

t)^2*(W/L),

where Cox

is the gate capacitance, which is inversely

proportional to the EOT. The balance between IL scaling

for EOT reduction and its impact on mobility must be

optimized.

An alternative approach for IL formation is to use an

SC1 chemical treatment, which cleans the surface and

leaves an oxide layer of approximately 4Å. This type

of oxide has a much lower density than a thermally

grown oxide, which can be seen by comparing the large

discrepancy in thickness from optical ellipsometry

versus XPS. Current studies are examining the reliability

of this type of oxide versus thermally grown oxide;

results will be presented at a future date.

Figure 1

450 500 550 600 650 700 750 800

Temperature (C)

XP

S T

hic

k (Å

)

9

8

7

6

5

4

3

2

1

0

Chem-Ox Thickness

SC1 Chem-Ox

HF-Last

LT RadOx 60s 1%H2

LT RadOx 5s 1%H2

Figure 2

(a)

Gate Last

Gate First

HfO2 Trendline

8 9 10 11 12 13 14 15

EOT (Å)

J g @ V

fb-1

(Å

/cm

2)

1.E+01

1.E+00

1.E-01

1.E-02

1.E-03

Jg/EOT

6Å IL

9Å IL3Å IL

3Å IL

Spike RTO

Low-Temp RadOx

Spike RTO

Low-Temp RadOx

(b)

IL Scaling Trendline

10 11 12 13 14 15

EOT (Å)

Mo

bili

ty (

cm2/V

s)

340

320

300

280

260

240

220

Peak Mobility

Internal MTCG Data

Internal MTCG Data

6Å IL

9Å IL

3Å IL

Figure 1. Radical oxidation

enables controlled, repeatable

IL scaling to 2Å for gate first

and gate last processes.

Figure 2. (a) MOSCAP

results showed equivalent

Jg/EOT performance for

high-temperature RTO and

low-temperature radox

processes.

(b) Ring gate mobility

decreased with EOT for both

along the expected trendline.


ALD HIGH-κ DEPOSITION AND POST TREATMENTSReplacing thermally grown oxide dielectrics with a

deposited dielectric (ALD HfO2) requires a highly

manufacturable process, in particular excellent

uniformity and low particle count.[9] The ALD high-κ

film used in these studies demonstrates 100% step

coverage in a very aggressive 10nm structure,

confirming its extendibility to emerging 3D transistor

structures (Figure 3).

Figure 3

10nm CD Trench with

7.0-8.6 Aspect Ratio

(Internal Wafer)

Figure 4 shows the scaling trend of oxide, oxynitride,

and HfO2, defined by the dielectric constant, band

gap and alignment, and tunneling effective mass.[10]

For higher-κ films, the slope of the Jg/EOT trendline

becomes steeper, reducing the EOT window for each

material. At this rate, the leakage for HfO2, is expected

to be too high for EOTs of less than ~7-8Å. To extend

HfO2 further, post high-κ plasma nitridation (typically

a 4-10% dose) provides 1-2Å of additional EOT scaling

(Figure 5), deferring the need for higher-κ materials to

<6Å.[11] A post-nitridation anneal removes metastable

Hf-O-N bonds.The EOT-reduction effect of nitrided

HfO2, derives from an increase in the film dielectric

constant (through greater electron and ionic

polarization).[12,13]

GATE STACK CLUSTERINGClustering of oxidation, plasma nitridation, and anneal

process chambers on a vacuum mainframe is well

established in high-volume manufacturing for SiON

gate dielectrics. This approach ensures short, consistent,

and vacuum-controlled queue-time between each

process step in the critical and sensitive gate stack

sequence. By adding a high-κ dielectric film to the gate

stack, two additional interfaces are introduced. At each

logic technology node reduction, the interface-to-bulk

ratio increases dramatically, making process clustering

ever more crucial. During a vacuum break, molecular

contaminants (e.g., C, N, O, F, Na, S) can be incorporated

into the gate stack interfaces. Previous studies have

shown a reduction in gate oxide integrity from the

introduction of hydrocarbons into the gate stack.[14]

Besides freedom from contamination, process control

is another vital advantage of gate stack clustering.

Figure 5 shows the growth in interface layer thickness

with increasing queue-time after an ultra-thin IL

process as compared to a clustered process (zero

queue-time data point). Data collected thus far suggest

tighter transistor characteristics (e.g., >30% reduction

in σVt) and >5% increase in mobility when gate stack

clustering is used.


Figure 4

(a)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

EOT (nm)

J g (Å

/cm

2)

102

100

10-2

10-4

10-6

SiO2

HfO

2 SiON

Doped H

igh-κ

(b)

5 6 7 8 9 10 11 12 13

EOT (Å)

Gat

e Le

akag

e (Å

/cm

2)

1e+2

1e+1

1e+0

1e-1

1e-2

1e-3

ALD HfO2

with Post

Nitridation

ALD HfO2

Figure 3. ALD high-κ

achieves 100% step

coverage of aggressive

aspect ratios.

Figure 4. (a) Jg/EOT trends

illustrate the narrower EOT

scaling window for each

material.

(b) Below 7-8Å, gate

leakage necessitates plasma

nitridation to obtain 1-2Å

further EOT scaling.


Figure 5

0 1 2 3 4 5

Queue-Time to ALD High-κ Deposition (Hours)

XP

S T

hic

knes

s (Å

)

4

3

2

1

0

Clustered Condition

EXTENDIBILITY TO 16NM AND BELOWTo further scale the EOT to meet 16/14nm node

requirements, reduction of the low-κ interface layer

to less than 3Å was investigated (Figure 1). This is the

limit of an SC1-last pre-clean. For ultra-thin to zero IL

formation, an HF-last type clean must be used. The

degree of control and interface quality necessary for

the gate stack require that a dry plasma gate pre-clean

be integrated on the same mainframe. MOSCAP data

show Jg/EOT performance equivalent to traditional

cleans, but with superior interface layer control resulting

from fixed and clustered queue-time. The κ-value of bulk

HfO2 must also be increased, which is accomplished by

incorporating a κ-boosting element, such as Ti, into the

matrix during ALD deposition. By so doing, the element

distribution in the layer can be carefully tailored.

CONCLUSIONThe consistent reduction in EOT at each subsequent

node necessitated by Moore’s Law poses new challenges

for the high-κ gate stack at 22nm and below. These EOT

scaling challenges can be addressed at each process

step in the gate stack sequence. Using low-temperature

radical oxidation, IL thickness can be reduced in a

controlled manner to less than 8Å. The κ-value of

the ALD HfO2 layer can be increased through post-

deposition plasma nitridation and anneal, reducing the

EOT by an additional 1-2Å. Clustering the IL and high-κ

processes improve control and quality. The impact

on transistor performance and reliability is still under

investigation, but initial data suggest improvement

in both electrical performance and distribution. The

proposed gate stack is extendible to 14/16nm nodes

by introducing integrated dry gate pre-clean, <2Å IL

formation, and higher-κ ALD films.

ACKNOWLEDGEMENTSThe authors would like to thank the entire high-κ ALD

team, the oxidation and nitridation team in FEP, design

and core engineering, GPS, TPS, CAT, DTCL, and MTCG.

REFERENCES[1] http://www.intel.com/pressroom/archive/

releases/2007/20070128comp.htm.

[2] K. Mistry, et al., “A 45nm Logic Technology with

High-κ + Metal Gate Transistors, Strained Silicon,

9 Cu Interconnect Layers, 193nm Dry Patterning, and

100% Pb-Free Packaging,” Proceedings of the IEDM,

pp. 247-250, 2007.

[3] M. Chudzik, et al., “High-Performance High-κ/Metal

Gates for 45nm CMOS and Beyond with Gate-First

Processing,” Symposium on VLSI Technology,

pp. 194-195, 2007.

[4] http://www.samsung.com/us/business/

semiconductor/newsView.do?news_id=1162.

[5] http://www.globalfoundries.com/

newsroom/2010/20100901_ARM.aspx.

[6] http://www.tsmc.com/tsmcdotcom/

PRListingNewsArchivesAction.do?action=

detail&newsid=4041&language=E.

[7] M.J. Bevan, et al., “Ultra-Thin SiO2 Interface Layer

Growth,” Proc. of the 18th Conf. on Adv. Thermal

Process. of Semic. – RTP 2010.

[8] J. Huang, et al., “Gate First High-κ/Metal Gate

Stacks with Zero SiOx Interface Achieving

EOT=0.59nm for 16nm Application,” Symposium

on VLSI Technology, pp. 34-35, 2009.

[9] A. Noori, et al., “Enabling ALD Hardware for High-κ

Dielectrics,” 10th International Conference on Atomic

Layer Deposition, 2010.

[10] Y.C. Yeo, et al., “MOSFET Gate Leakage Modeling

and Selection Guide for Alternative Gate Dielectrics

Based on Leakage Considerations,” IEEE Trans. on

Elect. Dev., Vol. 50, No. 4, pp. 1027-1035, 2003.

[11] S. Hung, et al., “ALD HfOx Scaling Through

Nitridation for 22nm and Beyond,” 10th International

Conference on Atomic Layer Deposition, 2010.


Figure 5. Increasing

interface layer thickness

with unclustered process

for ultra-thin IL.



[12] T. Ino, et al., “Dielectric Constant Behavior of

Hf-O-N System,” Jap J. of Appl. Phys. Vol. 45,

No. 4B, pp. 2908-2913, 2006.

[13] C.S. Kang, et al., “The Electrical and Material

Characterization of Hafnium Oxynitride Gate

Dielectrics with TaN-Gate Electrode,” IEEE Trans.

Elect. Dev., Vol. 51, No. 2, pp. 220-227, 2004.

[14] F. Tardiff, et al., “Hydrocarbons Impact on Thin Gate

Oxides,” Proc. of the Intern. Symp. on Ultra-Clean

Process. of Silicon Surf, pp. 309-312, 1996.

AUTHORSAtif Noori, is a global product manager in the ALD

division at Applied Materials. He holds his Ph.D. in

materials science and engineering from UCLA.

Steven Hung is an integration engineer in the HKMG

Technology Group of the ALD division at Applied

Materials. He received his Ph.D. in electrical

engineering from Stanford University.

Tatsuya E. Sato is a process member of technical staff in

the HKMG Technology Group of the ALD division at

Applied Materials. He holds his M.S. in mechanical

engineering from Hokkaido University, Japan.

Malcolm Bevan is gate manager of the Gate Stack and

Oxidation Products unit of the Front End Products

business unit at Applied Materials. He received his

Ph.D. in physical chemistry from Cambridge University.

Kenric Choi is a member of technical staff in the

ALD division at Applied Materials. He holds his B.S. in

mechanical engineering from San Jose State University.

Brendan McDougall is an integration engineer in the

Transistor Technology Group of Applied Materials. He

received his Ph.D. in physics from Brandeis University.

Johanes Swenberg is head of the gate and oxidation

product line in the Front End Products business unit at

Applied Materials. He holds his Ph.D. in applied physics

from the California Institute of Technology.

Maitreyee Mahajani is general manager in the HKMG

Technology Group of the ALD division at Applied

Materials. She holds her M.S. in materials science

from the University of Alabama.


PROCESS SYSTEM USED IN STUDYCentura® Integrated Gate Stack

(RadOxiL, ALD High-κ, DPN3, RadiancePlus Anneal)


EXTENDING OXYNITRIDE GATE TECHNOLOGYfor Advanced DRAM

Scaling the DRAM peripheral gate is key to advanced high-

performance, low-power devices, but current nitridation

processes are limited in achieving the optimal leakage and

threshold voltage. A new high-temperature, high-power

NH3 nitridation process with pulsed RF plasma generates

the higher nitrogen doses needed for the 3x/2x nodes

without deterioration of leakage and threshold voltage

performance.

DRAM devices with advanced power-management

features and faster access/storage rates are required to

keep pace with the rapidly expanding variety of mobile

devices. The subsequent performance scaling of the

dielectric gate has prompted successive advances in

oxynitride gate technology. This article discusses

the advantages of plasma nitridation in creating an

oxynitride film and the advances in extending this

technology over multiple generations.

Scaling the transistor to smaller dimensions requires

a gate dielectric with increased capacitance to control

short channel effects. Higher capacitance is achieved

by reducing the gate oxide thickness, but this increases

gate leakage. At thicknesses less than approximately

30Å, the leakage is unacceptably high when SiO2 is

used as the gate dielectric. Consequently, integrated

device manufacturers transitioned to nitrided oxide

(SiON). Over the past decade, nitridation treatments

have been used to incorporate nitrogen into previously

grown SiO2 film. Incorporating the SiON (oxynitride) as

the dielectric gate raises the gate dielectric constant,

thus reducing the equivalent oxide thickness (EOT),

while also reducing the gate leakage more than ten

times over SiO2.

Besides enabling device scaling, oxynitride gate

dielectrics are highly effective barriers to boron dopant

diffusion from the polysilicon gate, which would other-

wise result in unmanageable PMOS threshold voltage

shifts and degraded process control.

Over the past decade, operating powers have scaled

aggressively from 2.5V to operating voltages now

approaching 1.0V while, simultaneously, transfer

rates have increased from 1.0GB/s to those exceeding

20GB/s. Scaling the DRAM peripheral gate is key to

enabling this aggressive performance improvement.

PLASMA VS. THERMAL NITRIDATIONAlthough the first oxynitrides were processed by

annealing a grown SiO2 film in nitrogen-containing

chemistries, plasma nitridation has proven to be far

superior in performance, reliability, and extendibility.

Unlike thermal nitridation, which relies on temperature

to drive nitrogen into the oxide, plasma nitridation

employs a plasma source to expose the SiO2 oxide film

to a nitrogen-rich environment, thereby “dosing” it with

nitrogen. An RF generator creates an electric current

through two source coils (inner and outer) that oscillates

at 13.56MHz. The resulting synchronous oscillating

magnetic field generates an oscillating electric field

that initiates plasma ionization. The ensuing inductively

coupled plasma is “self-contained” in this electric field,

minimizing acceleration of the ions to the wafer surface.

Adjusting the input power modifies the ion density

KEYWORDS

Nitridation

Gate Stack

DRAM Peripheral Gate

Pulsed Plasma

Post-Nitridation Anneal


High-Temperature, Pulsed Plasma Nitridation

of the plasma, which, in turn, defines the amount of

nitrogen incorporated into the oxide layer. The inner

and outer coil design of the source allows for tuning

plasma density across the wafer to improve nitrogen

dose uniformity.

Figure 1 compares nitrogen depth profiles of a thermal

nitridation and plasma nitridation treatment.[1] The

former results in high nitrogen concentration at the

Si/SiON interface. Nitrogen has a deleterious effect

on device performance, both in the form of reduced

mobility and reduced negative bias temperature insta-

bility (NBTI).[2,3] On the other hand, plasma nitridation

concentrates most of the nitrogen near the top surface

of the oxynitride film, improving device performance

relative to thermal nitridation. By concentrating the

nitrogen near the top surface, higher nitrogen content

can be realized compared to thermal nitridation without

adversely affecting device performance.[1] In addition,

plasma nitridation at lower temperatures suppresses

unwanted dielectric gate thickening caused by thermal

processes, thus enabling greater scaling control.

Investigation of alternative process integrations

incorporating thermal nitridation has shown some

capability to shift the nitrogen profile toward the top

surface, but such efforts are inherently limited by the

thermal nature of the process.[4,5,6]

PULSED PLASMA The penetration of nitrogen ions through the dielectric

gate to the Si/SiO2 interface, potentially compromising

device performance, becomes of increasing concern

as the dielectric gate is thinned. Pulsing the plasma

avoids this effect.[2] Higher energy electrons diffuse to

the wall of the chamber during the off cycle, leaving and

cooling the plasma. The heavier ions are too slow to

escape. The net result is a significant reduction in the

electron energy of the plasma species (<0.5eV) without

a change in ion density. The plasma “softens” by this

shifting of the ion energy distribution to lower levels.

Figure 1. Comparison of

nitrogen profiles shows

nitrogen accumulation at

the Si/SiO2 interface with

thermal nitridation. Plasma

nitridation keeps nitrogen at

the top surface away from

the Si/SiO2 interface.

Figure 2. (a) Langmuir probe

measurements reveal lower kTe

and Vp when the RF plasma is

pulsed (green data). A 4X re-

duction is achieved at 10mTorr.

(b) Nitrogen ion-energy

distributions (10mTorr and fixed

effective RF power for modified

pulsed RF plasmas at 10kHz

and duty cycles <20%) show a

shift to lower ion energy levels,

i.e., “softer” plasma.

0 200 400 600 800

Sputter Time (s)

Seco

nd

ary

Ion

Co

un

ts

104

103

102

101

100

Thermal Nitridation

(a)

NO

0 200 400 600 800

Sputter Time (s)

Seco

nd

ary

Ion

Co

un

ts

104

103

102

101

100

Plasma Nitridation

(b)

SiON/Si InterfaceNO

SiON/Si Interface

Images courtesy of Toshiba

0 20 40 60

Pressure (mTorr)

No

rm. E

lect

ron

Tem

per

atu

re o

rN

orm

. Pla

sma

Pote

nti

al (

au)

1.0

0.8

0.6

0.4

0.2

0.0

(a)

pRF

CW

Vp

kTe

20%

5%

15%

10%

0.0 0.2 0.4 0.6 0.8 1.0

Normalized Ion Energy (au)

f(v)

(b)

CWPulsed RF (% Duty Cycle)

Figure 1

Figure 2



Langmuir probe measurements of kTe at 1µs intervals

reveal the periodic variations resulting from pulsed

plasma power. At the lower process pressures

(~10mTorr) optimal for high plasma density, kTe

for pulsed RF plasma is four times lower than for

continuous wave plasma (Figure 2a). The shift in

ion-energy level can also be represented by plotting the

ion-energy distributions (Figure 2b). (Although higher

pressures can be used as an alternative means of

lowering the ion energy, by decreasing the mean free

path, the subsequent drop in ion density results in lower

nitridation rates.[7]) The ensuing “softer” plasma further

ensures that nitrogen is incorporated only at the top

surface of the dielectric gate, thereby maintaining high

channel mobility.[3] This “softer” plasma results in a 15%

improvement in high-field effective mobility compared

to continuous wave plasma at a given nitrogen content

(Figure 3). This improvement reduces threshold voltage

shift, translating into an approximate doubling of

transistor lifetime.[2]

INTEGRATED POST-NITRIDATION ANNEALNitrogen incorporation into the dielectric gate shifts the

threshold voltage. The high sensitivity of threshold volt-

age to nitrogen content poses manufacturing challenges

as nitrogen concentration in the oxynitride decreases

over time following the nitridation treatment.[8] Figure

4a shows a greater than 10% drop in nitrogen content

over a short idle time after plasma nitridation, which

translates into a significant shift in threshold voltage.

A high-temperature (≥950°C) post-nitridation anneal

(PNA) immediately following the nitridation process

counteracts this nitrogen loss (Figure 4b). By clustering

the plasma nitridation and post-nitridation anneal on a

common platform, time-dependent process variability

can be removed, resulting in a stable and robust process

essential for manufacturing oxynitride gates.

The PNA also eliminates an unstable bonding phase

that results from plasma damage during the nitridation

process. This instability causes a fluctuation in electrical

(a) (b)Source: Reference 2.

1.0 1.5 2.0

Stress Voltage (V)

Life

tim

e (a

u)

102

10

1

10-1

10-2

10-3

10-4

Pulsed RFCW

10 12 14 16

Nitrogen Concentration (at. %)

PM

OS

I dsa

t* T

inv

1600

1400

1200

1000

800

Pulsed RF (15% Higher)

CW

Figure 3

Figure 4

Figure 4. (a) PMOS

threshold voltage shows a

significant shift as a function

of nitrogen content.

(b) A 15% drop in nitrogen

content occurs without PNA.

PNA counteracts the nitrogen

loss.

Figure 3. (a) Normalized

saturation drain current for

long channel PMOS transistors.

(b) NBTI lifetime estimate

(10% Idsat

degradation failure

criterion). The lower electron

temperature (“softer” plasma)

of pulsed plasma improves

high-field effective mobility by

15%, in turn improving NBTI

performance.

(a) (b)

0 5 10 15 20 25 30

Time to XPS (hrs)

No

rmal

ized

Nd

ose

100

95

90

85

80

20Å Base Oxide, ~20% N, 1000°C PNA

No PNA

With PNA

0 5 10 15 20

XPS N% (EW)

Vt S

hif

t (m

V)

vs. T

her

mal

Nit

rid

atio

n

Ref

eren

ce (

4%

)

300

200

100

0

-100

Vt Sensitivity

is 28mV/%N

PMOS 10Å Base Oxide

(PMOS 10Å Base Oxide)


characteristics and, hence, variation in the threshold

voltage. The high-temperature, post-nitridation anneal

not only removes this unstable phase, but also reduces

the defects brought about by plasma damage near the

high-mobility channel, further ensuring optimal device

performance.

HIGHER NITROGEN CONTENT PROCESSINGConventional nitrogen plasma nitridation begins to

approach a limit when scaling the dielectric gate to

thicknesses of approximately 20Å. Attempts to increase

nitrogen content can enable further EOT scaling;

however both leakage and threshold voltage require-

ments can no longer be met. A high-temperature, high-

power NH3 plasma satisfies all three requirements by

altering the trade-off between EOT, threshold voltage,

and gate leakage.

NH3 plasma consists primarily of NH radicals while N

2

plasma contains mostly N2 ions (Figure 5). It has been

theorized that ammonia’s propensity to dissociate in

plasma relative to that of nitrogen results in more

effective incorporation of nitrogen into the oxide film.[9]

However, NH3 plasma nitridation at room temperature

produces an unacceptably large shift in threshold

voltage for the same amount of nitrogen incorporated

(Figure 6a). Heating the substrate during nitridation

eliminates the threshold voltage shift and also improves

EOT scaling (Figure 6b). The additional process space

made available by the shifted threshold voltage versus

EOT trade-off may then be exploited to improve leakage

performance by increasing the nitrogen dose.

NH3 chemistry is introduced into the chamber in a

fashion similar to that used for earlier nitrogen

chemistry, with an added insulated gas box to ensure

safe delivery of the toxic chemistry. The necessary high

temperature is provided by an electrostatic chuck that

delivers direct and more stable heating of the wafer

than is possible with a heated pedestal that relies on

convective heating. Although a heated pedestal can

achieve higher starting temperatures, the convective

nature of the heater causes wafer temperature to drop

during the reduced-pressure plasma process. This

results in a highly variable process temperature with an

overall lower average. In comparison, an electrostatic

chuck demonstrates a stable and robust temperature

over the entire process (Figure 7).

High power is necessary to compensate for the lower

nitridation rates associated with NH3 plasma. Pulsing

delivers a “soft” plasma at elevated RF power and

temperature. Combining these conditions with an

integrated PNA on a common platform delivers superior

production-worthy, plasma nitridation capability.

Figure 5

300 310 320 330 340 350 360 370 380 390 400

Wavelength (nm)

OES

In

ten

sity

(au

)

7000

6000

5000

4000

3000

2000

1000

0

N2

+

353.3,353.8,354.9,356.4,358.2

N2

357.7

N2

353.7

N2

350.0

N2

380.5N

2

399.8

N2

394.3

N2

+

391.4

NH337.0

NH336.0

N2

337.1

N2

315.9

N2

313.6

N2

311.7 N2

389.5

N2

375.5

N2

371.1N2

367.2

N2

328.5N

2

326.8

N2 Plasma

NH3 Plasma


Figure 5. Optical emission

spectroscopy highlights the

species difference between

N2 and NH

3 plasmas.

Figure 6. (a) Elevated process

temperature eliminates the

shift in threshold voltage that

occurs in room-temperature

NH3 plasma.

(b) NH3 plasma improves

EOT scaling compared to

N2 plasma for given nitrogen

content.

Figure 6

(a)

20 22 24 26 28

ReVera N%

Th

resh

old

Vo

ltag

e (V

)

Room Temperature NH3

High Temperature NH3

Target Performance

50mV

1.85 1.9 1.95 2.00

Equivalent Oxide Thickness (CET@1V - 0.45) (nm)

Th

resh

old

Vo

ltag

e (V

)

(b)

10mV

NH3

N2

17.5% N

20% N


Figure 7

Time

Tem

per

atu

re (

�C)

550

500

450

400

350

300

Wafer Chuck

Wafer DechuckPlasma On

Plasma On

Pre-Heat andGas Stabilization

Gas Stabilization

DPN HD (500�C)

Heated Pedestal (550�C)

CONCLUSIONCombining a high-temperature, high-power NH

3 plasma

nitridation with pulsed RF plasma and an integrated

PNA satisfies EOT scaling, leakage, and threshold voltage

requirements for next-generation DRAM peripheral

gates and offers an attractive alternative to the costly

transition to high-κ dielectric gates. Furthermore, a

unique feature of the NH3 chemistry is the formation of

NH radicals in the plasma, which is typically associated

with greater process conformality. As device structures

transition to 3D, this property may facilitate new

nitridation applications utilizing NH3 plasma.

REFERENCES[1] B. Chow, et al., “Extending Silicon Oxynitride Gate

Dielectrics for the 90nm Node,” Semiconductor FabTech, 17th Edition – Wafer Processing, pp. 107-109, 2002.

[2] P.A. Kraus, et al., “Low-Energy Nitrogen Plasmas for 65nm node Oxynitride Gate Dielectrics: A Correlation of Plasma Characteristics and Device Parameters,” VLSI, 2003.

[3] P.A. Kraus, et al., “Further Optimization of Plasma Nitridation of Ultra-Thin Oxides for 65nm Node MOSFETS,” Semiconductor FabTech 23rd Edition – Wafer Processing, pp. 73-76, 2004.

[4] S. Inaba, et al., “Device Performance of Sub-50nm CMOS with Ultra-Thin Plasma Nitrided Gate Dielectrics,” IEEE-IEDM, pp. 651-654, 2002.

[5] T. Sasaki, et al., “Engineering of Nitrogen Profile in an Ultra-Thin Gate Insulator to Improve Transistor Performance and MBTI,” IEEE Electron Device Letters, Vol. 24, No. 3, pp. 150-152, 2003.

[6] S.H. Hong, et al., “The Development of Dual-Gate

Poly Scheme with Plasma Nitride Gate Oxide for

Mobile High Performance DRAMs: Plasma Process

Monitoring and the Correlation with Electrical

Results,” IEEE ICICDT, pp. 219-222, 2004.

[7] H.H. Tseng, et al., “Ultra-Thin Decoupled Plasma Ni-

tridation (DPN) Oxynitride Gate Dielectric for 80nm

Advanced Technology,” IEEE Electron Device Letters,

Vol. 23, No. 12, pp. 704-706, 2002.

[8] A.Hegedus, et al., “Clustering of Plasma Nitridation

and Post Anneal Steps to Improve Threshold Voltage

Repeatability,” IEEE Transactions on Semiconductor

Manufacturing, Vol. 16, No. 2, pp. 165-169, 2003.

[9] T. Bieniek, et al., “Ultra-Shallow Nitrogen Plasma

Implantation for Ultra-Thin Silicon Oxynitride (SiOxN

y)

Layer Formation,” Journal of Telecommunications

and Information Technology, pp. 70-75, 2005.

AUTHORSDavid Chu is global product manager of the Gate Stack

and Oxidation Products unit of the Front End Products

business unit at Applied Materials. He received his

Ph.D. in materials science and engineering from the

University of California, Berkeley.

Wei Liu is a senior member of technical staff in the

Gate Stack and Oxidation Products unit of the Front End


his Ph.D. in chemistry from the University of British

Columbia, Canada.

Theresa Guarini is a process engineer in the Gate Stack


business unit at Applied Materials. She received her

Ph.D. in applied physics from Stanford University.

Nathan Sanchez is program manager for the Gate Stack


business unit at Applied Materials. He holds his B.S.

in mechanical engineering from the Massachusetts

Institute of Technology.


PROCESS SYSTEM USED IN STUDYApplied Centura® DPN HD™


Figure 7. Process

temperature-time profiles

for electrostatic chuck and

heated pedestal demonstrate

temperature stability during

the plasma process when

using the chuck.


IMPROVING TUNGSTEN CHEMICAL MECHANICAL PLANARIZATIONfor Next-Generation Applications

KEYWORDS

Tungsten

CMP

Slurry

Pad

Planarization

Tungsten CMP is becoming a more frequent and

challenging process in advanced integrations. Here,

preservation of device topography through precision

planarization end-pointing is crucial to successful device

performance. Future applications, such as 3D memory

structures, will demand even greater removal control, while

lower costs and higher productivity will be necessary if

these new integration schemes are to be cost competitive.

Dual-wafer polishing and real-time process control will help

satisfy these diverse requirements.

Tungsten is used throughout the transistor creation

level, i.e., front-end, of advanced 3D memory in buried

word line and buried bit line, local interconnects, and

contacts to transistors. Tungsten is favored over other

metals for its large thermal budget for subsequent

processing steps. In addition, tungsten’s conductivity,

lack of diffusion/interaction with other materials and

proven performance in logic and memory devices also

make it the likely metal for next-generation applications.

Like other metal CMP applications, the fundamental mechanism for tungsten removal is based on oxidizing the metal surface and subsequently abrading the metal oxide to expose a new layer of unoxidized metal. This process repeats itself until all the metal is removed over a stop layer (typically a dielectric material, e.g., TEOS, USG), which is also referred to as clearing the metal. The remaining metal in the via or trench undergoes further removal (metal dishing) by this oxidation process. Controlling the removal process to clear the tungsten over oxide and ensure uniform removal within the dies, both within wafer (WiW) and wafer-to-wafer (WtW), is the key to meeting next-generation tungsten CMP performance requirements.

This article looks at two technologies to help improve tungsten CMP performance and lower costs. First, it shows how adapting an in-situ tungsten thickness sensor and a multi-zone polishing head improves WtW, WiW, and within die uniformity. Second, it investigates dual-wafer tungsten CMP and its ability to lower costs. The combination and synergy of these two technologies in a single product enables tungsten CMP for future on-wafer performance, throughput, and cost requirements.

EXPERIMENTAL SET-UPDual-wafer and single-wafer polishing platforms were used in these comparative studies. Both were equipped with production-proven stacked polishing pads comprising a top pad composed of a high durometer polyurethane over a high compression sub-pad, i.e., a hard pad, with concentric grooves. For these experi-ments, the polish slurry was a silica-based abrasive slurry with 2% H

2O

2. The polishing test was conducted

on both blanket tungsten and test pattern wafers. An RS-100 four-point probe and an eddy current sensor measured blanket tungsten film thickness and profile.


Real-Time Process Control

TUNGSTEN REMOVAL PROFILE CONTROLProfile control has been implemented for 300mm tungsten CMP via closed-loop, real-time WiW control of bulk tungsten removal. The method uses a high- resolution sensor for in-situ measurement of tungsten thickness across the wafer during polishing. The high-resolution sensor is a critical component of process control technology due to the challenge of the relatively high resistance of the relatively thin tungsten film. The bulk tungsten removal process is controlled via real-time, in-situ incremental changes to polishing conditions, using a multi-zone polishing head. These controls have demonstrated more uniform tungsten clearing, resulting in lower and more consistent WiW tungsten and dielec-tric loss than is possible with an open-loop process.

Figure 1 shows the elements of the control system. The eddy current-based sensor makes in-situ, millimeter-scale measurements of tungsten thickness from the center to the edge of the film.[1] During polishing, the software model instantaneously analyzes the tungsten

thickness profile and determines which areas are

diverging from the target. It then generates incremental

modifications to the polish recipe parameters, feeding

these forward to the CMP system at discrete, user-

defined intervals to correct the deviations.

The process control model is constructed from a

physical model of the hardware components and the

characteristic response of the tungsten CMP process

for a given set of input parameters. The system can

be adapted to a variety of input parameters, including

pressure, velocity, and slurry flow. The polish head

incorporates multiple independent annular pressure

zones located behind the wafer. The simple graphical

user interface allows the user to optimize system

performance by adjusting relatively few parameters.

The evolution of the tungsten film profile during a CMP

process is shown in Figure 2, in which the open-loop

polish (Figure 2a) was conducted with fixed input

pressures and the closed-loop polish (Figure 2b) with

variable input pressures on different zones depending

on signal feedback. Polishing conditions were the same

Figure 1. (a) Schematic

of eddy current sensor

for tungsten thickness

measurement.

(b) Elements of the closed-

loop profile control system.

Figure 2. (a) Open-loop and

(b) closed-loop polishing

profiles of tungsten films at

3.5psi, and (c) a film profile

comparison.

Figure 1

Figure 2

(a) (b) (c)

Closed LoopOpen Loop

-150 -75 0 75 150

2000

1500

1000

500

0

-150 -100 -50 0 50 100 150

Position (mm)

Tun

gste

n T

hic

knes

s (Å

)

1600

1400

1200

1000

800

600

400

200

0

-150 -75 0 75 150

4-point Probe Measurements

Open Loop (1 wafer)

Closed Loop (4 wafers)

Udrive

Usignal

(a) (b)

D can be correlated to:

- Usignal

(amplitude)

- Phase di�erence between U

drive and U

signal

BulkConductor

Layer

Electromagnetic Sensor

Eddy Current

Driving Flux

Opposing Flux

Wafer

D

ProfileError

Desired Profile

Incremental Adjustment

In-Situ ProfileMeasurement

CMP System

Wafer

Process ControlSoftware Model



at the start of both experiments. Under open-loop

conditions, the polish rate at the edge dropped over

time, resulting in an edge-thick profile of the remaining

film (edge thickness of 450Å vs. center thickness of

250Å). Under closed-loop conditions, the system

increased the pressure to the edge zones as polishing

proceeded, achieving a much more uniform post-polish

profile. The 200Å difference in edge thickness remaining

between the two polish modes is significant as the post

profiles are compared in Figure 2c.

Figure 3

-150 -100 -50 0 50 100 150

Wafer Diameter (mm)

Tun

gste

n F

ilm

Po

st T

hic

knes

s(Å

, Ed

dy

Cu

rren

t M

easu

rem

ent)

2000

1800

1600

1400

1200

1000

800

600

400

200

0

Side A

Side B

Figure 4

200 300 400 500 600

Prestonian, Pressure x Linear Velocity(psi*inch/sec)

Rem

oval

Rat

e (Å

/min

)

(b)

5000

4000

3000

2000

1000

0

Dual Heads per Platen

Single Head per Platen

100 200 300 400 500 600

Prestonian, Pressure x Linear Velocity (psi*inch/sec)

Rem

oval

(Å

, 60

sec)

(a)

2000

1500

1000

500

0

42” Platen

30” Platen

4psi/115rpm

4psi/115rpm3psi/73rpm

3psi/73rpm

DUAL-WAFER POLISHING OF TUNGSTENA dual-wafer polishing configuration was developed

to advance CMP manufacturing capabilities in which

two wafers were polished simultaneously on the same

platen (42-inch). The two heads were controlled

independently with dedicated pressure regulators and

closed-loop control systems. Figure 3 demonstrates the

closely matched performance on the two wafers.

In describing its polish rate as a function of platen

revolutions per minute and polish pressure, tungsten

CMP closely follows the Preston equation RR = k*P*V,

where:

RR = removal rate

k = empirical constant taking into account such

parameters as polishing pad surface and slurry

availability at the wafer’s surface

P = average polishing pressure at the wafer’s surface

V = average polishing velocity between wafer and

pad surfaces

As shown in Figure 4, the rate of tungsten removal is

linearly proportional to the down force and the linear

velocity experienced at the wafer surface. The linearity

is almost independent of the polish system as the data

from a 30-inch platen system and those from a 42-inch

platen closely match a single fit line. The smaller

diameter of the 30-inch platen limits the process

window whereas a 42-inch platen widens it and

enhances the removal rate by 50%.

Figure 4 also illustrates the increase in removal rate

achieved by using a dual-wafer platen. While each

wafer can still be independently controlled, an

additional synergy occurs when two wafers share the

same platen. This synergy dramatically enhances the

polish rate and significantly reduces slurry consumption.

In our tests, we observed an average of 20%

enhancement in productivity and 50% savings in slurry

usage. The rate enhancement also enables flexibility

in pad selection. Pads that are typically eliminated

on the basis of a lower removal rate can be reconsid-

ered for their superior defect performance and/or

cost advantage. Figure 5 illustrates a typical example

of pattern wafer performance. The tungsten plugs

remained intact after polish with very minimum plug

topography (24Å).

Figure 4. (a) Tungsten

CMP exhibits the Prestonian

relationship regardless of

platen size, but (b) dual-wafer

polishing increases the

removal rate.

Figure 3. Comparison of

in-situ, real-time tungsten

film profile monitoring with

closed-loop control on dual

heads A and B.



PERFORMANCE CONSISTENCYIn a 5000-wafer marathon to test the validity of the

above studies, the tungsten CMP process demonstrated

a consistent removal rate of 3700Å/min with average

WiW non-uniformity of less than 2.1% and WtW non-

uniformity of 3.7%. With the eddy current sensor, the

consistent polishing performance results in accurate

in-film stopping capability (Figure 6).

CONCLUSIONReal-time process control enables the greater precision

and uniformity of tungsten removal and dishing required

for next-generation devices, such as 3D memories. In

addition, real-time process control enables dual-wafer

polishing in a production environment. Real-time process

control ensures the same on-wafer performance for

both of the wafers being polished. Dual-wafer polishing

inherently improves productivity/throughput, but

more importantly uses substantially less slurry without

compromising removal rate, uniformity, and defectivity.

By combining both technologies in a single product,

both on-wafer performance and productivity/cost for

future tungsten CMP applications can be achieved

simultaneously.

REFERENCES[1] D. Bennett, et al., “Real-Time Profile Control:

Advanced Process Control for Copper CMP,”

Semiconductor Fabtech, Vol. 22, pp. 33-35, 2004.

AUTHORSSidney Huey is a global product manager in the Chemical

Mechanical Planarization business unit at Applied

Materials. He holds his M.S. in mechanical engineering

from Princeton University.

Stan Tsai is a technology manager in the Chemical


Materials. He received his Ph.D. in chemistry from

the University of Alberta, Canada.

Zhefu Wang is a process engineer in the Chemical


Materials. He holds his Ph.D. in mechanical engineering

from Oregon State University.

Rixin (Vince) Peng is a process engineer in the

Chemical Mechanical Planarization business unit at

Applied Materials. He received his B.S. in chemical

engineering from the University of California, Berkeley.


PROCESS SYSTEMS USED IN STUDYApplied Reflexion® GT™ CMP

Applied Reflexion® LK™ CMP

Figure 5. Tungsten CMP

performance on patterned

wafers (Applied Materials

internal test pattern, 50nm

plug arrays). (a) SEM shows

intact plugs and (b) AFM

shows minimum plug recess.

Figure 6. Consistent in-film

stopping at 650Å remaining

through 5000-wafer marathon.

Figure 5

FOV = 3μm

(a)

0 200 400 600

nm

nm

(b)

9.5

0

-9.5

Plug Recess = 24Å

Section Analysis

Figure 6

0 1000 2000 3000 4000 5000

Wafer #

Rem

ain

ing

Th

ickn

ess

(Å, @

28

% E

P)

1000

900

800

700

600

500

400

300

200

100

0

10% Control Line

Day 1 Day 2 Day 3 Day 4 Day 5WetIdle

WetIdle

WetIdle

WetIdle


Complex multi-level logic and memory structures require

a large number of thin conformal oxide layers, but low

thermal budgets rule out furnace processes. Additionally,

conformality and pattern loading effects become significant

challenges at the aggressive aspect ratios and high feature

densities of sub-20nm geometries. A new low-temperature

process deposits an oxide film with conformality and

pattern independence similar to atomic layer deposition,

but scalable from 10Å to 300Å at high productivity, making

it suitable for diverse applications.

With device geometries shrinking to sub-20nm levels,

the integration schemes for manufacturing complex

multi-level logic and memory structures require an

increased number of applications for thin conformal

oxide films (typically 10Å-300Å thick). Besides good

conformality, these applications require minimal to no

pattern loading and film properties similar to those of

thermal oxides. Further, at advanced technology nodes,

the thermal budget of these liners is limited to less

than 400°C. Furnaces have historically been used for

thin oxide film deposition, but they typically operate at

much higher temperatures (>600°C) and film properties

and deposition rates degrade as the thermal budget

is lowered. Atomic layer deposition (ALD) techniques

can provide near 100% conformality and zero pattern

loading, but deposition rates are extremely low and

productivity concerns rule out scaling these technologies

for mid-range thicknesses nearing 300Å.

An ALD-like conformal oxide film that deposits at low

temperatures has been developed to address the thermal

budget concerns for these thin oxide liners. This ALD-

like process uses a new silicon precursor with low

sticking coefficient to achieve near 100% conformality

and minimal pattern loading, as well as high deposition

rates and extremely good film quality. Further, the

process can be scaled from very thin films approaching

10Å up to 300Å at high productivity, making it suitable

for an array of spacer and thin oxide film applications.

EXPERIMENTAL SET-UP AND RESULTSThe reactor used for this film was a modified HARP

design[1] with the unique capability of in-situ plasma

treatments using different inert gases, which densify

the film and result in lower wet etch rate ratios (WERR).

It also allows for cyclic processing similar to ALD

reactors with plasma treatments. Precursor flow control

and hardware were optimized to enable uniform mixing

of individual reactants, facilitating the short deposition

times necessary for thickness control in the angstrom

regime.

For process development, such parameters as

temperature, precursor flow, oxidative ambient

flow/concentration, and heater spacing were varied.

Step coverage and pattern loading effect (PLE) were

evaluated using cross-sectional TEM images. Based on

these experiments, a process regime was identified that

shows extremely good conformality and minimal PLE.

Figure 1 shows several examples. Figure 1a is a cross-

KEYWORDS

ALD

Liner

Oxide

Low-Temperature

Conformal

Pattern Loading Effect

A HIGH PRODUCTIVITY ALD-LIKE CONFORMAL OXIDE LINERfor ≤20nm Technology Nodes


ALD-Like High Productivity Oxide Liner

section of TEM images of via features with ~2:1 aspect

ratio. The images were taken in the via array center

and the via array edge. The TEM measurements reveal

>99% film conformality. Figure 1b shows the ALD-like

oxide liner deposited on 4:1 aspect ratio structures on a

dense array of trenches and a trench feature adjacent to

a wide open area. Here, the film was >99% conformal

and PLE measured only ~3Å from the dense sidewall

thickness to the thickness in the open field. For oxide

liner applications in deep trenches, such as shallow

trench isolation (STI) liners or buried word lines and

buried bit lines in advanced DRAM, the oxide liner

conformality was also measured in high aspect ratio

(7:1) STI features. Figure 1c shows an STI structure on

which >99% conformality was achieved.

The low deposition temperature (350°C) makes the

new liner suitable for a variety of advanced applications

in which lowering the thermal budget is critical. Several

in advanced memory and logic require oxide deposition

on metals, such as TiN or W (e.g., on a gate in logic

or flash, or a word or bit line in memory). Higher

temperatures are not suitable because of the oxidation

of the underlying metal, which may inherently increase

the resistivity of the metal line. The TEMs in Figure 2

show deposition on W and TiN with virtually no

oxidation of the underlying metal.

Figure 2

Pre ~150Å Oxide Liner

50

0Å

TiN

Su

bst

rate

50

0Å

W S

ub

stra

te

20nm 20nm

20nm 20nm

14.8nm

50.1nm

47.6nm48.3nm

3nm 3.5nm

17.2nm

Minimal oxide growth after liner dep

35Å oxide after liner dep

30Å oxide prior to liner dep

Figure 1. The new liner

exhibits >99% conformality

on aspect ratios from

(a) a 2:1 via to (b) 4:1

trenches to (c) 7:1 STI in

addition to minimal PLE.

Figure 1

Before Liner With Liner Deposited

(b) (c)

100nm

Step Coverage: Sidewall/Top: 100%; Bottom/Top: 100%

Pattern Loading E�ect: Top/Open: 96%; Sidewall/Open: 96%

Dense Dense and Open

(a)

23.9nm

24nm

24.2nm

24nm

24nm

50nm

Via at Pattern Edge Center Via

1.00um

71Å

71Å

69Å

71Å

71Å 71Å

71Å

74Å

74Å

69Å

50nm 50nm 500nm6/28/2010

24.1nm

Figure 2. Low-temperature

deposition of new oxide liner

allows for deposition on

metal lines without oxidation

of underlying metal.



Electrical properties for the new oxide liner were

obtained on both planar and 3D MOSCAP structures.

For a planar MOSCAP, the top and bottom electrodes

are separated by a dielectric in the horizontal plane

(Figure 3). The 3D MOSCAP is conceptually similar

to a planar MOSCAP, except that the dielectrics

between the two electrodes are no longer planar. Three

dielectrics are present: SiN on top of the silicon fin, a

sidewall dielectric, and a bottom STI oxide. The sidewall

dielectric is designed to be much thinner than the top

SiN and bottom STI oxide, thus all current-related

measurements are dominated by the sidewall. The

total sidewall area is designed to be much larger than

the area of the top SiN and bottom STI oxide. The total

measured capacitance is dominated by the sidewall

dielectric due to this combination of much larger area

and much thinner dielectric. The oxide liner exhibited

excellent electrical and isolation characteristics. Figure

3 shows planar MOSCAP I-V data for 100Å of conformal

oxide compared to 100Å of high quality thermal oxide,

demonstrating a higher breakdown voltage (>10MV/cm)

for the new liner. Also shown is the sidewall breakdown

voltage (using 3D MOSCAP wafers), which measures the

insulation and electrical characteristics of the film on the

sidewall. Again, the oxide liner performance was superior

to those of a 100Å high quality thermal oxide film.

The modified HARP reactor allows for in-situ

densification of the oxide liner using plasma treatments.

These can be cycled in blocks of thickness depending

on the final thickness and WERR requirement of the

film. Several applications for new oxide liners require

improved WERR in wet clean environments. The new

oxide liner exhibits a WERR of <2.3 in 100:1 DHF

compared to thermal oxides. The improvement in film

quality with the plasma treatment manifests itself in

film stress stability as a function of time, as well as

Fourier-transform infrared (FTIR) spectra. Figure 4

shows excellent film stress stability over time in

addition to FTIR spectra confirming good quality oxide

with no Si-H, Si-OH or C present.

Figure 3. (a) Cross-section

of planar MOSCAP and 3D

MOSCAP.

Figure 3. (b) (c) Excellent

breakdown voltage on both

planar and 3D MOSCAPS.

Figure 3

0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0

Vbd

(mV/cm)

I (A

mp

s)

1.00E+00

1.00E-02

1.00E-04

1.00E-06

1.00E-08

1.00E-10

1.00E-12

2X 50Å

100Å Thermal Oxide Film

(b)

2X 50Å

100Å Thermal Oxide Film

(c)

0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0

Vbd

(mV/cm)

I (A

mp

s)

1.00E+00

1.00E-02

1.00E-04

1.00E-06

1.00E-08

1.00E-10

1.00E-12

(a)

Pad Metal

Poly

Gate Dielectric

Si

Planar MOSCAP

Pad Metal

SiNPo

lyGateDielectric

SiO

2

3D MOSCAP



DISCUSSIONAdvanced semiconductor fabrication requires thin films

to be deposited uniformly on patterned structures with

varying geometries (trenches, fins, vias, and islands) and

a wide range of aspect ratios. Line-of-sight processes

(PVD, PECVD) do not provide good conformality on

aggressive structures, but ALD and CVD provide viable

alternatives. CVD processes in certain growth regimes

are capable of high conformality without sacrificing

film growth rates. In the CVD literature, the problem of

identifying conformal growth regimes is addressed by

the surface reaction probability ß (also called sticking

coefficient), defined as the probability that a precursor

molecule will adsorb to form a film per unit molecular

collision.[2,3] For high conformality, lower values of

ß are preferred, which implies that the precursor

consumption rate is low, resulting in a smaller gradient

in precursor partial pressure with increasing depth in

the feature.[4]

The new ALD-like process lowers the surface reaction

probability ß by changes in process, as well as by

employing a new precursor for film growth. The two

key features of the new process regime that improve

conformality are high pressure (>500Torr) and choked

oxidative ambient flow. Higher pressure reduces the

precursor partial pressure gradient from feature top to

bottom and the choked oxidative ambient flow reduces

the precursor consumption rate. Both these parameters

help to operate in a surface reaction limited regime with

lower values of surface reaction probability ß.

The improved conformality with the new precursor is

attributed to the reduction in the concentration of the higher order intermediates and their participation in film growth. As shown in Figure 5, the new precursor forms a stable intermediate while higher order reactive species like poly-siloxanes are not formed (These heavier species have low mobility and much higher sticking coefficients, leading to an increased surface reaction rate and severely worsening film conformality.) The secondary reactive species are produced by gas phase reactions and/or surface reactions on the trench walls and thus have a higher concentration gradient (with feature depth) than that of the first order intermediates.

PLE has been another major concern with traditional

CVD oxide liners as the deposition rate is inversely

correlated with the pattern area density of the

Figure 4

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Time (hrs)St

ress

(M

Pa)

0

-20

-40

-60

-80

-100

-120

-140

-160

(a)

3900 3400 2900 2400 1900 1400 900 400

Wavenumber (cm-1)

Ab

sorp

tio

n (

au)

0.25

0.2

0.15

0.1

0.05

0

-0.05

(b)

Si-O Stretch

Si-OStretch

Si-OBend

5min1hr2hr3hr

Figure 5

TEOS as Precursor

(Silanol)

OC2H

5

OC2H

5

OC2H

5

OC2H

5Si

OC2H

5

OH

OC2H

5

OC2H

5Si+O

3

(Higher Order Silanols)

OC2H

5

OH

OC2H

5

OC2H

5Si2x Si SiO

New Precursor

H

R1

H

R2 Si +O3

OO

H-O

R1

H

R2 Si

OOOH

R1

H

R2 SiR1

H

O Si

Figure 5. The >Si=O

moieties of the new

precursor are very stable

and no further polymeriza-

tion is possible to bigger

chains. Low sticking coef-

ficient of these monomers

promotes less selective and

highly conformal film growth

with minimal PLE.

Figure 4. (a) The new oxide

shows stable compressive

stress (-135 MPa) over time,

while (b) FTIR spectra show

stable film without detectable

C or H bonds.


Figure 6

Th

ickn

ess

(�)

Conformal(Low Pattern

Loading)

Selective(High Pattern

Loading)

Low-Temperature CVD Process

Cg: Bulk gas phase concentration of reactive intermediate

[eg., (NEt)HSi=O]

Cs: Concentration of the reactive intermediate at the interface

(Boundary Layer) (Boundary Layer)

OxideFilm

OxideFilm

Gas

δ

Cs

Cg

Gas

δ

Cs

Cg

0 20 40 60 80 100

Deposition Time (s)

700

600

500

400

300

200

100

0

Figure 7

12

10

8

6

4

2

0340 345 350 355 360

Temperature (C)

12

10

8

6

4

2

0

150 200 250 300 350

Spacing (mils)

12

10

8

6

4

2

0

400 600 800 1000 1200

Flow (mgm)

substrate.[5,6] One of the keys to pattern insensitivity

is eliminating mass transport as a limiting step in the

deposition mechanism.[7] For this to occur, precursor

concentration must be constant through the boundary

layer over the entire deposition surface (Figure 6).

This is achieved in two ways: 1) the oxidative ambient

is limited to reduce gas phase reaction and confine

the reaction closer to the substrate surface and 2) the

reaction times are kept short and cycled to minimize

any depletion that may occur during deposition. The

deposition rate limiting step then becomes the surface

reaction wherein the reactive intermediates are

incorporated into the bulk film.

Figure 7 shows that the deposition rate is insensitive to

temperature, precursor flow, and spacing, suggesting

that the process is indeed operating in a surface reaction

limited regime. This is achieved by depleting oxidative

ambients available for the CVD reaction. Supplying a

choked oxidative ambient flow substantially confines

the reaction closer to or on the patterned substrate

surface, thereby promoting uniform deposition thickness

regardless of the local exposed pattern area density.

Furthermore, the deposition thickness is limited,

terminating the CVD reaction before the silicon reactant

concentration in the boundary layer decreases.

This methodology of operating in a surface reaction

limited regime and cyclic deposition would work with

differing precursors, such as TEOS, which is commonly

used for CVD oxide depositions. However, to minimize

PLE, the new precursor was selected, because its small

siloxane intermediates are stable and inhibit further

polymerization. As these radical species are much

smaller (compared with TEOS), they have low sticking

coefficients, which results in a high net diffusion rate

through the boundary layer that promotes film growth

with minimal PLE.

CONCLUSIONA new ALD-like oxide liner with excellent electrical

film properties has been developed that achieves

maximum conformality and negligible PLE. The film can

be used for multiple thin oxide applications, such as STI

liners, gate and implant spacers, oxide hard masks, and

contact liners. Furthermore, a single CVD reactor can

be used to deposit film thicknesses ranging from 10Å

to 300Å at high productivity.

Figure 7. Deposition

rate independence from

temperature, spacing, and

precursor flow suggest that

the reaction is in a surface

reaction limited regime.


Figure 6. Incubation effects

on deposition mechanism.


REFERENCES[1] C. Ching, et al., “Improving Electrical Performance

Using SACVD Oxide Films,” Semiconductor

International, April 1, 2008.

[2] J.C. Rey, et al., “Monte Carlo Low Pressure

Deposition Profile Simulations,” Journal of Vacuum

Science and Technology, May 1991.

[3] A. Sanger, et al., “Chemical Vapor Deposition of

Tungsten Silicide (WSix) for High Aspect Ratio

Applications,” Thin Solid Films, October 2003.

[4] A. Yanguas-Gil, et al., “Highly Conformal Film

Growth by Chemical Vapor Deposition. I.

A Conformal Zone Diagram Based on Kinetics,”

Journal of Vacuum Science & Technology A, Vol. 27,

Issue 5, 2009.

[5] A.H. Labun, et al., “Mechanistic Feature-Scale

Profile Simulation of SiO2 Low-Pressure Chemical

Vapor Deposition by Tetraethoxysilane Pyrolysis,”

Journal of Vacuum Science & Technology B, Vol. 18,

Issue 1, 2000.

[6] M.K. Gobbert, et al., “Mesoscopic Scale Modeling of

Microloading During Low Pressure Chemical Vapor

Deposition,” Journal of the Electrochemical Society,

Vol. 142, Issue 8, 2003.

[7] J.W. Smith, et al.,“Pattern-Dependent Microloading

and Step Coverage of Silicon Nitride Thin Films

Deposited in a Single-Wafer Thermal Chemical

Vapor Deposition Chamber,” Journal of Vacuum

Science & Technology B, Vol. 23, Issue 6, 2005.

AUTHORSCary Ching is a product manager in the Dielectric and

Systems Modules business unit at Applied Materials.

He holds his M.S. in materials science from Rensselaer

Polytechnic Institute.

Sidharth Bhatia is a process engineer in the Dielectric

Systems and Modules business unit at Applied

Materials. He received his Ph.D. in materials science

from Brown University.

Paul Gee is a process engineering manager in the

Dielectric Systems and Modules business unit at

Applied Materials. He holds his Ph.D. in chemical

engineering from the University of California Los

Angeles.

Bingxi Wood is a senior technology program manager

in FEOL integration in the SSG CTO/MTCG group at

Applied Materials. She received her Ph.D. in physics

from Rensselaer Polytechnic Institute.

Ajay Bhatnagar is a director of Global Product

Management in the Dielectric and Systems Modules

business unit at Applied Materials. He holds his Ph.D.

in materials science and engineering from Stanford

University.


PROCESS SYSTEM USED IN STUDYApplied Producer® GT™



KEYWORDS

Interlayer Dielectrics

Nano-Porous Dielectrics

Ultraviolet

UV Curing

Ultra-Low-κ Dielectrics

Cross-Linking

Shrinkage

OPTIMIZING NANO-POROUS DIELECTRICSfor ≤28nm Applications

Nano-porous low-κ films are the standard interlayer

dielectrics at 45nm, but their relative fragility poses

challenges, such as susceptibility to downstream plasma

damage or physical damage during packaging. However,

new chemistries and improved ultraviolet curing have

enhanced these films’ mechanical strength and damage-

resistance through controlled polymerization and

physical restructuring, producing a new generation of

robust ultra-low-κ dielectrics that fulfill requirements

for 28nm and beyond.

As semiconductor devices continue to scale in

accordance with Moore’s Law, the ability to increase

signal speed is significantly affected by the dielectric

constant (κ) of the insulating materials sandwiched

between the copper interconnects. To achieve desired

electrical performance, the effective κ value (κeff

)

of the inter-level dielectric (ILD) combined with any

associated barrier films must scale correspondingly.

With packaging development and the move towards

lead-free solder, chip packaging interaction becomes

increasingly important to ensure high yields. The

dielectric constant reduction must not be at the expense

of film strength and compatibility with existing process

techniques.

Plasma enhanced chemical vapor deposition (PECVD)

carbon-doped oxides (CDO) were first introduced as

a means of reducing RC delay at the 90nm node. As

devices scaled below the 45nm node, the industry

transitioned from dense CDO (dielectric constant, or

κ of 3) to nano-porous CDO in which porosity was

introduced to lower the dielectric constant below 2.5.

Today, six years after the introduction of nano-porous

CDOs, the industry is seeking to extend nano-porous

CDOs to 28nm and below through innovation of the

dielectric film and subsequent UV cure process.

IMPROVING FILM STRENGTH AND REDUCING DIELECTRIC CONSTANTNano-porous low-κ films with a dielectric constant

of approximately 2.5 are the industry standard for

the 45/32nm node. These films are most effectively

fabricated using a two-step process. First, PECVD

is used to create a nano-composite composed of an

organo-silicate glass (OSG) backbone, simultaneously

deposited with a thermally labile organic (TLO) phase

that will partially define the final pore space. Second,

an advanced curing step, optimally an ultraviolet (UV)

cure, is applied to the film to remove the labile phase

and to restructure the remaining matrix to form the final

nano-porous film.[1] This porosity helps to reduce the

final dielectric constant of the film; however, it can also

make the film extremely susceptible to material damage

during subsequent wet and dry processing steps.


Robust Ultra-Low-κ Dielectrics

At 45/32nm, this challenge has been successfully

managed. Achieving ultra-low-κ (ULK) film (κ~2.2) for

scaling to 28nm and below, however, requires

re-engineering of the ILD’s composition and structure

to improve its ability to withstand subsequent

downstream plasma etch, photoresist ash, wet clean,

and chemical mechanical planarization (CMP), and

maintain required mechanical properties.

To determine the most effective chemistry for making

a robust nano-porous low-κ film, comparative studies

were conducted of various organosilane precursors

with different carbon-based backbone structures and

an organic precursor for the labile, pore-forming phase.

Among the organosilane precursors, the key differences

included the nature of the carbon bridge (seen to

largely determine resistance to integration damage)

and methyl content. Comparisons of commercially

available options showed that a new, proprietary

precursor needed to be developed as the methyl in the

existing chemicals tended to decrease the mechanical

strength contributed by the carbon.

Table 1

Dielectric Constant (κ)

2.2 2.4 2.55 2.6 2.8

Modulus (GPa) 7.1 10.7 8 11.3 14.2

Hardness (GPa) 1.0 1.54 1.25 1.8 2.27

XPS Carbon (%) 23 17.3 19 >19 >19

Having engineered a precursor with the appropriate

carbon content and structure provided the matrix

to control film properties and maintain chemical

resistance. As with the existing generation of 45nm

films, the key to achieving the desired mechanical

strength (elastic modulus, E, and hardness, H) and

dielectric constant was applying a UV cure to the

film. This process, in cooperation with the engineered

nano-porous film, promotes controlled cross-linking

of the dielectric backbone, creating a denser, stronger

material. It also drives out the labile species, thereby

lowering the κ value. The new chemistry enables a wide

range of dielectric constants while maintaining superior

film mechanical properties (Table 1).

Ultraviolet curing leverages both thermal and photon

energy in restructuring the film to generate porosity,

enhances backbone structure, and modifies film

composition to meet advanced logic requirements.

However, the curing of nano-porous CDOs introduced

new challenges requiring advances in curing process

and hardware design.

CREATING NANO-POROUS LOW-κ FILM BY UV CURINGCuring of the nano-composite starts with TLO removal

using UV photon wavelengths (200nm-300nm) to

break the carbon-hydrogen (C-H) and carbon-carbon

(C-C) bonds in the TLO. Figure 1a shows the C-H

intensity, measured using FTIR absorption spectroscopy,

as a function of UV curing time. The intensity is

expressed as a percentage of C-H peak area remaining

relative to that of an uncured sample. When exposed to

Figure 1. (a) FTIR C-H

intensity vs. UV curing time.

Plots A and B represent ULK

films cured under normal

and higher UV intensity,

respectively. Plot C

represents κ≤2.2 films with

increased TLO content cured

under higher UV intensity.

(b) Degree of cross-linking

vs. UV curing time for ULK

films.

Figure 1

0 200 400 600 800 1000

Time (s)

C-H

In

ten

sity

1.0

0.8

0.6

0.4

0.2

(a)

A

B

C

0 100 200 300 400 500 600

Time (s)

Si-O

-Si N

etw

ork

/Si-

O-S

i To

tal

0.46

0.45

0.44

0.43

0.42

0.41

0.40

(b)

Table 1. Key film properties

over wide range of dielectric

constants



UV light, a rapid decrease in C-H bonds occurs within

approximately 15 seconds and then gradually slows

down. The data set shows that TLO removal occurs

very rapidly and can be accelerated by strengthening

the UV intensity. This TLO removal behavior remains

unchanged even for ULK film with a dielectric constant

of 2.2 as well.

During the curing process, cross-linking of the Si-O-Si

network occurs in parallel with TLO removal. Figure 1b

shows the extent of cross-linking as a function of UV

cure time. As soon as ULK film is exposed to UV light,

the Si-O-Si network starts to increase linearly as curing

progresses. This indicates that the cross-linking and

TLO removal is happening simultaneously in the early

stage of the film re-structuring process, and then cross-

linking continues on after TLO removal is complete.

This behavior remains the same for all of the current

porous ULK films cured under UV treatment, which

suggests that it will also hold true for films with κ≤2.5

and next-generation ULK film with κ≤2.2.

Experiments were conducted to understand whether or

not ULK film property behavior varies with different UV

curing conditions. Film shrinkage is a control parameter

often used as a measure of the film state to target

desired dielectric constant, carbon content, and

mechanical strength. Figure 2a and b illustrate the

trends in dielectric constant, modulus, and carbon

content with respect to shrinkage of ULK film cured

under various wafer temperature and UV output power

conditions. While elastic modulus increases linearly as

film shrinkage progresses, dielectric constant drops and

plateaus at a certain shrinkage range before starting to

rise again as a result of greater loss in Si-CH3 bonds.

From Figure 2, multiple conclusions can be made. First,

Figure 2. (a) Dielectric

constant and modulus, and

(b) methyl content with

respect to film shrinkage of

ULK film cured under various

wafer temperatures and UV

output powers.

Figure 2

S0.3

S0.7

S1.0

S1.3

Normalized Film Shrinkage

Die

lect

ric

Co

nst

ant

(κ)

Mo

du

lus

(GPa

)

3.0

2.9

2.8

2.7

2.6

2.5

2.4

14

12

10

8

6

4

2

(a)

400°C, 75%

400°C, 90%

390°C, 90%

410°C, 90%

400°C, 75%

400°C, 90%

390°C, 90%

410°C, 90%

S0.3

S0.7

S1.0

S1.3


Met

hyl

Co

nte

nt

(%)

3.5

3.0

2.5

2.0

(b)

400°C, 75%

400°C, 90%

390°C, 90%

410°C, 90%

Figure 3

(a) (b)

t1.0

t1.4

t3.0

Normalized Cure Time

No

rmal

ized

Film

Sh

rin

kage

S1.3

S1.0

S0.7

S0.3

Bulb B/Bulb A

Bulb A

Bulb B

S0.3

S0.7

S1.0

S1.3


Die

lect

ric

Co

nst

ant

(κ)

Mo

du

lus

(GPa

)

3.0

2.9

2.8

2.7

2.6

2.5

2.4

14

12

10

8

6

4

2

Bulb A only

Bulb B/Bulb A

Bulb B only

Bulb A only

Bulb B/Bulb A

Bulb B only

Figure 3. (a) Effect of bulb

type on film shrinkage.

Bulb A and B are short

wavelength (200–300nm)

and long wavelength

(300nm–500nm) bulbs,

respectively.

(b) Dielectric constant,

modulus, and methyl

content with respect to film

shrinkage of ULK film cured

under various UV bulbs.



the curing behavior of ULK film remains consistent

regardless of UV curing conditions. In other words, at

the same film shrinkage, comparable film properties

can be achieved. Second, for every curing condition, an

optimal window of process conditions exists in which

elastic modulus increases while dielectric constant of

the ULK film remains constant.

SELECTING THE OPTIMAL UV WAVELENGTHEffective curing of nano-porous CDOs starts with

selection of the correct UV wavelength for efficient TLO

removal (C-H, C-C) and Si-O-Si network cross-linking.

The microwave lamp used as the UV source in this

study can easily shift the wavelength distribution by

the selection of the appropriate UV bulb. To identify the

optimal UV bulb, two types with different wavelengths

were used to cure nano-porous low κ film (κ≤2.5). In

addition, the effect of separating the TLO removal and

cross-linking steps was studied to understand whether

or not acceleration of the film restructuring process

could be achieved by first removing TLO with a long

wavelength UV bulb (300nm–500nm) followed by

cross-linking with a short wavelength UV bulb (200nm-

300nm). Heater temperature was adjusted to achieve

comparable wafer temperature between the two bulbs.

Figure 3 illustrates film shrinkage with respect to the

cure time for different approaches. The data indicate

that one-step curing with Bulb A was the most effective.

Two-step curing did not show acceleration of film

restructuring in this experiment. Figure 3b and Table 2

confirm that regardless of the curing approach, ULK

film curing behavior is universal and comparable film

properties are achievable for the same film shrinkage.

Thus, reaching the target film shrinkage as fast as

possible is the key factor for successful ULK curing.

CURING PROCESS EFFICIENCYAs noted earlier, the key function of the UV curing

process is to modify the molecular structure of the

as-deposited ULK film through UV photon energy.

Therefore, it is important to develop a curing process

that can accelerate this restructuring process and reach

the desired target as rapidly, uniformly, and consistently

as possible.

The kinetics of removing the TLO and cross-linking

can be enhanced without compromising the thermal

budget by increasing the UV intensity.[2] However, the

curing temperature plays a critical role in this process,

as illustrated in Figure 4. ULK film was cured at

various wafer temperatures for different cure times

using broadband UV. The UV cure time series data

demonstrate a linear relationship between film

shrinkage and cure time with the trendline shifting

to the left as wafer temperature increases, indicating

higher curing efficiency. However, BEOL thermal budget

limitation requires wafer temperature to be ~400°C.

Table 2

Parameter Bulb A Only Bulb B Only Bulb B/Bulb A (2-Step)

Normalized Cure Time 1.0 3.0x 1.4x

Refractive Index 1.349 1.347 1.350

Normalized Film Shrinkage 1.0 0.96 1.02

Dielectric Constant (5pts avg) 2.48 2.48 2.48

Hardness/Modulus (GPa) 1.28/8.3 1.27/8.2 1.32/8.6

Porosity (%) 23.9 24.9 23.2

Pore Radius (Å) 11.6 11.5 11.3

SiCH3/SiO (area %) 2.8 2.8 2.8

Table 2. Post-cured

properties of ULK film with

similar shrinkage cured

under various UV bulbs


Figure 4

t0.3

t0.7

t1.0


Film

Sh

rin

kage

(%

)

18.0

17.0

16.0

15.0

14.0

13.0

12.0

11.0

405°C

420°C

435°C

445°C

Wafer Temperature

Figure 5

(a)

(b)

(c)

t1.0

t1.4


No

rmal

ized

Film

Sh

rin

kage

S1.1

S1.0

S0.8

Target

S0.8

S1.0

S1.1


Die

lect

ric

Co

nst

ant

2.54

2.52

2.50

2.48

2.46

S0.8

S1.0

S1.1


Mo

du

lus

(GPa

)

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

Low Pressure

High Pressure

Low Pressure

High Pressure

Low Pressure

High Pressure

Cure pressure is another process variable that

accelerates film restructuring. Figure 5 shows the

relationship of pressure to film shrinkage at constant

wafer temperature. To understand the effect of pressure

on the restructuring process, ULK film was cured at low

and high pressures and for various lengths of time.

Figure 5a shows that lower cure pressure achieves the

target film shrinkage approximately 40% faster than

high cure pressure. Figures 5b and 5c show that for the

same film shrinkage, low pressure performance is supe-

rior to high pressure cure, suggesting that the former

accelerates restructuring of the as-deposited ULK film.

One of the major challenges in curing TLO-containing

ULK film is managing the outgassed TLO by-products.

As shown earlier, TLOs are removed very quickly.

These organic by-products can unfortunately be easily

re-deposited onto cold (<200°C) surfaces, such as the

UV window and chamber body, leading to inconsistent

and non-uniform curing that, in turn, compromises

film properties and can have negative impact on film

defectivity levels. Consequently, maintaining a clean

environment is imperative.

UV CHAMBER CLEANINGIn-situ cleaning is essential for delivering fast, uniform,

and consistent film restructuring by curing. Because the

outgassed by-products are organic, an oxygen-based

clean was expected to be best for removing them,

producing mainly CO2 and H

2 by-products that do not

re-deposit on chamber surfaces. Two oxygen-based

cleaning processes were evaluated: one ozone-based

and the other remote plasma source-based. Both are

known to create active oxygen radicals. The clean etch

rate of the two approaches was compared using blanket

photoresist and constant wafer temperature to elimi-

nate the thermal effect. The data show an etch rate ap-

proximately 20% higher for the ozone-based cleaning,

suggesting greater oxygen radical availability. An addi-

tional benefit of the ozone clean is that the dissociation

process starts only when the gases are introduced into

the chamber and are exposed to UV lights (200nm–

300nm) and hot (>200°C) surfaces, creating the

chemically active oxygen radicals precisely where they

are needed for effective and efficient cleaning.


Figure 5. (a) Effect of curing

pressure on film shrinkage.

(b) Dielectric constant vs.

film shrinkage.

(c) Modulus vs. film

shrinkage.

Figure 4. Relationship

of wafer temperature to

film shrinkage and curing

efficiency.


OPTIMIZING CURING PROCESS UNIFORMITYPurge flow is another critical parameter governing

consistent and uniform cure within the wafer and from

wafer to wafer. The purge flow prevents outgassed

by-products from reaching the UV window so that

uniform and consistent UV light reaches the wafer.

Computational fluid dynamics (CFD) modeling was

used to compare concentrations of outgassing species

for side-to-side purge flow and uniform purge flow from

an overhead source. Simulation data indicated that

uniform purge flow was superior in keeping the window

continuously clean (Figure 6a). Previous study has

shown that the uniformity of the film shrinkage is highly

dependent on the uniformity of wafer temperature.

Side-to-side purge flow creates a temperature gradient

on the wafer that can be correlated to the shrinkage

profile. Uniform purge flow can reduce wafer

temperature non-uniformity to <5°C.

Figure 6b shows the change in the film shrinkage maps

of post-cured TLO-containing ULK (κ≤2.5) film using

conventional UV hardware and optimized UV hardware.

Shrinkage uniformity can be further enhanced through

uniform purge flow and improved window engineering

compared to conventional side-to-side purge flow and

window configuration.

Delivering uniform incident UV light to the wafer is

essential for uniform film curing. UV source rotation is

one method of achieving this while maximizing source

efficiency. Similar to the microwave oven, rotation of

the UV source delivers uniform light across the wafer

without leaving “hot spots” behind as occurs when the

UV source is fixed. Although the issue can be resolved

by increasing the distance between the wafer and the

UV bulb, this approach reduces source efficiency and

leads to a drop in cure rate. The UV window itself can

also improve UV light distribution uniformity. Figure 7

compares film shrinkage profiles across the wafer for

conventional and engineered windows. The profile for

the conventional window shows more shrinkage at the

center than at the edge, corresponding to the loss of

light at the rim of the window. The new window design

minimizes the reflection loss at the window surfaces,

allowing more UV light to illuminate the edge of wafer

and thereby optimizing UV light distribution. Shrinkage

uniformity maps in Figure 6b demonstrate the effect

on curing uniformity of the re-engineered lighting and

purge flow hardware.

IMPROVING CDO ADHESION TO THE BARRIER DIELECTRICThe low-κ dielectric must be mechanically strong to

resist stresses applied to the chip during packaging.

Packaging failures commonly occur at the barrier/low-κ

interface due to mismatch between the barrier film

and bulk dielectric. To enhance adhesion, a transition

layer is deposited between the barrier and bulk low-κ.

Although this layer greatly improves adhesion, its

higher dielectric properties raise the κeff

. However, the

chemistry used results in the initiation and transition

layer of the film being significantly thinner than was

true of previous-generation chemistries. The SIMS

profile in Figure 8 shows that the transition from low

carbon at the barrier interface to the bulk carbon in

the film occurs in 75Å. This thinner adhesion layer

improves overall κeff

of the film without loss of

mechanical integrity.


Figure 6

Outgassing Species Concentration

at Window

Uniform Purge Flow

Side-to-SidePurge Flow

(a) (b)

Parameter

Shrinkage Map

Film Shrinkage (%)

Shrinkage Uniformity (%, 1s)

Shrinkage Range (%) (Max-Min)

E&H Uniformity (GPa) (Max-Min)

Conventional UV Hardware

15.3

3.0

1.8

0.8/0.1

Optimized UV Hardware

15.0

1.6

1.0

0.3/0.04

Figure 6. (a) CFD modeling

showed uniform purge flow

to be more effective in

maintaining a constantly

clean UV window.

(b) On-wafer results also

demonstrated better

shrinkage uniformity.


Figure 7

-150 -100 -50 0 50 100 150

Wafer Position (nm)

No

rmal

ized

Sh

rin

kage

1.2

1.1

1.0

0.9

0.8

Conventional

Engineered

Figure 8

0 100 200 300 400 500 600 700

Depth (Å)

Car

bo

n C

on

cen

trat

ion

(ato

m%

)

20

16

12

8

4

0

New Chemistry

Previous Chemistry

340Å

75Å

Figure 9

0.2μm

CONCLUSIONDeveloping dielectric TLO-containing ULK dielectric

films for successful integration at advanced logic

nodes poses many challenges in identifying the optimal

CDO chemistry, enhancing the curing process, and

optimizing integrated process steps to maintain

adhesion and lower κeff

. Designing a UV cure solution

for robust film restructuring not only extends the use of

nano-porous ULK film to the next generation but also

extends curing to other applications, such as tensile

stress nitride for device performance improvement and

κ-recovery of integration-damaged nano-porous ULK

films. Process and hardware advances in dielectric

deposition, UV curing, and interface engineering have

created a film ready for sub-20nm integration (Figure 9).

ACKNOWLEDGMENTSThe authors would like to thank K. Chan, M. Chhabra,

B. Xie, S. Hendrickson, A. Kangude, M. Martinelli,

D. Raj, R. Odom and D. Witty for their support and

comments.

REFERENCES[1] Kelvin Chan, et al., “Structural Evolution of Nano-

Porous Ultra-Low-κ Dielectrics under Broadband UV

Curing,” Advanced Metallization Conference 2007,

Proceedings, October 9-11, 2007, Tokyo, Japan;

October 22-24, 2007, New York, NY, pp. 507-511,

2008.

[2] Alex Demos, et al., “Porous Low-κ Dielectrics

Using Ultraviolet Curing,” Solid State Technology,

September, 2005.

AUTHORSHarry Whitesell is a global product manager in the


Applied Materials. He holds his Ph.D. in materials

engineering from Auburn University.

Tsutomu Kiyohara is a global product manager in

the Dielectric Systems and Modules business unit at

Applied Materials. He received his B.S. in industrial

engineering from the University of Toronto.

Kang Sub Yim is a senior member of technical staff

in the Dielectric Systems and Modules business unit

at Applied Materials. He holds his Ph.D. in chemical

engineering from Stanford University.


Figure 9. 2LM test

structure fabricated with

TLO-containing ULK

dielectric and advanced

UV curing (courtesy MTCG).

Figure 8. Carbon profile

demonstrates the reduction

of adhesion layer thickness.

Figure 7. Greater illumination

around the edges of the

new window results in more

uniform center-to-edge film

shrinkage.


Thomas Nowak is a distinguished member of technical

staff in the Dielectric Systems and Modules business

unit at Applied Materials. He received his Ph.D. in

mechanical engineering from the Massachusetts


Alex Demos is a director in the Dielectric Systems and

Modules business unit at Applied Materials. He holds

his Ph.D. in chemical engineering from the University of

Michigan.

Juan Carlos Rocha is an engineering director in the


Applied Materials. He received his Engineer’s Degree

in Mechanical Engineering from the Massachusetts


Sanjeev Baluja is a senior engineering manager in

the Dielectric Systems and Modules business unit at

Applied Materials. He holds his Master’s of Engineering

in Manufacturing from the University of Michigan.


[email protected]

PROCESS SYSTEMS USED IN STUDYApplied Producer® PECVD Black Diamond® 3

Applied Producer® PECVD with Nanocure™ 3



OPTIMIZING DIELECTRIC ETCH UNIFORMITYfor 28nm Copper Dual Damascene

Feature dimensions at the 2x node are making it increasingly

challenging to achieve the center-to-edge etch depth

uniformity and CD control necessary for uniform resistance

of copper interconnect lines. In combination with optimized

chemistry, varying the inter-electrode gap of a plasma

reactor is an effective method by which to tune these

aspects of etch performance. Experiments show that using

this mechanism for individual steps achieves superior yield

from a multi-step process.

Etch reactors are equipped with a number of tuning

parameters, including power levels, process chemistry,

gas flow distribution, chamber pressure, and wafer

temperature gradient to meet requirements for etch

rate, selectivity, and critical dimension (CD) control.

However, as process requirements tighten, it becomes

difficult to optimize the process for one performance

requirement without affecting other aspects of perfor-

mance. Varying the gap between the electrodes provides

a significant and independent means of tuning process

performance, particularly center-to-edge uniformity. We

present results from an investigation of dual damascene

(DD) etch uniformity using a reactor with a moving

cathode to optimize the inter-electrode gap.

MODELING STUDYDelivering uniform process results across the wafer

typically requires optimizing the spatial distribution

of plasma-generated species (ions, electrons) in the

reactor. One factor that significantly influences plasma

spatial distribution is the inter-electrode gap. To under-

stand the effect of this gap on the behavior of capacitive

coupled plasmas, we developed a two-dimensional

model of an argon plasma operating at 13.5MHz.

The reactor has a top electrode separated from the

grounded chamber wall by a quartz ring. The bottom

electrode is surrounded by a set of silicon and quartz

rings. A silicon wafer is placed at the bottom electrode;

argon gas flows into the plasma process chamber

through the top electrode and is removed through the

pump port at the bottom of the chamber. The plasma

simulations were performed at 1000W with the RF

source connected to the bottom electrode. Gas pressure

was 100mTorr and the inter-electrode gap was varied

between 1.25in. and 3.0in. Secondary electron emission

was not included in these simulations. Peak electron

density is close to the edge of the bottom electrode for

an inter-electrode gap of 1.25in. (Figure 1).[1]

Plasma sheath thickness scales with electron density;

at the minimum gap, the sheath is thicker near the

center of the chamber where electron density is lower.

As the inter-electrode gap is increased, the peak

plasma density initially increases, then saturates and

starts decreasing (Figure 1). Although not shown here,

the peak electron density further decreases if the inter-

electrode gap exceeds 3.0in.

These changes in electron density magnitude can be

understood in terms of the surface area to volume ratio,

A/V, of the effective plasma region, which decreases

KEYWORDS

Dual Damascene

Dielectric Etch

Inter-Electrode Gap

Center-to-Edge Uniformity


Inter-Electrode Gap Tuning

as the inter-electrode gap increases. Electrons are lost

primarily at the reactor surfaces in an argon discharge.

Therefore, as the relative surface area A/V is larger

at smaller gaps, electron density is lowest when the

inter-electrode gap is 1.25in. As the gap increases

beyond a certain limit, the same RF power is deposited

over a larger volume. The peak plasma density therefore

saturates and then decreases. The spatial structure

of the plasma changes appreciably with the inter-

electrode gap.

Electric field enhancement causes electron power

deposition to be stronger near the edge of the electrode

(Figure 1). Plasma is therefore produced more strongly

near the electrode edge. At large inter-electrode gaps,

plasma can diffuse relatively easily and fills the inter-

electrode region better. The axial location of the peak

in plasma density shifts toward the powered electrode

when the inter-electrode gap increases. When the gap

is narrow, the lower electron density results in a thicker

cathode sheath, notably above the lower electrode, as

the RF potential drop across the sheath is larger in this

asymmetric plasma reactor. The peak electron density

therefore appears off axis, closer to the top electrode.

As the inter-electrode gap increases, the peak electron

density gradually moves closer to the lower electrode

as more electron power is being deposited adjacent to it.

The effect of the inter-electrode gap on plasma spatial

structure is also reflected in the ion flux to the wafer

(Figure 2). As electron density is higher near the edge

of the lower electrode, argon ion flux to the wafer peaks

near the electrode edge at the narrow gap of 1.25in.

The plasma diffuses to the chamber center as the inter-

electrode gap is increased. This, in turn, raises plasma

density and argon ion flux near the wafer center.

The etch rate is typically dependent on the flux of ions

and reactive species to the wafer. If the etch process

at the center of the reactor is limited by the availability

of reactive species, widening the inter-electrode gap

facilitates diffusion of the reactive species from the

edge region, providing a more uniform etch result.

Controlling the flux distribution by varying the inter-

electrode gap offers a mechanism for optimizing the

etch across the wafer. The CD of the etch feature, which

is dependent on the anisotropy of the etch and mask

erosion, can be similarly optimized.

Figure 2

0 0.05 0.10 0.15

Radius (m)

1.2x1020

8.0x1019

4.0x1019

0

Ar+

Flu

x (m

-2s-1

)

1.25”

1.5”

2.0”

2.5”

3.0”

(a) (b)

(a)

(c)

(b)

1.25” Gap Max: 377.8kW/m3

2.5” Max: 240.0kW/m3

3.0” Max: 239.3kW/m3

Min Max

(a)

(c)

(b)

Min = Max/10 Max

Gap

Cha

mbe

r W

all

Quartz

QuartzSi

3.0” Max: 6.07 x 10 16m-3

Bottom Electrode

Top Electrode

Wafer

Pump Port

2.5”

1.25” Gap

8.2”

6.0”

Max: 6.17 x 1016m-3

Max: 3.54 x 1016m-3

Figure 1

Figure 1. (a) Electron density and

(b) power distribution for

different inter-electrode gaps

at 1000W, 100mTorr, and

13.5MHz. Model results (top

to bottom) from 1.25in., 2.5in.,

and 3.0in. gap.

Figure 2. Argon ion flux to

the wafer for different inter-

electrode gaps at 1000W,

100mTorr, and 13.5MHz.


ON-WAFER RESULTSThe effect of electrode gap variation on etch perfor-

mance was investigated experimentally for copper back-

end-of-line DD etches using porous low-κ dielectric with

a TiN hard mask, representative of the film stacks being

adopted by the industry for nominal 28nm design rules.

The inter-electrode gap shows a significant effect on CD

uniformity for the via etch process. During the via mask

open step, the CD pattern shifts from center-small/edge-

large to center-large/edge-small as the gap increases

from 1.25in. to 3.5in., with optimum uniformity occurring

at gaps between 1.6in. and 2.5in. (Figure 3). Via depth

uniformity also varies with the gap and was similar to

the via CD results, the optimum center-edge uniformity

occurring when the gap ranged between 1.5in. and 2.0in.

For the subsequent trench etch, the inter-electrode gap

was found to be a powerful means of optimizing center-

to-edge trench depth uniformity. However, unlike the

via process, center-to-edge trench CD uniformity was

not affected by the gap, likely because of the difference

in plasma conditions (power, gas flows) for the two

processes (Figure 4).

The optimum gap varies with other parameters of

the etch process, such as the process chemistry. Figure

5 shows electrical resistance of copper-filled DD test

structures with optimization of process chemistry and

gap to improve uniformity of the electrical results.

Achieving uniform resistance of the copper lines

requires optimizing both CD and trench depth

uniformity. Moving from a C4F

6-based chemistry to

a leaner C4F

8-based chemistry and reducing the gap

from 3.5in. to 1.8in. resulted in a 55% reduction in

non-uniformity.

For reactors in which one of the electrodes can be

moved under recipe control, the inter-electrode gap

can be used as a process tuning parameter to optimize

uniformity for individual steps of a multi-step recipe

(Figure 6). In this example, the electrode gap was

adjusted by moving the cathode to the appropriate

position for individual steps of the DD process, resulting

in CD uniformity of 1.4nm 3σ. After filling with copper,

these structures yielded at 100% with a uniform line

resistance distribution (2.3% 1σ).

Figure 4. Effect of inter-

electrode gap on trench etch

depth and CD uniformities.

Figure 5. Line resistance (R)

for 4.5m long 45/45nm line/

space copper lines.

Figure 3. Via CD bias vs.

gap for via mask open etch

(a) 1.25in., (b) 1.6in.,

(c) 2.5in., and (d) 3.5in.

Figure 3

-20.4

-22.2

-24.1

-25.9

-27.7

-29.6

-31.4

-33.3

-35.1

-20.6

-21.9

-23.2

-24.5

-25.8

-27.1

-28.4

-29.7

-31.0

-28.1

-29.2

-30.2

-31.3

-32.4

-33.4

-34.5

-35.5

-36.6

-23.3

-24.6

-25.9

-27.2

-28.5

-29.9

-31.2

-32.5

-33.8

Mean : -26.3nm3-Sigma : 10.2nmRange : 14.7nm

(a)


(b)


(c)


(d)

Figure 4 Figure 5

1.60 1.75 2.00

Inter-Electrode Gap (in.)

16

14

12

10

8

6

4

2

0

No

n-U

nif

orm

ity

(nm

)

Trench Depth Non-Uniformity

Trench CD Non-Uniformity

1E+07 1E+08

Line Resistance (Ohms)

�

��

�

LSL Target USL

1.8” Gap/C

4F

8 Chemistry

+, x 3.5” Gap/C

4F

6 Chemistry

*, �

99.9

99

959080

60

40

20

1052

.5

.1

Perc

ent



Figure 6

10 100 1000 10000

Measurement

99.9

99

959080

60

40

20

1052

.5

.1

Perc

ent

(b)

(a)

PRARCHM

SOHTiNHM

ULK

BarrierM1

Via HardMask Etch

OrganicMask Etch

Via Etch Via Ash/Organic

Mask Strip

TrenchEtch

Barrier Open/

Post EtchTreatment

4

3

2

1

0

Gap

(in

.)

CONCLUSIONExperimental studies have demonstrated the

effectiveness of using the inter-electrode gap of a

plasma reactor to tune center-to-edge etch performance,

such as CD uniformity or etch depth uniformity.

Widening the gap caused etch rate to transition from

edge high to center high; the CD pattern shifted from

center-small/edge-large to center-large/edge-small as

the gap increased. These results were consistent with

an argon plasma model that showed an increase in ion

flux near the center of the wafer and a decrease at the

edge as the distance between the electrodes widened.

REFERENCES

[1] K. Bera, et al., “Effects of Inter-Electrode Gap

on High Frequency and Very High Frequency

Capacitively Coupled Plasmas,” J. Vac. Sci. Technol.

A 27 (4), pp. 706-711, Jul/Aug 2009.

ACKNOWLEDGEMENTSThe authors would like to acknowledge the support

of Nikos Bekiaris and the Applied Materials Maydan

Technology Center for processing the electrical test

wafers. Shahid Rauf, Peter Hsieh, Kathryn Keswick,

and Bryan Pu of the Etch Products business unit also

contributed to this work.

AUTHORSAmulya Athayde is the global product manager for

Dielectric Etch at Applied Materials. He holds his Ph.D.

in chemical engineering from the University of Notre

Dame.

Chia-Ling Kao is a senior process engineer in the

Dielectric Etch Application Technology Development

group at Applied Materials. He received his Ph.D. in

chemical engineering from Stanford University.

Kallol Bera is a senior member of technical staff in the

Dielectric Etch Disruptive Technology and Engineering

group at Applied Materials. He holds his Ph.D. in

mechanical engineering from Drexel University.

Sean Kang is a senior member of technical staff in the

Dielectric Etch Application Technology Development

group at Applied Materials. He received his M.S. in

chemical engineering from the University of Southern

California.


PROCESS SYSTEM USED IN STUDYApplied Producer® Etch

Figure 6. (a) DD etch process

with gap optimized by

process step.

(b) Distribution of electrical

line resistance for 120 micron

75/75nm comb-serpentine

test structures.


volume 9, issue 2, 2011

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