EXPERIMENT 03

AIM: To study the Transient Analysis of CMOS Transistor using Tanner Tool

Given Parameters:

For NMOS:

Level=1, Threshold Voltage (vto) =0.7, Transconductance parameter Kp =5*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.01/Volt

For PMOS:

Level=1, Threshold Voltage (vto) =-1, Transconductance parameter Kp =16*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.02/Volt

Operation of CMOS (Complimentary metal Oxide Semiconductor) Transistor:

The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal--oxide--semiconductor field-effect transistors to create paths to the output from either the voltage source or ground

When a path to output is created from the voltage source, the circuit is said to be pulled up.

The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential.

Output is inversion of the input :

The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied

The composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied

Both NMOS and PMOS transistors have a gate—source threshold voltage, below which the current (called sub-threshold current) through the device drops exponentially. CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5V, and Vth for both NMOS and PMOS might have been 700mV).

Two important characteristics of CMOS devices are

1. High immunity 2. Low static power consumption. Significant power is only drawn while the

transistors in the CMOS device are switching between on and off stataes.

Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices.

CMOS also allows a high density of logic functions on a chip. It was primarily this reason why CMOS won the race in the eighties and became the most used technology to be implemented in VLSI designs.

Steps to be followed to generate CMOS Output Waveform

1. Schematic Diagram

2. T-Spice file

3. T-spice file (Simulation Status)

4. Output Waveform

RESULT

When the voltage of input (vin) is high, the PMOS transistor is in an off (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in on (low resistance) state, allowing the output to drain to ground.

Because the resistance between vout and ground is low, the voltage drop due to current drawn into vout, placing vout above ground s small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this opposite behaviour of input and output, the CMOS circuits’ output is the inversion of the input.

EXPERIMENT 04

AIM: To study the DC Analysis of CMOS Transistor using Tanner Tool

Given Parameters:

For NMOS:

Level=1, Threshold Voltage (vto) =0.7, Transconductance parameter Kp =5*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.01/Volt

For PMOS:

Level=1, Threshold Voltage (vto) =-1, Transconductance parameter Kp =16*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.02/Volt

Operation of CMOS (Complementary metal Oxide Semiconductor) Transistor:

The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal--oxide--semiconductor field-effect transistors to create paths to the output from either the voltage source or ground

When a path to output is created from the voltage source, the circuit is said to be pulled up.

The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential.

Both NMOS and PMOS transistors have a gate—source threshold voltage, below which the current (called sub-threshold current) through the device drops exponentially. CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5V, and Vth for both NMOS and PMOS might have been 700mV).

Two important characteristics of CMOS devices are

1. High immunity

2. Low static power consumption.

DC ANALYSIS  

The DC analysis is helpful in determining the required power supply and its limits, the current consumption and to be sure that all the devices in the circuit are working in the safe region without exceeding their normal rating.

From the dc analysis, we can determine the node voltage, mesh current and branch voltage and branch current of a network.

The MOSFETS must be perfectly matched for optimum operation, that is, they must have the same threshold voltage magnitude and conduction parameter. 

The drain current (ID) through the NMOS device equals the drain current through the PMOS device at all times.  MOSFET gates have a high input impedance and we assume the circuit’s output sees no significant loading.

VDD equals the voltage across the PMOS plus the voltage across the NMOS by KVL. 

 

The DC operating point (also known as bias point, quiescent point, or Q-point) is the DC steady-state operating condition of a transistor, (with no AC input signal applied), determined by current and voltage of the input port and the output port.

Steps to be followed to generate CMOS Output Waveform

1. Schematic Diagram

2. T-Spice file

3. T-spice file (Simulation Status)

4. Output Waveform

RESULT

When Vin lies between 0 and Vtn i.e. threshold voltage of NMOS transistor the NMOS is cutoff and operation of PMOS is linear and resulting output voltage is equal to VDD.

When the input voltage is increased beyond Vtn. The NMOS transistor starts conducting in saturation mode and output voltage begins to decrease.

When the input voltage is equal to VDD/2. Both NMOS and PMOS transistors enter into saturation mode and output voltage drops sharply.

When Vin lies between VDD/2 and VDD - |Vtp |. The NMOS transistor starts to operate in linear mode.

When the input voltage is greater than VDD - |Vtp|. The PMOS transistor is cutoff and output voltage is equal to 0.

EXPERIMENT 05

AIM: To design a schematic and simulate a 2-input CMOS NAND gate with power supply voltage=5V using Tanner Tool

Given Parameters:

For NMOS:

Level=1, Threshold Voltage (vto) =0.7, Transconductance parameter Kp =5*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.01/Volt

For PMOS:

Level=1, Threshold Voltage (vto) =-1, Transconductance parameter Kp =16*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.02/Volt

Operation of CMOS gate Transistor:

The 2-input NAND gate is the simplest CMOS gate to illustrate the name complementary MOS :

The P-type transistors are connected in parallel between VDD and the output vout .

The N-type transistors are connected in series between GND and the output vout .

That is, the N-type and the P-type parts of the CMOS gate are complementary.

Working:

In this circuit, if both inputs are high, both P-channel MOSFETs will be turned off, thus providing a connection to +V. Both N-channel MOSFETs will be on, so there will be no ground connection. Output will be pulled low.

If either input goes low, that P-channel MOSFET will turn on and disconnect the output from +V, while that N-channel MOSFET will turn off, thus grounding the output. Output will be pulled high.

Circuit diagram of CMOS NAND

TRUTH TABLE OF “CMOS NAND” GATE

Input VA Input VB Output Vout

0 0 1

0 1 1

1 0 1

1 1 0

Steps to be followed to generate CMOS NAND Gate Output Waveform

1. Schematic Diagram

2. T-Spice File

3. T-Spice (Simulation File)

4. Output Waveform

RESULT

The above waveforms for inputs VA and VB along with the output waveforms satisfies the truth table of CMOS NAND gate as given above in the operation section of the experiment.

Thus,

If both inputs VA and VB are ‘1’, there is a conducting path from output to the GND (output level’0’).

An input combination with VA and VB ‘0’ provides the conducting path from VDD to the output, but closes a path from GND to the output (so that the output level is ‘1’).

EXPERIMENT 06

AIM: To design a schematic and simulate a 2-input CMOS NOR gate with power supply voltage=5V using Tanner Tool

Given Parameters:

For NMOS:

Level=1, Threshold Voltage (vto) =0.7, Transconductance parameter Kp =5*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.01/Volt

For PMOS:

Level=1, Threshold Voltage (vto) =-1, Transconductance parameter Kp =16*10-6Amp/V2 , Channel length modulation parameter lambda(λ) =0.02/Volt

Operation of CMOS gate Transistor:

The 2-input NOR gate is the simplest CMOS gate to illustrate the name complementary MOS :

The P-type transistors are connected in series between VDD and the output vout

. The N-type transistors are connected in parallel between GND and the

output vout .

That is, the N-type and the P-type parts of the CMOS gate are complementary.

Working:

In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be off, so there will be no ground connection.

If either input goes high, that P-channel MOSFET will turn off and disconnect the output from +V, while that N-channel MOSFET will turn on, thus grounding the output.

Only if both inputs VA and VB are ‘0’ (corresponding to GND), there is a conducting path from VDD to the output (output level ‘1’).An input combination with A and B ‘1’ blocks the path from VDD to the output, but opens a path from GND to the output (so that the output level is ‘1’)

TRUTH TABLE OF “CMOS NOR” GATE

Input VA Input VB Output Vout

0 0 1

0 1 0

1 0 0

1 1 0

Steps to be followed to generate CMOS NOR Gate Output Waveform

1. Schematic Diagram

2. T-spice File

3. T-Spice File(Simulation File)

4. Output Waveform

RESULT

The above waveforms for inputs VA and VB along with the output waveforms satisfies the truth table of CMOS NOR gate as given above in the operation section of the experiment.

Thus,

If both inputs VA and VB are ‘0’, there is a conducting path from VDD to the output (output level ‘1’).

An input with VA and VB ‘1’ blocks the path from VDD to the output, but opens a path from GND to the output (so that the output level is ‘0’).