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Slides adapted from:

N. Weste, D. Harris, CMOS VLSI Design, © Addison-Wesley, 3/e, 2004

MOS Transistor Theory

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Outline

The Big PictureMOS StructureIdeal I-V CharcteristicsMOS Capacitance ModelsNon ideal I-V EffectsPass transistor circuitsTristate InverterSwitch level RC Delay Models

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The Big Picture

So far, we have treated transistors as ideal switchesAn ON transistor passes a finite amount of current

Depends on terminal voltagesDerive current-voltage (I-V) relationships

Transistor gate, source, drain all have capacitanceI = C (∆V/∆t) ∆t = (C/I) ∆VCapacitance and current determine speed

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MOS Transistor Symbol

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MOS Structure

Gate and body form MOS capacitorOperating modes

AccumulationDepletionInversion

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nMOS Transistor Terminal VoltagesMode of operation depends on Vg, Vd, Vs

Vgs = Vg – Vs

Vgd = Vg – Vd

Vds = Vd – Vs = Vgs - Vgd

Source and drain are symmetric diffusion terminalsBy convention, source is terminal at lower voltageHence Vds ≥ 0

nMOS body is grounded. First assume source is 0 too.Three regions of operation

CutoffLinearSaturation

Vg

Vs Vd

VgdVgs

Vds+-

+

-

+

-

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nMOS in cutoff operation mode

No channelIds = 0

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nMOS in linear operation mode

Channel formsCurrent flows from D to S

e- from S to DIds increases with Vds

Similar to linear resistor

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nMOS in Saturation operation mode

Channel pinches offIds independent of Vds

We say current saturatesSimilar to current source

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pMOS Transistor

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I-V Characteristics (nMOS)In Linear region, Ids depends on

How much charge is in the channel?How fast is the charge moving?

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Channel Charge

MOS structure looks like parallel plate capacitor while operating in inversion:

Gate – oxide – channelQchannel = CVC = Cg = εoxWL/tox = coxWLV = Vgc – Vt = (Vgs – Vds/2) – Vt

cox = εox / tox

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Carrier velocity

Charge is carried by e-Carrier velocity v proportional to lateral E-field between source and drainv = µE µ called mobilityE = Vds/LTime for carrier to cross channel:

t = L / v

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nMOS Linear I-VNow we know

How much charge Qchannel is in the channelHow much time t each carrier takes to cross

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QItW VC V V VL

VV V V

µ

β

=

= − −

= − −

ox = WCL

β µ

=

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nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drainWhen Vds > Vdsat = Vgs – Vt

Now drain voltage no longer increases current

( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

β

β

= − −

= −

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nMOS I-V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VVI V V V V V

V V V V

β

β

< = − − <

− >

first order transistor models

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I-V characteristics of nMOS Transistor

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Example

0.6 µm process from AMI Semiconductortox = 100 Åm = 350 cm2/V*sVt = 0.7 V

Plot Ids vs. VdsVgs = 0, 1, 2, 3, 4, 5Use W/L = 4/2 λ

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3.9 8.85 10350 120 /100 10ox

W W WC A VL L L

β µ µ−

−

• ⋅ = = = ⋅

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

I ds (m

A)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2Vgs = 1

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pMOS I-V Characteritics

All dopings and voltages are inverted for pMOSMobility µp is determined by holes

Typically 2-3x lower than that of electrons µn

120 cm2/V*s in AMI 0.6 mm processThus pMOS must be wider to provide same current

In this class, assume µn / µp = 2

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pMOS I-V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VVI V V V V V

V V V V

β

β

< = − − <

− >

first order transistor models

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I-V characteristics of pMOS Transistor

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Capacitances of a MOS Transistor

Any two conductors separated by an insulator have capacitanceGate to channel capacitor is very important

Creates channel charge necessary for operation (intrinsic capacitance)

Source and drain have capacitance to body (parasitic capacitance)

Across reverse-biased diodesCalled diffusion capacitance because it is associated with source/drain diffusion

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Gate Capacitance

When the transistor is off, the channel is not invertedCg = Cgb = εoxWL/tox = CoxWLLet’s call CoxWL = C0

When the transistor is on, the channel extends from the source to the drain (if the transistor is unsaturated, or to the pinchoff point otherwise)Cg = Cgb + Cgs + Cgd

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Gate Capacitance

In reality the gate overlaps source and drain. Thus, the gate capacitance should include not only the intrinsic capacitance but also parasitic overlap capacitances:Cgs(overlap) = Cox W LDCgs(overlap) = Cox W LD

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Detailed Gate Capacitance

2/3 C0+ CoxWLDC0/2 + CoxWLDCoxWLDCgs (total)CoxWLDC0/2 + CoxWLDCoxWLDCgd (total)00C0Cgb (total)SaturationLinearCutoffCapacitance

Source: M-S Kang, Y. Leblebici,CMOS Digital ICs, 3/e,2003, McGraw-Hill

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Diffusion CapacitanceCsb, CdbUndesired capacitance (parasitic) Due to the reverse biased p-njunctions between source diffusion and body and drain diffusion and bodyCapacitance depends on area and perimeter

Use small diffusion nodesComparable to Cg for contacted diffusion½ Cg for uncontactedVaries with process

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Lumped representation of the MOSFET capacitances

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Non-ideal I-V effects

The saturation current increases less than quadratically with increasing Vgs

Velocity saturationMobility degradation

Channel length modulationBody EffectLeakage currents

Sub-threshold conductionJunction leakageTunneling

Temperature DependenceGeometry Dependence

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Velocity saturation and mobility degradation

At strong lateral fields resulting from high Vds, drift velocity rolls off due to carrier scattering and eventually saturates

Strong vertical fields resulting from large Vgscause the carriers to scatter against the surface and also reduce the carrier mobility. This effect is called mobility degradation

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Channel length modulation

The reverse biased p-n junction between the drain and the body forms a depletion region with length L’ that increases with Vdb. The depletion region effectively shorten the channel length to: Leff = L – L’

Assuming the source voltage is close to the body votage Vdb ~ Vsb. Hence, increasing Vds decrease the effective channel length.

Shorter channel length results in higher current

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Body Effect

The potential difference between source and body Vsb affects (increases) the threshold voltageThreshold voltage depends on:

Vsb

ProcessDopingTemperature

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Subthreshold Conduction

The ideal transistor I-V model assumes current only flows from source to drain when Vgs > Vt.In real transistors, current doesn’t abruptly cut off below threshold, but rather drop off exponentiallyThis leakage current when the transistor is nominally OFF depends on:

process (εox, tox)doping levels (NA, or ND)device geometry (W, L)temperature (T)( Subthreshold voltage (Vt) )

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Junction LeakageThe p-n junctions between diffusion and the substrate or well for diodes.The well-to-substrate is another diodeSubstrate and well are tied to GND and VDD to ensure these diodes remain reverse biasedBut, reverse biased diodes still conduct a small amount of current that depends on:

Doping levelsArea and perimeter of the diffusion regionThe diode voltage

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Tunneling

There is a finite probability that carriers will tunnel though the gate oxide. This result in gate leakage current flowing into the gate

The probability drops off exponentially with tox

For oxides thinner than 15-20 Å, tunneling becomes a factor

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Temperature dependence

Transistor characteristics are influenced by temperature

µ decreases with TVt decreases linearly with TIleakage increases with T

ON current decreases with T OFF current increases with T

Thus, circuit performances are worst at high temperature

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Geometry Dependence

Layout designers draw transistors with Wdrawn, LdrawnActual dimensions may differ from some factor XW and XLThe source and drain tend to diffuse laterally under the gate by LD, producing a shorter effective channelSimilarly, diffusion of the bulk by WD decreases the effective channel widthIn process below 0.25 µm the effective length of the transistor also depends significantly on the orientation of the transistor

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Impact of non-ideal I-V effectsThreshold is a significant fraction of the supply voltageLeakage is increased causing gates to

consume power when idle limits the amount of time that data is retained

Leakage increases with temperatureVelocity saturation and mobility degradation result in less current than expected at high voltage

No point in trying to use high VDD to achieve fast transistorsTransistors in series partition the voltage across each transistor thus experience less velocity saturation

Tend to be a little faster than a single transistorTwo nMOS in series deliver more than half the current of a single nMOS transistor of the same width

Matching: same dimension and orientation

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Pass Transistors

nMOS pass transistors pull no higher than VDD-VtnCalled a degraded “1”Approach degraded value slowly (low Ids)

pMOS pass transistors pull no lower than |Vtp|Called a degraded “0”Approach degraded value slowly (low Ids)

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Pass transistor Circuits

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Transmission gate ON resistance

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Tri-state Inverter

If the output is tri-stated but A toggles, charge from the internal nodes (= caps) may disturb the floating output node

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Effective resistance of a transistor

First-order transistor models have limited valueNot accurate enough for modern transistorsToo complicated for hand analysis

Simplification: treat transistor as resistorReplace Ids(Vds, Vgs) with effective resistance RIds = Vds/RR averaged across switching range of digital gate

Too inaccurate to predict current at any given timeBut good enough to predict RC delay (propagation delay of a logic gate)

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RC Values

CapacitanceC = Cg = Cs = Cd = 2 fF/µm of gate widthValues similar across many processes

ResistanceR ≈ 6 KΩ*µm in 0.6um processImproves with shorter channel lengths

Unit transistorsMay refer to minimum contacted device (4/2 λ)or maybe 1 µm wide deviceDoesn’t matter as long as you are consistent

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RC Delay Models

Use equivalent circuits for MOS transistorsideal switch + capacitance and ON resistanceunit nMOS has resistance R, capacitance Cunit pMOS has resistance 2R, capacitance C

Capacitance proportional to widthResistance inversely proportional to width

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Switch level RC models

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Inverter Delay EstimateEstimate the delay of a fanout-of-1 inverter

delay = 6RC

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Resistance of a unit transmission gateThe effective resistance of a transmission gate is the parallel of the resistance of the two transistorApproximately R in both directionsTransmission gates are commonly built using equal-sized transistorsBoosting the size of the pMOS only slightly improve the effective resistance while significantly increasing the capacitance

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Summary

Models are only approximations to reality, not reality itselfModels cannot be perfectly accurate

Little value in using excessively complicated models, particularly for hand calculations

To first order current is proportional to W/LBut, in modern transistors Leff is shorter than Ldrawn

Doubling the Ldrawn reduces current more than a factor of twoTwo series transistors in a modern process deliver more than half the current of a single transistor

Use Transmission gates in place of pass transistorsTransistor speed depends on the ratio of current to capacitance

Sources of capacitance (voltage dependents)Gate capacitanceDiffusion capacitance