MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 2

1.1 INTRODUCTION TO 8086

• It is a 16-bit μp.

• Has a 20 bit address bus can access up to 220

memory locations (1 MB).

• It can support up to 64K I/O ports.

• It provides 14, 16 -bit registers.

• It has multiplexed address and data bus AD0- AD15 and A16 – A19.

• Designed to operate in two modes, Minimum and Maximum.

• It requires +5V power supply.

• A 40 pin dual in line package.

• Address ranges from 00000H to FFFFFH

1.2 REGISTER ORGANIZATION OF 8086

All the registers of 8086 are 16-bit registers. The general purpose registers can be used as either 8-bit

registers or 16-bit registers. The register set of 8086 can be categorized into 4 different groups. The

register organization of 8086 is shown in the figure.

Fig 1 Register organization of 8086

General Purpose Registers

• The first four registers are sometimes referred as data registers. They are the ax, bx, cx and dx

registers.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 3

Fig 2 general purpose registers with functions

Pointers and Index Registers

Used to keep offset addresses.

Used in various forms of memory addressing.

SP: Stack pointer

– Used to access the stack segment

BP: Base Pointer

– Primarily used to access data on the stack

– Can be used to access data in other segments

SI: Source Index register

– is required for some string operations

– When string operations are performed, the SI register points to memory locations in the data segment

which is addressed by the DS register. Thus, SI is associated with the DS in string operations.

DI: Destination Index register

– is also required for some string operations.

– When string operations are performed, the DI register points to memory locations in the data segment

which is addressed by the ES register. Thus, DI is associated with the ES in string operations.

Segment Registers

4 segments registers

Code Segment register (CS)

Data Segment register (DS)

Extra Segment register (ES)

Stack Segment register (SS).

CS: is used for addressing memory location in the code segment of the memory, where the executable

program is stored.

DS: points to the data segment of the memory where the data is stored.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 4

ES: also refers to a segment in the memory which is another data segment in the memory.

SS: is used for addressing stack segment of the memory. The stack segment is that segment of memory

which is used to store stack data.

Flag Register

A flag indicates some conditions produced by the execution of an instruction or controls .

In 8086 contains

a 16 bit flag register

9 of the 16 are active flags and remaining 7 are undefined.

6 flags indicates some conditions- status flags

3 flags –control Flags

Fig 3 flag registers in 8086

Fig 4 status flags with purposes

Fig 5 control flags with purposes

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 5

1.3 ARCHITECTURE

8086 microprocessor is internally divided into two separate functional units.

Bus Interface Unit (BIU)

Execution Unit (EU

BIU and EU functions separately

Fig 6 internal architecture of 8086

Bus Interface Unit (BIU)

• Fetches instructions, reads data from memory and I/O ports, writes data to memory and I/ O ports.

Interfaces the 8086 to the outside world. Provides all external bus operations.

• Contains Memory address and Data Bus Interface Logic, Segment registers, Memory addressing

logic, address conversion mechanism and a Six byte instruction object code queue.

• Instruction queue is a First-In First-out (FIFO) group of registers in which up to six bytes of

instruction codes are pre-fetched from memory ahead of time.

• Memory Address and Data bus interface logic of the BIU generates all the bus control signals

such as read and write signals for memory and I/O.

• Address conversion mechanism: which is used to produce the 20-bit address. It is generated using

segment and offset registers each of the size 16-bit.The content of a segment register also called as

segment address, and content of an offset register also called as offset address. To get total physical

address, put the lower nibble 0H to segment address and add offset address.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 6

Fig 7 address conversion mechanism in 8086

Fig 8 example of address conversion

• Segment registers: hold the base address of where a particular segment begins in memory.

Execution Unit (EU):

• Executes instructions that have already been fetched by the BIU.

• Contains decoder, flags ,ALU,Timing and Control circuit and Register banks

• Decoder: translates instructions.

• ALU: perform arithmetic and logic operations.

• Register banks: eight 16-bit general registers. These are AX, BX, CX, DX, SP, BP, SI and DI.

• Flags: holds the status flags after an ALU operation.

• Timing and control Circuit: Generates control signals for internal and external operations of the

microprocessor

1.4 MEMORY SEGMENTATION

The memory is organized as segmented memory.

Physically available memory may be divided into a number of logical segments.

The size of each segment is 64 KB

A segment may be located anywhere in the memory

Each of these segments can be used for a specific function.

Code segment is used for storing the instructions.

The stack segment used as a stack and it is used to store the return addresses.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 7

Data and extra segments are used for storing data byte.

Fig 9 memory segmentation in 8086

1.5 PINS AND SIGNALS

Pin diagram is shows all the signal pins used by the microprocessor and the sequence of the signals and

their connections. 8086 microprocessor is a 40 pin IC which operate on 5volt power supply.

Fig 10 pin diagram of 8086

AD0-AD15 (Bidirectional): Address/Data bus

These are multiplexed address/ data bus.

When AD lines are used to transmit memory address the symbol A is used instead of

AD, for example A0-A15.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 8

When data are transmitted over AD lines the symbol D is used in place of AD, for

example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

These are multiplexed with status signals

The S4 and S3 combined indicate which segment register is presently being used for

memory accesses.

S5 shows the status of Interrupt enable flag status.

The status line S6 is always low (logical).

Fig 11 purposes of pins s4 and s3

NMI-Non-maskable Interrupt

Is not maskable internally by software.

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit

device connected to upper half of the data bus use BHE (Active Low) signal. It is

multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 9

input is tested by the ‘WAIT’ instruction

8086 will enter a wait state after execution of the WAIT instruction and will resume

execution only when the is made low by an active hardware.

This is used to synchronize an external activity to the processor internal operation.

READY

This is the acknowledgement from the slow device or memory that they have

completed the data transfer.

RESET (Input)

Causes the processor to immediately terminate its present activity.

The signal must be active HIGH for at least four clock cycles.

CLK

The clock input provides the basic timing for processor operation and bus control

activity.

INTR (Interrupt Request)

This is a triggered input. This is sampled during the last clock cycles of each

instruction to determine the availability of the request. If any interrupt request is

pending, the processor enters the interrupt acknowledge cycle.

DT/ (Data Transmit/ Receive)

Output signal from the processor to control the direction of data flow through the data

transceivers.

(Data Enable)

Output signal from the processor used as output enable for the transceivers

ALE (Address Latch Enable)

Used to demultiplex the address and data lines using external latches

M/

Used to differentiate memory access and I/O access. For memory reference

instructions, it is high. For IN and OUT instructions, it is low.

: Write control signal

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 10

asserted low Whenever processor writes data to memory or I/O port

(Interrupt Acknowledge)

When the interrupt request is accepted by the processor, the output is low on this line.

HOLD

Input signal to the processor form the bus masters as a request to grant the control of

the bus.

HLDA (Hold Acknowledge)

Acknowledge signal by the processor to the bus master requesting the control of the

bus through HOLD.

, , Status signals

Used by the 8086 bus controller to generate bus timing and control signals. These are

decoded as shown.

, (Queue Status)

The processor provides the status of queue in these lines.

The output on QS0 and QS1 can be interpreted as shown in the table.

Fig 12 purposes of S0, S1, S2, QS0 and QS1

, (Bus Request/ Bus Grant)

These requests are used by other local bus masters to force the processor to release

the local bus at the end of the processor’s current bus cycle.

These pins are bidirectional.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 11

The request on will have higher priority than

An output signal activated by the LOCK prefix instruction.

The 8086 output low on the pin while executing an instruction prefixed by

LOCK to prevent other bus masters from gaining control of the system bus.

1.6 PHYSICAL MEMORY ORGANIZATION

In an 8086 based system, the 1Mbyte memory is physically organized as odd bank and even bank,

each of 512kbytes, addressed in parallel by the processor.

Byte data with even address is transferred on D0-D7 and byte data with odd address is transferred

on D8-D15.

The processor provides two enable signals, BHE and A0 for selecting of either even or odd or both

the banks.

Fig 13 memory selection pins

Fig 14 physical memory organization

1.7 GENERAL BUS OPERATION

The 8086 has a combined address and data bus commonly referred as a time multiplexed address

and data bus.

The main reason behind multiplexing address and data over the same pins is the maximum

utilization of processor pins and it facilitates the use of 40 pin standard DIP package.

The bus can be demultiplexed using a few latches and transceivers, whenever required.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 12

The main reason behind multiplexing address and data over the same pins is the maximum

utilization of processor pins and it facilitates the use of 40 pin standard DIP package.

Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as

T1, T2, T3, and T4. The address is transmitted by the processor during T1. It is present on the bus

only for one cycle.

T2, i.e. the next cycle, is the data read cycle.

The data transfer takes place during T3 and T4. In case, an addressed device is slow and shows

‘NOT READY’ status the wait states Tw are inserted between T3 and T4.

The address latch enable (ALE) signal is emitted during T1 by the processor (minimum mode) or

the bus controller (maximum mode) depending upon the status of the MN/MX input.

Fig 15 bus operation

1.8 MINIMUM AND MAXIMUM MODE

Minimum Mode

This is a single microprocessor configuration selected by applying logic 1 to the MN / MX input

pin.

The remaining components in the system are latches, transceivers, clock generator, memory and I/O

devices.

Latches are used to separate valid address from address/data signals controlled by ALE

Transceivers are bidirectional buffers Also termed as data amplifiers Controlled by DEN or DT/R

No interfacing or master/slave signals is required.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 13

No bus controller required.

The DEN signal indicates the direction of data, i.e. from or to the processor.

The system contains memory for the monitor and users program storage. Usually, EPROM are used

for monitor storage, while RAM for user’s program storage. A system may contain I/O devices

Fig 18 minimum mode operation of 8086

Maximum mode

MN/MX connect to Ground

Some control signals are generated externally by the 8288 bus controller chip

8086 generates QS1, QS0, S0, S1, S2, LOCK, RQ/GT1, RQ/GT0 control signals.

Max mode is used when math processor is used.

Master/slave, multiplexing and several such control signals are required.

The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by

CPU.

It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC.

The AEN, IOB and CEN pins are specially useful for multiprocessor systems.

IORC, IOWC are I/O read command and I/O write command signals respectively. These signals

enable an IO interface to read or write the data from or to the address port.

The MRDC, MWTC are memory read command and memory write command signals respectively

and may be used as memory read or write signals.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 14

Fig 19 maximum mode operation of 8086

Fig 20 comparison between Minimum and Maximum modes

1.9 ADDRESSING MODES

The different ways in which a source operand is denoted in an instruction are known as addressing

modes.

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing

7. Based Index Addressing

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 15

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

1. Register Addressing

The instruction will specify the name of the register which holds the data to be operated by the

instruction.

Example:

MOV CL, DH

The content of 8-bit register DH is moved to another 8-bit register CL

(CL) (DH)

2. Immediate Addressing

an 8-bit or 16-bit data is specified as part of the instruction

Example:

MOV DL, 08H

The 8-bit data (08H) given in the instruction is moved to DL (DL) 08H

3. Direct Addressing

The address of the memory location at which the data operand is stored is given in the instruction.

The effective address is just a 16-bit number written directly in the instruction.

Example:

MOV BX, [1354H]

MOV BL, [0400H]

The square brackets around the 1354H denotes the contents of the memory location. When

executed, this instruction will copy the contents of the memory location into BX register.

4. Register Indirect Addressing

In Register indirect addressing, name of the register which holds the effective address (EA) will be

specified in the instruction.

Registers used to hold EA are any of the following registers: BX, BP, DI and SI.

Example:

MOV CX, [BX]

5. Based Addressing

In Based Addressing, BX or BP is used to hold the base value for effective address and a signed 8-

bit or unsigned 16-bit displacement will be specified in the instruction.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 16

When BX holds the base value of EA, 20-bit physical address is calculated from BX and DS.

When BP holds the base value of EA, BP and SS is used.

Example:

MOV AX, [BX + 08H]

6. Indexed Addressing

SI or DI register is used to hold an index value for memory data and a signed 8-bit or unsigned 16-

bit displacement will be specified in the instruction.

Displacement is added to the index value in SI or DI register to obtain the EA.

Example:

MOV CX, [SI + 0A2H]

7. Based Index Addressing

In Based Index Addressing, the effective address is computed from the sum of a base register (BX

or BP), an index register (SI or DI) and a displacement.

Example:

MOV DX, [BX + SI + 0AH]

8. String Addressing

Employed in string operations to operate on string data.

The effective address (EA) of source data is stored in SI register and the EA of destination is stored

in DI register.

Segment register for calculating base address of source data is DS and that of the destination data is

ES.

Example:

MOVS BYTE

9. Direct I/O port Addressing

are used to access data from standard I/O mapped devices or ports.

In direct port addressing mode, an 8-bit port address is directly specified in the instruction.

Example: IN AL, [09H]

Operations: PORTaddr = 09H

(AL) (PORT)

10. Indirect I/O port Addressing

The port number is taken from DX allowing 64K 8 bit ports or 32K 16 bit ports.

Example:- IN AX,DX

If [DX]=5040,Inputs the 8 bit content of port 5040 into AL and 5041 into AH.

MODULE 1 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai Page 17

11. Relative Addressing

In this addressing mode, the effective address of a program instruction is specified relative to

Instruction Pointer (IP) by an 8-bit signed displacement.

Example: JZ 0AH

12. Implied Addressing

Instructions using this mode have no operands. The instruction itself will specify the data to be

operated by the instruction.

Example: CLC

This clears the carry flag to zero.