Clocks and Timing/Overview

Definitions and Conventions Synchronous circuits and Timing Margin Clock skew and clock distribution Other timing conventions Clock oscillators Jitter

Definitions Mathematical description:

( ) ( ) ( )( )[ ]1modttffptx ++=where p(t) is a 50% duty cycle pulse, f is the nominal frequency, (t) is the instantaneous phase (expressed as a fraction of a cycle) and f is a frequency offsetIf f is a constant then the signal is isochronous; if f varies as a function of time, then the signal is anisochronousIsochronous signals have bounded phase (and the derivative of phase instantaneous frequency has a time average of 0), anisochronous signals do not.

DefinitionsInstantaneous frequency

( ) ( )tdtdfftf ++=

Instantaneous phase difference expresses the phase jitter

( ) ( ) ( ) ( )( )tttfft 2121 +=

tt

f(t) (t)

Terminology Synchronous - significant edge of the signals is

locked to a common source More correctly instantaneous phase difference = 0

Mesochronous - signals with the same average frequency which have a bounded delay or skew between them

Clk1

Clk2

tclk1-clk2

T1=T2

Timing Signal Definitions Asynchronous - two signals with different frequencies;

must be synchronized into each others clock domains Plesiochronous - two signals with the same nominal

frequency but with a different actual frequency; time-varying instantaneous phase difference

Heterochronous two signal with nominally different average frequencies (usually known)

fr

fwExample: data transfer

What happens if fw fr?

Timing Conventions

Synchronous timing - all signals have their timing referenced to a single clock: a single clock domain Timing margin must be calculated to allow for

uncertainties in delays and clock skew Globally asynchronous, locally synchronous

For larger systems where clock skew becomes too large

Timing Margin

Clk

outputQ2D2Q1D1

2-bit ring counter circuit should produce repeating sequence, 00110011

At a certain frequency it fails, due to failure of setup time atD2

Timing Margin

Q1

Clk1

D2

TsetupClk2

Q2

D1

Clk1 to Q1 output delay

Gate propagation delayTiming margin is almost gone

Setup time for D1 is ok

Calculating Timing Margin

To calculate worst-case timing margin, at a gate input:

earliest arrival required

Tarr

= Tclk _ pd1 + TclktoQ1,max + TG ,max

Treq = Tclk + Tclk _ pd 2 Tsu

Vs latest arrival possible

Calculating Timing Margin

We require:

Tarr

< Treq

Tclk > TclktoQ1,max + TG ,max + Tsu + Tclk _ pd1 Tclk _ pd 2( )

Which, by substituting for Tarr and Treq:

Note that in this case, the difference between clock delay along different paths, clock skew, matters!

Timing Margin

Measures the slack in the clock cycle that allows for factors such as: variations in propagation delay clock skew crosstalk signal delay and jitter

Systems with a bigger timing margin can run at higher clock speeds without failure

What is Clock Skew?

Skew is just the average delay between two signals

As a clock is distributed across a system variations in propagation delay, length of tracks, performance of clock drivers mean that the timing of the clock edge becomes progressively delayed

Controlling Clock Skew

Brute force approach is to locate all clock inputs close together and drive from the same source

Clearly this will only work in limited circumstances e.g. small layouts, few clock inputs

Controlling Clock Skew Spider distribution network

Clock

Clk driver

As number of loads increases, so driver load decreases - needs a powerful driver e.g. connect drivers in parallel or use a low-impedance amplifier

Damp reflections with end termination

Clock Distribution Tree

Clk

Notice that every path traverses the same number of drivers

Delay Control We can use adjustments to clock delays to achieve

either low clock skew - improves timing margin purposeful skew - at some point in a circuit, increasing

the skew of a clock edge may be used to increase timing margin - but only at that point

Approaches to adjust clock delays Fixed delay element Adjustable delay element Programmable delay element

Fixed Delay Element Built from transmission lines, logic gates or

passive (lumped) elements Delay lines (transmission lines) very

accurate for short delays

5-20%0.1-1000Lumped circuit

300%0.1-20Gate delay10%0.1-5Delay line

Variation in delay

Amount of delay (ns)

Fixed Delay Element/Lumped Circuit Approach

R

C

Quality and accuracy of R and C importantFor use with CMOS gates - does not affect noise margin

With TTL and HCT affects noise margin as too much current is required; also produces asymmetric delays

Fixed Delay Element/Gate delay

Using a track on a pcb as a delay element uses up a lot of space 1 ns delay costs 0.135 in2 (87 mm2)

A spare gate is effective as a delay element But, variation in delay is often very large Often no choice inside FPGA etc.

Adjustable Delays All three types of delays come in adjustable

versions Delay lines have jumpers or taps which

provide delays in quantized steps Lumped circuit element delays are more

continuously adjustable Chains of gates may be used but will have a

wide inaccuracy

Delays - Considerations

Adjustable delay can be used to adjust for actual delays in the circuit

A fixed delay cannot deal with variations in delay due to manufacturing and device variability

Incorporate the uncertainty of the delay used into timing margin calculations

Clock Duty Cycle Desirable clock duty cycle is 50% Can also use inverted clock as a timing

signal Clock duty cycle changes through clock

distribution because drivers have asymmetrical response to rising and falling edges

Pulse width compression/expansion

Pulse Width Distortion

Clk1

Clk2

Clk3

Clk4

Here the rising edge is delayed a bit more than the falling edgeso the positive pulse shrinks as it passes through the system

To prevent pulse width distortion use a chain of inverting drivers

Use an analog fix - feedback to tweak the input switching threshold of the driver

Clk

Pulse Width Distortion

Pipelined Timing For a system (or sub-system) in which data

flow is uni-directional System is broken up into stages - each has

its own clock which is a progressively delayed version of system clock

Throughput is limited only be total timing uncertainty

Clk

Data

Produces delay and inverts phase

Closed-Loop Timing

Using a system which actively controls timing parameters such as phase of clocks, delays or frequencies

Typically uses feedback control such as a PLL

Clock Oscillators

Modern piezoelectric quartz crystal oscillators are extremely accurate so variations from nominalfrequency can often be overlooked

Frequency specifications: Nominal frequency +/- stability (% or ppm)

Typically 10kHz to 300 MHz ppm indicates higher quality than % (100ppm = 0.01%)

Aging - frequency drift per year New crystals age faster, then drift slows down!

Voltage sensitivity ppm/volt

Temperature stability

Most important determinant of stability Cheapest oscillators are noncompensated Can also get temperature-compensated which

includes circuitry to counteract temp. induced drift

Oven-controlled oscillators are the best Note that drift is not linear with temperature -

be sure to check operating range

Clock Jitter Noise affecting a clock signal causes its

edges to deviate from their ideal positions Timing jitter is defined as the deviation of

the timing of a clock edge from its ideal position

Jitter - measured in seconds

Clock Jitter Phase jitter is defined as a variation in the

proportion of the clock cycle achieved at a certain time with respect to the ideal

Phase and timing jitter often used as if the same thing. This is not the case, but for low levels of jitter, the approximation can be made

Phase jitter can be measured in the frequency domain as a frequency deviation

Causes of Jitter In clock sources:

Noise from the crystal itself Effect of mechanical perturbations Amplifier noise Power supply noise

Elsewhere: Timing uncertainty from variable delays (gates,

propagation), crosstalk, temperature variations,

Why does jitter matter?

fr

fwExample: data transfer

What happens if fw fr?

Even if fw = fr , the clocks are synchronized to a common reference

jitter can still cause buffer overflow or underflow

Measuring Jitter Spreading and spurs around the fundamental frequency

peak as measured by a spectral analyzer

fosc

Noise power in dBc

1 Hz band

spurs

Phase noise in dBc/Hz

fm = offset from carrier (Hz)

Calculating RMS Jitter from Phase Noise Measurement

Integrate over range of interest to get noise power ( )dffLN m

m

f

f=2

1

Convert to RMS jitter in radians10/102 NRMSJ =

Convert to RMS jitter in seconds oscRMSRMS fradsJJ pi2/)(=

Measuring Jitter Measure directly in the time domain using

appropriate equipment Some oscilloscopes can easily be set up to

measure it Differential phase measurement technique -

simply measure the clock using delayed time base sweep on oscilloscope

Jitter becomes uncorrelated if delay is large enough and can be observed as a blur on clock edge