MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or STP ... · input (oLDI) and a CML serial...

General DescriptionThe MAX9277/MAX9281 are 3.12Gbps Gigabit Multimedia Serial Link (GMSL) serializers with 3- or 4-data lane LVDS input (oLDI) and a CML serial output programmable for 50Ω coax or 100Ω shielded twisted pair (STP) cable drive. The MAX9281 has HDCP content protection but other-wise is the same as the MAX9277. The serializers pair with any GMSL deserializer capable of coax input. When programmed for STP output they are backward compat-ible with any GMSL deserializer. The output amplitude is programmable 100mV to 500mV single-ended (coax) or 100mV to 400mV differential (STP).The audio channel supports L-PCM I2S stereo and up to eight channels of L-PCM in TDM mode. Sample rates of 32kHz to 192kHz are supported with sample depth up to 32 bits.The embedded control channel operates at 9.6kbps to 1Mbps in UART-UART and UART-I2C modes, and up to 1Mbps in I2C-I2C mode. Using the control channel, a µC can program serializer, deserializer and peripheral device registers at any time, independent of video timing, and manage HDCP operation (MAX9281). A GPO output sup-ports touch-screen controller interrupt requests from the remote end of the link.For use with longer cables, the serializers have program-mable pre/deemphasis. Programmable spread spectrum is available on the serial output. The serial output meets ISO 10605 and IEC61000-4-2 ESD standards. The core supply is 1.7 to 1.9V and the I/O supply is 1.7 to 3.6V. The package is a lead-free, 48-pin, 7mm x 7mm TQFN with exposed pad and 0.5mm lead pitch.

Applications● High-Resolution Automotive Navigation● Rear-Seat Infotainment● Megapixel Camera Systems

Features and Benefits ● Ideal for High-Definition Video Applications

• Drives Low-Cost 50Ω Coax Cable and FAKRA Connectors or 100Ω STP

• 104MHz High-Bandwidth Mode Supports 1920x720p/60Hz Display With 24-Bit Color

• Serializer Pre/Deemphasis Allows 15m Cable at Full Speed

• Up to 192kHz Sample Rate and 32-Bit Sample Depth For 7.1 Channel HD Audio

● Multiple Data Rates for System Flexibility• Up to 3.12Gbps Serial-Bit Rate• 6.25MHz to 104MHz Pixel Clock• 9.6kbps to 1Mbps Control Channel in UART,

mixed UART/I2C, or I2C Mode with Clock Stretch Capability

● Reduces EMI and Shielding Requirements• Serial Output Programmable for 100mV to 500mV

Single-Ended or 100mV to 400mV Differential• Programmable Spread Spectrum Reduces EMI• Bypassable Input PLL for Pixel Clock Jitter

Attenuation• Tracks Spread Spectrum on Input• High-Immunity Mode for Maximum Control-

Channel Noise Rejection ● Peripheral Features for System Power-Up and

Verification• Built-In PRBS Generator for BER Testing of the

Serial Link• Programmable Choice of 9 Default Device

Addresses• Dedicated “Up/Down” GPO for Touch-Screen

Interrupt and Other Uses• Remote/Local Wake-Up from Sleep Mode

● Meets Rigorous Automotive and Industrial Requirements• -40ºC to +105ºC Operating Temperature• 8kV Contact and 15kV Air ISO 10605 and

IEC 61000-4-2 ESD Protection

Ordering Information appears at end of data sheet.

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or STP Output Drive and LVDS Input

19-6764; Rev 2; 7/15

EVALUATION KIT AVAILABLE


www.maximintegrated.com Maxim Integrated │ 2

TABLE OF CONTENTSGeneral Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Input Bit Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Serial Link Signaling and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Reserved Bit (RES)/CNTL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33High-Bandwidth Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Audio Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Audio Channel Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Interfacing Command-Byte-Only I2C Devices With UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Bus Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42I2C Communication with Remote Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

I2C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43



Pre/Deemphasis Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Coax Splitter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45High-Immunity Reverse Control Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48High-Bandwidth Digital Content Protection (HDCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Encryption Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Synchronization of Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Repeater Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

HDCP Authentication Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52HDCP Protocol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Example Repeater Network—Two µCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Detection and Action Upon New Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Notification of Start of Authentication and Enable of Encryption to Downstream Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Self PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Jitter-Filtering PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60RXCLKIN Spread Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Changing the Clock Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Providing a Frame Sync (Camera Applications). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613-Level Configuration Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Compatibility with other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Key Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61HS/VS/DE Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

TABLE OF CONTENTS (continued)



TABLE OF CONTENTS (continued)WS/SCK Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Line-Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Choosing I2C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75



LIST OF FIGURESFigure 1. Serial-Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 2. Output Waveforms at OUT+, OUT- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 3. Single-Ended Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 4. Line Fault Detector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 5. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 6. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 7. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 8. Input Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 9. LVDS Receiver Input Skew Margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 10. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 11. Serializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 12. Link Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 13. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 14. Input I2S Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 15. LVDS Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 16. LVDS Clock and Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 17. 3-Channel Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 18. 4-Channel Mode Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 19. High-Bandwidth Mode Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 20. Audio Channel Input Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 21. 8-Channel TDM (24-Bit Samples, Padded with Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 22. 6-Channel TDM (24-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 23. Stereo I2S (24-Bit Samples, Padded with Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 24. Stereo I2S (16-Bit Samples, No Padding). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 25. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 26. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 27. Sync Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 28. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 29. Format Conversion between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . 39Figure 30. Format Conversion between GMSL UART and I2C with Register Address (I2CMETHOD = 1) . . . . . . . . 39



LIST OF FIGURES (continued)Figure 31. START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 32. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 33. Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Figure 34. Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Figure 35. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 36. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 37. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 38. 2:1 Coax Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 39. Coax Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 40. State Diagram, CDS = LOW (Video Display Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Figure 41. State Diagram, CDS = HIGH (Image Sensing Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 42. Example Network with One Repeater and Two µCs (Tx = GMSL Serializers, Rx = Deserializers) . . . . . 56Figure 43. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Figure 44. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Figure 45. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64



LIST OF TABLES

Table 1. Power-Up Default Register Map (see Table 25 and Table 26). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 2. Device Address Defaults (Register 0x00, 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 3. Input Map (See Figure 15, Figure 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 4. Data-Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Table 5. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . 34Table 6. I2C Bit-Rate Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 7. TP/COAX Drive Current (400mV Output Drive Levels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 8. Serial Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 9. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 10. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 11. CONF[1:0] Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 12. Reverse Control Channel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 13. Fast High-Immunity Mode Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 14. Startup Procedure for Video-Display Applications (CDS = Low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 15. Startup Procedure for Image-Sensing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 16. Startup, HDCP Authentication, and Normal Operation (Deserializer is not a Repeater)—First Part of the HDCP Authentication Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Table 17. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 18. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After Encryption is Enabled . . . . 55Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the HDCP Authentication Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 20. MAX9277/MAX9281 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 21. Line Fault Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 22. Typical Power-Supply Currents (Using Worst-Case Input Pattern, VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C, SSEN = High, No HDCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 23. Additional Supply Current from HDCP (MAX9281 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 24. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 25. Register Table (see Table 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 26. HDCP Register Table (MAX9281 Only, see Table 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

AVDD to AGND ....................................................-0.5V to +1.9VDVDD to AGND ....................................................-0.5V to +1.9VIOVDD to AGND ...................................................-0.5V to +3.9VLVDSVDD to AGND .............................................-0.5V to +3.9VGND to AGND ......................................................-0.5V to +0.5VLMN_ to AGND (15mA current limit) ....................-0.5V to +3.9VOUT+, OUT- to AGND ..........................................-0.5V to +1.9VAll Other Pins to AGND .......................-0.5V to (VIOVDD + 0.5V)

OUT+, OUT- Short Circuit to Ground or Supply........ContinuousContinuous Power Dissipation (TA = +70ºC)TQFN (derate 40mW/ºC above +70ºC) ........................3200mWJunction Temperature ...................................................... +150ºCStorage Temperature .........................................-65ºC to +150ºCLead Temperature (soldering, 10s) ................................. +300ºCSoldering Temperature (reflow) .......................................+260ºC

TQFN Junction-to-Case Thermal Resistance (θJC) ................ 1°C/W Junction-to-Ambient Thermal Resistance (θJA) ......... 25°C/W

(Note 2)

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSSINGLE-ENDED INPUTS (CX/TP, PWDN, MS/CNTL0, CDS/CNTL3, SD, SCK, WS, AUTOS, CNTL1, CNTL2, HIM)

High-Level Input Voltage VIH1

(CX/TP, PWDN, MS/CNTL0, CDS/CNTL3, AUTOS, HIM)

0.65 x VIOVDD V

SD, SCK, WS, CNTL1, CNTL2 0.7 x VIOVDD

Low-Level Input Voltage VIL10.35 x

VIOVDDV

Input Current IIN1 VIN = 0V to VIOVDD -10 +20 µA

THREE-LEVEL LOGIC INPUTS (CONF0, CONF1, ADD0, ADD1, BWS)

High-Level Input Voltage VIH0.7 x

VIOVDDV


VIOVDDV

Mid-Level Input Current IINM (Note 4) -10 +10 µA

Input Current IIN -150 +150 µA

SINGLE-ENDED OUTPUT (GPO)

High Level Output Voltage VOH1 IOUT = -2mAVIOVDD -

0.2 V

Low Level Output Voltage VOL1 IOUT = 2mA 0.2 V

OUTPUT Short-Circuit Current IOS VOUT = 0V

VIOVDD = 3.0V to 3.6V 16 35 64 mAVIOVDD = 1.7V to 1.9V 3 12 21



Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Note 1: AGND, GND connected to PCB ground.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Thermal Characteristics

DC Electrical Characteristics


PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OPEN-DRAIN INPUT/OUTPUT (RX/SDA, TX/SCL, LFLT)

High-Level Input Voltage VIH20.7 x

VIOVDDV


VIOVDDV

Input Current IIN2 (Note 5)RX/SDA, TX/SCL -110 +5 µA

LFLT -80 +5

Low-Level Output Voltage VOL2 IOUT = 3mAVIOVDD = 1.7V to 1.9V 0.4 VVIOVDD = 3.0V to 3.6V 0.3

Input Capacitance CIN Each pin (Note 9) 10 pF

DIFFERENTIAL SERIAL OUTPUT (OUT+, OUT-)

Differential Output Voltage VOD

Pre-emphasis off (Figure 1) 300 400 500

mV3.3dB preemphasis setting (Figure 2) 350 610

3.3dB deemphasis setting (Figure 2) 240 425

Change in VOD Between Complimentary Output States ΔVOD Preemphasis off, deemphasis only 15 mV

Output Offset Voltage(VOUT+ + VOUT-)/2 = VOS

VOS Preemphasis off 1.1 1.4 1.56 V

Change in VOS between Complimentary Output States ΔVOS 15 mV

Output Short-Circuit Current IOSVOUT+ or VOUT- = 0V -62 mAVOUT+ or VOUT- = 1.9V 25

Magnitude of Differential Output Short-Circuit Current IOSD VOD = 0V 25 mA

Output Termination Resistance (Internal) ROUT From OUT+, OUT- to VAVDD 45 54 63 Ω

SINGLE-ENDED SERIAL OUTPUT (OUT+, OUT-)

Single-Ended Output Voltage VOUT

Pre-emphasis off, high drive (Figure 3) 375 500 625

mV3.3dB preemphasis setting, high drive (Figure 2) 435 765

3.3dB deemphasis setting, high drive (Figure 2) 300 535

Output Short-Circuit Current IOSVOUT+ or VOUT- = 0V -69 mAVOUT+ or VOUT- = 1.9V 32

Output Termination Resistance (Internal) RO From OUT+ or OUT- to VAVDD 45 54 63 Ω



DC Electrical Characteristics (continued)



REVERSE CONTROL CHANNEL RECEIVER (OUT+, OUT-)

High Switching Threshold VCHRNormal-immunity mode 27

mVHigh-immunity mode 40

Low Switching Threshold VCLRNormal-immunity mode -27

mVHigh-immunity mode -40

LINE FAULT DETECTION INPUT (LMN_)

Short-to-GND Threshold VTG Figure 4 0.3 V

Normal Threshold VTN Figure 4 0.57 1.07 V

Open Threshold VTO Figure 4 1.45VIO + 0.06 V

Open Input Voltage VIO Figure 4 1.47 1.75 V

Short-to-Battery Threshold VTE Figure 4 2.47 V

LVDS INPUTS (RXIN_, RXCLKIN_)

Differential Input High Threshold VTH VCM = 1.2V 50 mV

Differential Input Low Threshold VTL VCM = 1.2V -50 mV

Input Differential Termination Resistance RTERM 85 110 135 Ω

Input Current IIN+, IIN-PWDN = high or low, IN+ and IN- are shorted -25 +25 µA

Power-Off Input Current IIN0+, IIN0- VAVDD = VDVDD = VIOVDD = 0V -40 +40 µA

POWER SUPPLY

Total Supply Current (AVDD + DVDD + IOVDD) (Note 6) (Worst-Case Pattern, Figure 5)

IWCS

BWS = low

fPCLKIN_ = 16.6MHz 100 125

mA

fPCLKIN_ = 33.3MHz 106 140

fPCLKIN_ = 66.6MHz 123 155

fPCLKIN_ = 104MHz 146 190

BWS = midfPCLKIN_ = 36.6MHz 108 145


LVDSVDD Worst-Case Supply Current (Figure 5, Note 6)

IWCS

BWS = low

fPCLKIN_ = 16.6MHz 24 30

mA




BWS = midfPCLKIN_ = 36.6MHz 29 35






(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)


Sleep Mode Supply Current ICCSSingle wake-up receiver enabled, LVDS inputs not driven 42 170 µA

Power-Down Supply Current ICCZ PWDN = GND 6 120 µA

ESD PROTECTION

OUT+, OUT- (Note 6) VESD

Human body model, RD = 1.5kΩ, CS = 100pF

±8

kVIEC 61000-4-2, RD = 330Ω, CS = 150pF

Contact discharge ±10

Air discharge ±12

ISO 10605, RD = 2kΩ, CS = 330pF


Air discharge ±25

RXIN_, RXCLKIN_ (Note 7) VESD

Human body model, RD = 1.5kΩ, CS = 100pF

±8

kV

IEC 61000-4-2, RD = 330Ω, CS = 150pF


Air discharge ±20

ISO 10605, RD = 2kΩ, CS = 330pF


Air discharge ±30

All Other Pins (Note 8) VESDHuman body model, RD = 1.5kΩ, CS = 100pF

±4 kV


CLOCK INPUT (RXCLKIN)

Clock Frequency fRXCLKIN_

BWS = low, DRS = ‘1’ 8.33 16.66

MHz

BWS = low, DRS = ‘0’ 16.66 104

BWS = mid, DRS = ‘1’ 18.33 36.66

BWS = mid, DRS = ‘0’ 36.66 104

BWS = high, DRS = ‘1’ 6.25 12.5

BWS = high, DRS = ‘0’ 12.5 78

I2C/UART PORT TIMING

I2C/UART Bit Rate 9.6 1000 kbps

Output Rise Time tR30% to 70%, CL = 10pF to 100pF, 1kΩ pullup to IOVDD 20 150 ns

Output Fall Time tF70% to 30%, CL = 10pF to 100pF, 1kΩ pullup to IOVDD 20 150 ns




AC Electrical Characteristics



I2C TIMING (Figure 6)

SCL Clock Frequency fSCL

Low fSCL range:(I2CMSTBT = 010, I2CSLVSH = 10) 9.6 100 kHz

Mid fSCL range:(I2CMSTBT 101, I2CSLVSH = 01) > 100 400 kHz

High fSCL range:(I2CMSTBT = 111, I2CSLVSH = 00) > 400 1000 kHz

START Condition Hold Time tHD:STA fSCL range

Low 4.0

µsMid 0.6

High 0.26

Low Period of SCL Clock tLOW fSCL range

Low 4.7

µs

Mid 1.3

High

VIOVDD = 1.7V to < 3V (Note 9) 0.6

VIOVDD = 3.0V to 3.6V 0.5

High Period of SCL Clock tHIGH fSCL range

Low 4.0

µsMid 0.6

High 0.26

Repeated START Condition Setup Time tSU:STA fSCL range

Low 4.7

µsMid 0.6

High 0.26

Data Hold Time tHD:DAT fSCL range

Low 0

µsMid 0

High 0

Data Setup Time tSU:DAT fSCL range

Low 250

µsMid 100

High 50

Setup Time for STOP Condition tSU:STO fSCL range

Low 4.0

µsMid 0.6

High 0.26

Bus Free Time tBUF fSCL range

Low 4.7

µsMid 1.3

High 0.5



AC Electrical Characteristics (continued)



Data Valid Time tVD:DAT fSCL range

Low 3.45

µs

Mid 0.9

High

VIOVDD = 1.7V to < 3V (Note 10)

0.55

VIOVDD = 3.0V to 3.6V 0.45

Data Valid Acknowledge Time tVD:ACK fSCL range

Low 3.45

µs

Mid 0.9

High

VIOVDD = 1.7V to < 3V (Note 11)

0.55

VIOVDD = 3.0V to 3.6V 0.45

Pulse Width of Spikes Suppressed tSP fSCL range

Low 50

nsMid 50

High 50

Capacitive Load Each Bus Line CB Note 12 100 pF

SWITCHING CHARACTERISTICS (Note 12)

Differential Output Rise/Fall Time tR, tF

20% to 80%, VOD ≥ 400mV, RL = 100Ω, serial bit rate = 3.12Gbps 90 150 ps

Total Serial Output Jitter (Differential Output) tTSOJ1

3.12Gbps PRBS signal, measured at VOD = 0V differential, pre-emphasis disabled, Figure 7

0.21 UI

Deterministic Serial Output Jitter (Differential Output) tDSOJ2

3.12Gbps PRBS signal, measured at VOD = 0V differential, pre-emphasis disabled, Figure 7

0.09 UI

Total Serial Output Jitter (Single-Ended Output) tTSOJ1

3.12Gbps PRBS signal, measured at VO/2, pre-emphasis disabled, Figure 3

0.19 UI

Deterministic Serial Output Jitter (Single-Ended Output) tDSOJ2

3.12Gbps PRBS signal, measured at VO/2, Pre-emphasis disabled, Figure 3

10 UI

CNTL_ Input Setup Time tSET Figure 8 3 ns

CNTL_ Input Hold Time tHOLD Figure 8 1.5 ns

RXIN_ Skew Margin tRSKM No RXCLKIN spread, Figure 9 0.3 UI





Note 3: Limits are 100% production tested at TA = +105°C. Limits over the operating temperature range are guaranteed by design and characterization, unless otherwise noted.

Note 4: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current must be less than ±10μA.

Note 5: IIN MIN due to voltage drop across the internal pullup resistor.Note 6: HDCP not enabled (MAX9281 only). See Table 23 for additional supply current when HDCP is enabled.Note 7: Specified pin to ground.Note 8: Specified pin to all supply/ground.Note 9: The I2C bus standard tLOW min = 0.5µs. Note 10: The I2C bus standard tVD:DAT max = 0.45µs. Note 11: The I2C bus standard tVD:ACK max = 0.45µs. Note 12: Not production tested. Guaranteed by design.Note 13: Measured in serial link bit times. Bit time = 1/(30 x fPCLKIN) for BWS = ‘0’ or open. Bit time = 1/(40 x fPCLKIN)

for BWS = ‘1’.


GPI to GPO Delay tGPIODeserializer GPI to serializer GPO, Figure 10 350 µs

Serializer Delay (Note 13) tSD Figure 11Spread-spectrum enabled 5440

BitsSpread-spectrum disabled 1920

Link Start Time tLOCK Figure 12 3.5 ms

Power-Up Time tPU Figure 13 8 ms

I2S/TDM INPUT TIMING

WS Frequency fWS See Table 5 8 192 kHz

Sample Word Length nWS See Table 5 8 32 Bits

SCK Frequency fSCK fSCK = fWS x nWS x (2 or 8) (8 x 2) x 2 (192 x 32) x 8 kHz

SCK Clock High Time tHC VSCK ≥ VIH, tSCK = 1/fSCK (Note 13) 0.35 x tSCK ns

SCK Clock Low Time tLC VSCK ≥ VIL, tSCK = 1/fSCK (Note 13) 0.35 x tSCK ns

SD, WS Setup Time tSET Figure 14 (Note 13) 2 ns

SD, WS Hold Time tHOLD Figure 14 (Note 13) 2 ns




(VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C, unless otherwise noted.)

120

130

140

150

160

170

180

5 15 25 35 45 55 65 75 85 95 105

SUPP

LY C

URRE

NT (m

A)

RXCLKIN FREQUENCY (MHz)

SUPPLY CURRENTvs. RXCLKIN FREQUENCY (BWS = LOW)

toc01

PRBS ON,COAX MODE,

SS OFF,HDCP OFF

PREEMPHASIS = 0x00

PREEMPHASIS = 0x01 to 0x04

PREEMPHASIS = 0x0B to 0x0F

120

130

140

150

160

170

180

15 30 45 60 75 90 105SU

PPLY

CUR

RENT

(mA)


SUPPLY CURRENTvs. RXCLKIN FREQUENCY (BWS = OPEN)

toc02

PRBS ON, COAX MODE,

SS OFF, HDCP OFF

PREEMPHASIS = 0x00



120

130

140

150

160

170

180

5 20 35 50 65 80

SUPP

LY C

URRE

NT (m

A)


SUPPLY CURRENTvs. RXCLKIN FREQUENCY (BWS = HIGH)

toc03

PRBS ON,COAX MODE,

SS OFF,HDCP OFF

PREEMPHASIS = 0x00



120

130

140

150

160

170

180

5 15 25 35 45 55 65 75 85 95 105

SUPP

LY C

URRE

NT (m

A)


SUPPLY CURRENTvs. RXCLKIN FREQUENCY (BWS = LOW)

toc04

PRBS ON,COAX MODE,

PE OFF,HDCP OFF

ALL SPREAD VALUES

120

130

140

150

160

170

180

15 30 45 60 75 90 105

SUPP

LY C

URRE

NT (m

A)


SUPPLY CURRENTvs. RXCLKIN FREQUENCY (BWS = OPEN)

toc05

PRBS ON,COAX MODE,

PE OFF,HDCP OFF

ALL SPREAD VALUES


Maxim Integrated │ 15www.maximintegrated.com

Typical Operating Characteristics

(VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C, unless otherwise noted.)

120

130

140

150

160

170

180

5 20 35 50 65 80

SUPP

LY C

URRE

NT (m

A)


SUPPLY CURRENTvs. RXCLKIN FREQUENCY (BWS = HIGH)

toc06

PRBS ON,COAX MODE,

PE OFF,HDCP OFF

ALL SPREAD VALUES

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

31 31.5 32 32.5 33 33.5 34 34.5 35 35.5OU

TPUT

POW

ER (d

Bm)


OUTPUT SPECTURMvs. RXCLKIN FREQUENCY

(VARIOUS SPREAD)toc07

2% SPREAD

0% SPREAD

1% SPREAD

0.5% SPREAD

4% SPREAD

fPCLKIN = 33.3MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

62 63 64 65 66 67 68 69 70 71

OUTP

UT P

OWER

(dBm

)


OUTPUT SPECTURMvs. RXCLKIN FREQUENCY

(VARIOUS SPREAD)toc08

2% SPREAD

0% SPREAD

1% SPREAD

0.5% SPREAD

4% SPREAD

fPCLKIN = 66.6MHz

0

20

40

60

80

100

120

0 5 10 15 20 25

RXCL

KIN

FREQ

UENC

Y (M

Hz)

CABLE LENGTH (m)

MAXIMUM RXCLKIN FREQUENCYvs. COAX CABLE LENGTH (BER ≤ 10-10)

toc09

BER CAN BE AS LOW AS 10-12 FOR CABLE LENGTHS LESS THAN 15m

OPTIMUM PE/EQ

NO PE, 10.7dB EQ

NO PE/EQ


Maxim Integrated │ 16www.maximintegrated.com

Typical Operating Characteristics (continued)

TOP VIEW

MAX9277MAX9281

TQFN(7mm x 7mm x 0.75mm)

13

14

15

16

17

18

19

20

21

22

23

24

AGND

+ LVDSVDDAVDD

SD

SCK

WS

CNTL1

CNTL2

AGND

DVDD

GND

IOVDD

48

47

46

45

44

43

42

41

40

39

38

37

1 2 3 4 5 6 7 8 9 10 11 12

CX/TP

*CONNECT EP TO GROUND PLANE

AVDD*EP

ADD1

AUTOS

MS/CNTL0

CDS/CNTL3

PWDN

BWS

ADD0

DVDD

GND

IOVDD

RXIN

3+

RXIN

3-

RXCL

KIN+

RXCL

KIN-

RXIN

2+

RXIN

2-

AGND

LVDS

VDD

RXIN

1+

RXIN

1-

RXIN

0+

RXIN

0-

36 35 34 33 32 31 30 29 28 27 26 25

RX/S

DA

TX/S

CL

CONF

1

LMN1

AGND

OUT-

OUT+

AVDD

LMN0

LFLT

GPO/

HIM

CONF

0

PIN NAME FUNCTION

1–4, 7, 8, 11, 12

RXIN_-, RXIN_+

LVDS Data Inputs. Set BWS = low to use RXIN0_ to RXIN2_ (3-channel mode). Set BWS = high or open to use RXIN0_ to RXIN3_ (4-channel or high-bandwidth mode). Certain data bits encrypted when HDCP is enabled (MAX9281 only, Table 3)

5, 14 LVDSVDD 3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1µF and 0.001µF capacitors as close as possible to the device with the smallest value capacitor closest to LVDSVDD.

6, 13, 21, 29 AGND Analog and LVDS Ground

9, 10 RXLKIN-, RXCLKIN+ LVDS Clock Input. Provides the PLL reference clock.

15, 32, 47 AVDD 1.8V Analog Power Supply. Bypass AGND to EP with 0.1µF and 0.001µF capacitors as close as possible to the device with the smaller capacitor closest to AVDD.

16 SDI2S/TDM Serial-Data Input with Internal Pulldown to GND. Disable I2S/TDM encoding to use SD as an additional control/data input latched on the selected edge of PCLKIN. Encrypted when HDCP is enabled.

17 SCK I2S/TDM Serial-Clock Input with Internal Pulldown to GND



Pin Description

Pin Configuration

PIN NAME FUNCTION

18 WS I2S/TDM Word-Select Input with Internal Pulldown to GND

19 CNTL1

Control Input With Internal Pulldown to GND. Input data is latched every RXCLKIN_ cycle (Figure 15). CNTL1 is not available in 3-channel mode (BWS = low). Set BWS = high or open (4-channel or high-bandwidth mode) to use this input. CNTL1 not encrypted when HDCP is on (MAX9281 only) CNTL1 or RES (“Reserved” from VESA Standard Panel Specification) is mapped to internal bit DIN27. See the Reserved Bit (RES)/CNTL1 section.

20 CNTL2

Control Input With Internal Pulldown to GND. Input data is latched every RXCLKIN_ cycle (Figure 15). CNTL2 is not available in 3-channel mode (BWS = low). Set BWS = high or open (4-channel or high-bandwidth mode) to use this input. CNTL2 not encrypted when HDCP is on (MAX9281 only). CNTL2 is mapped to internal bit DIN28.

22, 39 DVDD 1.8V Digital Power Supply. Bypass DVDD to GND with 0.1µF and 0.001µF capacitors as close as possible to the device with the smaller value capacitor closest to DVDD.

23, 38 GND Digital and I/O Ground

24, 37 IOVDDI/O Supply Voltage. 1.8V to 3.3V logic I/O Power Supply. Bypass IOVDD to GND with 0.1µF and 0.001µF capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD. IOVDD sets the voltage levels for all pins except for the LVDS inputs and OUT+/-

25 RX/SDA

UART Receive/I2C Serial Data Input/Output with Internal 30kΩ Pullup to IOVDD. Function is determined by the state of CONF[1:0] at power-up (Table 11). RX/SDA has an open-drain driver and requires a pullup resistor.RX: Input of the serializer’s UART.SDA: Data input/output of the serializer’s I2C Master/Slave.

26 TX/SCL

UART Transmit/I2C Serial Clock Input/Output with Internal 30kΩ Pullup to IOVDD. Function is determined by the state of CONF[1:0] at power-up (Table 11). TX/SCL has an open-drain driver and requires a pullup resistor.TX: Output of the serializer’s UART.SCL: Clock input/output of the serializer’s I2C Master/Slave.

27 CONF1 Three-Level Configuration Input. The state of CONF1 latches at power-up or when resuming from power-down mode (PWDN = low). See Table 11 for details.

28 LMN1 Line-Fault Monitor Input 1 (see Figure 4 for details).

30 OUT- Inverting CML Coax/Twisted-Pair Serial Output

31 OUT+ Noninverting CML Coax/Twisted-Pair Serial Output

33 LMN0 Line-Fault Monitor Input 0 (see Figure 4 for details).

34 LFLT Active-Low Open-Drain Line-Fault Output. LFLT has a 60kΩ internal pullup to IOVDD. LFLT = low indicates a line fault. LFLT is output high when PWDN = low.

35 GPO/HIM

General-Purpose Output/High Immunity Mode Input.Functions as HIM input with internal pulldown to GND at power-up or when resuming from power-down mode (PWDN = low), and switches to GPO output automatically after power-up.HIM: Default HIGHIMM bit value is latched at power-up or when resuming from power-down mode (PWDN = low) and is active-high. Connect HIM to IOVDD with a 30kΩ resistor to set high or leave open to set low. HIGHIMM can be programmed to a different value after power-up. HIGHIMM in the deserializer must be set to the same value.GPO: Output follows the state of the GPI (or INT) input on the deserializer. GPO is low after power-up or when PWDN is low.



Pin Description (continued)

PIN NAME FUNCTION

36 CONF0 Three-Level Configuration Input. The state of CONF0 latches at power-up or when resuming from power-down mode (PWDN = low). See Table 11 for details.

40 ADD0 Three-Level Address Selection Input. The state of ADD0 latches at power-up or when resuming from power-down mode (PWDN = low). See Table 2 for details.

41 BWSThree-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial link. Set BWS = low for 3-channel mode. Set BWS = high for 4-channel mode. Set BWS = open for high-bandwidth mode.

42 PWDN Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter power-down mode to reduce power consumption.

43 CDS/CNTL3

Control Direction Selection/Auxiliary Control Signal Input with Internal Pulldown to GND. Function is determined by the CDSCNTL3 register bit and defaults to CDS on power-up.CDS (CDSCNTL3 = 0): Control link direction selection input with internal pulldown to GND. Set CDS = low when the control channel master µC is connected at the serializer. Set CDS = high when the control channel master µC is connected at the deserializer.CNTL3 (CDSCNTL3 = 1): Used only in high-bandwidth mode (BWS = open). CNTL3 not encrypted when HDCP is enabled (MAX9281 only).

44 MS/CNTL0

Mode Select/Auxiliary Control Signal Input with Internal Pulldown to GND. Function is determined by the MSCNTL0 register bit and defaults to MS on power-up.MS (MSCNTL0 = 0): Set MS = low, to select base mode. Set MS = high to select the bypass mode.CNTL0 (MSCNTL0 = 1): Used only in high-bandwidth mode (BWS = open). CNTL0 not encrypted when HDCP is enabled (MAX9281 only).

45 AUTOS

Active-Low Auto-Start Input With Internal Pulldown to GND. Set AUTOS = high, to disable serialization at power-up or when resuming from power-down mode (PWDN = low). Set AUTOS = low, to enable serialization and automatic PLL range selection power-up or when resuming from power-down mode.

46 ADD1 Three-Level Address Selection Input. The state of ADD1 latches at power-up or when resuming from power-down mode (PWDN = low). See Table 2 for details.

48 CX/TP Coax/Twisted Pair Input With Internal Pulldown to GND. Set CX/TP low for twisted-pair cable drive (differential output). Set CX/TP high for coax cable drive (single-ended output).

— EP Exposed Pad. EP is internally connected to AGND. MUST connect EP to the PCB ground plane through an array of vias for proper thermal and electrical performance.



Pin Description (continued)

SCRAMBLE /PARITY/8b/10b/9b/10b/

ENCODE

LVDS TOPARALLEL

CNTL1 (4-CH)

CNTL1 (9b10b)

PARALLELTO

SERIAL

MAX9277MAX9281

REVERSECONTROLCHANNEL

HDCPDECRYPT

(MAX9281ONLY)

HDCPDECRYPT

CONTROLMS, CDS

UART/I2C

GPO/HIMSD SCK WS TX /SCL RX/SDA AUTOSBWS CONF[3:0] ADD[1:0]

HDCPKEYS

RGB

HSVSDE

HSVSDE

ACB

CNTL[3:0](9b10b)

DIN[28:27](30-BIT)

FCC

HDCPCONTROL

AUDIO

FIFO

7x PLL

CONTROL(9b10b)

SYNC

VIDEO

CLKDIV

SSPLL

RES/CNTL1(4-CH)

CNTL0/MS,CNTL3/CDS

CNTL2

CNTL1

RXIN3 (4CH)

RXIN2

RXIN1

RXIN0

RXCLKIN

RGB[23:18](4 CH OR 9b10b)

RGB[17:0]

CML TX

LMN1

LMN0

LFLT

OUT+

CX/TP

OUT-

RX

PWDN

FILTERPLL LINE

FAULTDETECT

CNTL2 (4-CH)

CNTL2 (9b10b)

CNTL0 CNTL3 (9b10b)

MS, CDS



Functional Diagram

Figure 1. Serial-Output Parameters

Figure 2. Output Waveforms at OUT+, OUT-

Figure 3. Single-Ended Output Template

OUT-

VOD

VOS

GND

RL/2

RL/2

OUT+

OUT-

OUT+

(OUT+) - (OUT-)

VOS(-) VOS(+)

((OUT+) + (OUT-))/2

VOS(-)

VOD(-)VOD(-)

VOD = 0V

DVOS = |VOS(+) - VOS(-)|

DVOD = |VOD(+) - VOD(-)|

VOD(+)

OUT+

OUT-

VOS VOD(P) VOD(D)

SERIAL-BITTIME

OUT+OR

OUT-

VO/2 VO/2VO VO



Figure 4. Line Fault Detector Circuit

Figure 5. Worst-Case Pattern Input

OUTPUTLOGIC(OUT+)

LFLT REFERENCEVOLTAGE

GENERATOR

CONNECTORS

*±1% TOLERANCE

LEAVE UNUSED LINE FAULTINPUT UNCONNECTED

OUTPUTLOGIC(OUT-)

GMSLSERIALIZER

GMSLSERIALIZER

45.3kΩ*

LMN1

LMN1

LMN0

LMN0

45.3kΩ*

1.8V

4.99kΩ*

49.9kΩ* 49.9kΩ*

4.99kΩ*

TWISTED PAIR

COAX

OUT+

OUT-

CONNECTORS

GMSLSERIALIZER

45.3kΩ*LMN0

49.9Ω*

1.5V

4.99kΩ*

49.9kΩ*

OUT+

OUT-

RXCLKIN+

RXCLKIN-

RXIN0+ TO RXIN3+

RXIN0- TO RXIN3-

CNTL_



Figure 6. I2C Timing Parameters

Figure 7. Differential Output Template

Figure 8. Input Setup and Hold Times

PROTOCOL

SCL

SDA

STARTCONDITION

(S)

BIT 7MSB(A7)

BIT 6(A6)

BIT 0(R/W)

ACKNOWLEDGE(A)

STOPCONDITION

(P)

tSU;STA

VIOVDD x 0.7

VIOVDD x 0.7

VIOVDD x 0.3

VIOVDD x 0.3

tLOW tHIGH

tBUF

tHD;STA

trtSP

tf

tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO

1/fSCL

800mVP-P

tTSOJ12

tTSOJ12

RXIN_+/RXIN_-

RXCLKIN+

CNTL_

RXCLKIN-

tSET tHOLDVIHMIN

VILMAX



Figure 9. LVDS Receiver Input Skew Margin

Figure 12. Link Startup Time

Figure 10. GPI-to-GPO Delay

Figure 11. Serializer Delay

MIN MAXINTERNAL STROBE

IDEAL

tRSKM tRSKM

IDEAL SERIAL-BIT TIME

RXCLKIN-

SERIAL LINK INACTIVE SERIAL LINK ACTIVE

CHANNELDISABLED

REVERSE CONTROLCHANNEL ENABLED


PWDN MUST BE HIGH

RXCLKIN+

tLOCK

500µs

tGPIO tGPIO

VOH_MIN

VOL_MAX

VIH_MIN

VIL_MAX

DESERIALIZERGPI

SERIALIZERGPO

N-1 N

FIRST BIT LAST BIT

N N+1N-1 N+2 N+3

RXCLKIN+

RXCLKIN-

OUT+/OUT-

RXIN_+/RXIN_-

EXPANDED TIME SCALE

tSD



Figure 13. Power-Up Delay

Figure 14. Input I2S Timing Parameters

500µs

POWERED DOWN POWERED UP, SERIALLINK INACTIVE POWERED UP, SERIAL LINK ACTIVE

tPU

VIH1

REVERSE CONTROLCHANNEL DISABLED


REVERSE CONTROLCHANNEL DISABLED


PWDN

RXCLKIN+

RXCLKIN-

WS

tHOLD tSET

tHOLD tSET tHC

tSCK

tLC

SCK

SD/CNTL0



Detailed DescriptionThe MAX9277/MAX9281 serializers, when paired with the MAX9276/MAX9280 deserializers, provides the full set of operating features, but is backward compatible with the MAX9249–MAX9270 family of Gigabit Multimedia Serial Link (GMSL) devices, and have basic functionality when paired with any GMSL device. The MAX9281 has High-bandwidth Digital Content Protection (HDCP) while the MAX9277 does not.The serializer has a maximum serial-bit rate of 3.12Gbps for up to 15m of cable and operates up to a maximum output clock of 104MHz in 24-bit, 3-channel mode and 27-bit high-bandwidth mode, or 78MHz in 32-bit, 4-chan-nel mode. This bit rate and output flexibility support a wide range of displays, from QVGA (320 x 240) to 1920 x 720 and higher with 24-bit color, as well as megapixel image sensors. An encoded audio channel supports L-PCM I2S stereo and up to eight channels of L-PCM in TDM mode. Sample rates of 32kHz to 192kHz are supported with sample depth from 8 to 32 bits. Output pre/deemphasis, combined with GMSL deserializer equalization, extends the cable length and enhances link reliability.The control channel enables a µC to program the serial-izer and deserializer registers and program registers on

peripherals. The control channel is also used to perform HDCP functions (MAX9281 only). The µC can be located at either end of the link, or when using two µCs, at both ends. Two modes of control-channel operation are availa-ble. Base mode uses either I2C or GMSL UART protocol, while bypass mode uses a user-defined UART protocol. UART protocol allows full-duplex communication, while I2C allows half-duplex communication.Spread spectrum is available to reduce EMI on the serial output. The serial output and LVDS input complies with ISO 10605 and IEC 61000-4-2 ESD protection standards.

Register MappingRegisters set the operating conditions of the serializers and are programmed using the control channel in base mode. The MAX9277/MAX9281 holds its own device address and the device address of the deserializer with which it is paired. Similarly, the deserializer holds its own device address and the address of the MAX9277/MAX9281. Whenever a device address is changed be sure to write the new address to both devices. The default device address of the serializer is set by the ADD[1:0] (see Table 1 and Table 2). Registers 0x00 and 0x01 in both devices hold the device addresses.

Table 1. Power-Up Default Register Map (see Table 25 and Table 26)REGISTER ADDRESS

(hex)

POWER-UP DEFAULT(hex)

POWER-UP DEFAULT SETTINGS(MSB FIRST)

0x000x40, 0x44, 0x48, 0x80, 0x84, 0x88, 0xC0, 0xC4, 0xC8

SERID = XX00XX0, serializer device address is determined by ADD0 and ADD1 (Table 2)CFGBLOCK = 0, registers 0x00 to 0x1F are read/write

0x010x50, 0x54, 0x58, 0x90, 0x94, 0x98, 0xD0, 0xD4, 0xD8

DESID = XX01XX0, deserializer device address is determined by ADD0 and ADD1 (Table 2)RESERVED = 0

0x02 0x1F, 0x3F

SS = 00X spread-spectrum settings depend on CONF[1:0] pin states at power-upAUDIOEN = 1 I2S/TDM channel enabledPRNG = 11, automatically detect the pixel clock rangeSRNG = 11, automatically detect serial data rate

0x03 0x00 AUTOFM = 00, calibrate spread modulation rate only once after lockingSDIV = 000000, auto calibrate sawtooth divider



Table 1. Power-Up Default Register Map (see Table 25 and Table 26) (continued)REGISTER ADDRESS

(hex)



0x04 0x07, 0x17, 0x87, 0x97

SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default depends on AUTOS pin state at power-upCLINKEN = 0, configuration link disabledPRBSEN = 0, PRBS test disabledSLEEP = 0 or 1, sleep mode state depends on CDS/CNTL3 and AUTOS pin state at power-up (see the Link Startup Procedure section)INTTYPE = 01, local control channel uses UART when I2CSEL = 0, CDS = 1, MS = 0REVCCEN = 1, reverse control channel active (receiving)FWDCCEN = 1, forward control channel active (sending)

0x05 0x70

I2CMETHOD = 0, I2C packets include register addressDISJITFILT = 1, jitter filter disabledCMLLVL = 11, 400mV CML twisted pair output levelPREEMP = 0000, pre-emphasis disabled

0x06 0x40 RESERVED = 01000000

0x07 0x22 RESERVED = 00100010

0x08 0x0A(Read only)

RESERVED = 0000LFNEG = 10 no faults detectedLFPOS = 10 no faults detected

0x09 0xXX(Read only) RESERVED = XXXXXXXX

0x0A 0xXX(Read only) RESERVED = XXXXXXXX

0x0B 0xXX(Read only) RESERVED = XXXXXXXX

0x0C 0x20 X7PLLHIBW = 0, normal X7PLL bandwidthRESERVED = 0100000

0x0D 0x0F

SETGPO = 0, GPO set to LowINVVSYNC = 0, serializer does not invert VSYNCINVHSYNC = 0, serializer does not invert HSYNCDISRES = 0, RES transmitted to deserializerSKEWADJ = 1111 No X7PLL clock skew adjust

0x0E 0x00 INVDE = 0, serializer does not invert DERESERVED = 0000000

0x0F 0x00 I2CSCRA = 0000000, I2C address translator source A is 0x00

RESERVED = 0

0x10 0x00 I2CDSTA = 0000000, I2C address translator destination A is 0x00

RESERVED = 0

0x11 0x00 I2CSCRB = 0000000, I2C address translator source B is 0x00

RESERVED = 0

0x12 0x00 I2CDSTB = 0000000, I2C address translator destination B is 0x00

RESERVED = 0




(hex)



0x13 0xB6

I2CLOCACK = 0 acknowledge not generated when forward channel is not availableI2CSLVSH = 01, 469ns/234ns I2C setup/hold timeI2CMSTBT = 101, 339kbps (typ) I2C to I2C-master bit rate settingI2CSLVTO = 10, 1024µs (typ) I2C to I2C-slave remote timeout

0x14 0xA0CMLLVLCX = 1010, 500mV CML coax output levelRESERVED = 000DISRWAKE = 0, wakeup receiver enabled

0x15 0x50

DISDETRIG = 0, DE trigger enabled in high bandwidth modeCNTLTRIG = 10, CNTL triggered when DE is low (high bandwidth mode)ENREVP = 1, positive input reverse-channel receiver enabledENREVN = 0, negative input reverse-channel receiver disabledRESERVED = 000

0x16 0xXX RESERVED = XXXXXXXX

0x17 0x1F, 0x9FHIGHIMM = 0 (GPO/HIM = 0) HIGHIMM = 1 (GPO/HIM = 1), reverse-channel immunity mode default depends on GPO/HIM pin state at power-upRESERVED = 0011111

0x18 0xXX (read only) RESERVED = XXXXXXXX

0x19 0x4A RESERVED = 01001010

0x1A 0x00

REVFAST = 0, High-immunity mode uses 500kbps bit rateRESERVED = 0MSCNTL0 = 0, normal MS functionalityCDSCNTL3 = 0, normal CDS functionalityRESERVED = 000REVARBTO = 0, 256µs reverse-channel arbitration time out (coax splitter mode only)

0x1B 0x00INVSCK = 0, SCK input not invertedINVWS = 0, WS input not invertedRESERVED = 000000

0x1E 0x2X(read only) ID = 00100011 (MAX9277) or ID = 00100111 (MAX9281)

0x1F 0x0X(read only)

RESERVED = 000CAPS = 0 (MAX9277) or 1 (MAX9281), Only MAX9281 is HDCP capableREVISION = XXXX, Revision number

0x80 to 0x84 0x0000000000 BKSV = 0x0000000000, HDCP receiver KSV is 0x0000000000

0x85 to 0x86 0x0000 RI = 0x0000, RI of the transmitter is 0x0000

0x87 0x00 PJ = 0x00, PJ of the transmitter is 0x00

0x88 to 0x8F 0x0000000000000000(Read only) AN = 0000000000000000, Session random number (read only)

0x90 to 0x94 0xXXXXXXXXXX(Read only)AKSV = 0xXXXXXXXXXXXXXXXX, HDCP transmitter KSV is 0xXXXXXXXXXX (read only)



X = Indeterminate.


(hex)



0x95 0x00

PD_HDCP = 0, HDCP circuits powered upEN_INT_COMP = 0, internal link verification disabledFORCE_AUDIO = 0, normal I2S audio operationFORCE_VIDEO = 0, normal video link operationRESET_HDCP = 0 normal HDCP operationSTART_AUTHENTICATION = 0 HDCP authentication not startedVSYNC_DET = 0 VSYNC rising edge not detectedENCRYPTION_ENABLE = 0 HDCP encryption disabled

0x96 0x01(Read only)

RESERVED = 0000V_MATCHED = 0, SHA-1 hash value not matchedPJ_MATCHED = 0, enhanced link verification response not matchedR0_RI_MATCHED = 0, link verification response not matchedBKSV_INVALID = 1, invalid receiver KSV

0x97 0x00 RESERVED = 0000000REPEATER = 0, HDCP receiver is not a repeater

0x98 to 0x9C 0x0000000000 ASEED = 0x0000000000 Optional RNG seed value is 0x0000000000

0x9D to 0x9F 0x000000 DFORCE = 0x000000, video data forced to 0x000000 when FORCE_VIDEO = 1

0xA0 to 0xA3 0x00000000 H0 part of SHA-1 hash value is 0x00000000

0xA4 to 0xA7 0x00000000 H1 part of SHA-1 hash value is 0x00000000

0xA8 to 0xAB 0x00000000 H2 part of SHA-1 hash value is 0x00000000

0xAC to 0xAF 0x00000000 H3 part of SHA-1 hash value is 0x00000000

0xB0 to 0xB3 0x00000000 H4 part of SHA-1 hash value is 0x00000000

0xB4 0x00Reserved = 0000MAX_CASCADE_EXCEEDED = 0, Less than 7 cascaded HDCP devices attachedDEPTH = 000, device cascade depth is zero

0xB5 0x00 MAX_DEVS_EXCEEDED = 0, Less than 127 HDCP devices attachedDEVICE_COUNT = 0000000, zero attached devices

0xB6 0x00 GPMEM = 00000000, 0x00 stored in general-purpose memory

0xB7 to 0xB9 0x000000 Reserved = 0x000000

0xBA to 0xFF All zero KSV_LIST = all zero, no KSVs stored



Input Bit MapThe input bit width depends on settings of the bus width (BWS) pin. Table 3 lists the bit map.

Table 2. Device Address Defaults (Register 0x00, 0x01)

Table 3. Input Map (See Figure 15, Figure 16)

*X = 0 for the serializer address, X = 1 for the deserializer address.

*See the High-Bandwidth Mode section for details on timing requirements.**Not encrypted when HDCP is enabled (MAX9281 only).

PIN DEVICE ADDRESS(bin)SERIALIZER

DEVICEADDRESS

(hex)

DESERIALIZERDEVICE

ADDRESS(hex)ADD1 ADD0 D7 D6 D5 D4 D3 D2 D1 D0

Low Low 1 0 0 X* 0 0 0 R/W 80 90

Low High 1 0 0 X* 0 1 0 R/W 84 94

Low Open 1 0 0 X* 1 0 0 R/W 88 98

High Low 1 1 0 X* 0 0 0 R/W C0 D0

High High 1 1 0 X* 0 1 0 R/W C4 D4

High Open 1 1 0 X* 1 0 0 R/W C8 D8

Open Low 0 1 0 X* 0 0 0 R/W 40 50

Open High 0 1 0 X* 0 1 0 R/W 44 54

Open Open 0 1 0 X* 1 0 0 R/W 48 58

MODE3-CHANNEL MODE

(BWS = LOW)

HIGH-BANDWIDTH MODE

(BWS = MID)

4-CHANNEL MODE(BWS = HIGH)SIGNAL INPUT PIN/BIT POSITION

R[5:0] DIN[5:0] Used Used Used

G[5:0] DIN [11:6] Used Used Used

B[5:0] DIN [17:12] Used Used Used

HS, VS, DE DIN18/HS, DIN19/VS, DIN20/DE Used** Used** Used**

R[7:6] DIN [22:21] Not used Used Used

G[7:6] DIN [24:23] Not used Used Used

B[7:6] DIN [26:25] Not used Used Used

RES, CNTL[2:1] RES, CNTL[2:1] Not used Used*,** Used**

CNTL3, CNTL0 CDS/CNTL3, MS/CNTL0 Not used Used*,** Not used

I2S/TDMWS, SCK, SD

Used Used Used

AUX SIGNAL Used Used Used



Figure 15. LVDS Input Timing

Figure 16. LVDS Clock and Bit Assignment

DIN1 DIN0 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0




CYCLE NCYCLE N-1

RXIN0+/RXIN0-

RXCLKIN+

RXIN1+/RXIN1-

RXIN2+/RXIN2-

RXIN3+/RXIN3-*

RXCLKIN-

CNTL1*

CNTL2*

SD SD

CNTL0

CNTL3

CNTL0**

CNTL3**

CNTL1/DIN27

CNTL2/DIN28

**CNTL0, CNTL3 ONLY USED IN HIGH-BANDWIDTH MODES*RXIN3+/-, CNTL1, CNTL2 ONLY USED IN 32-BIT AND HIGH-BANDWIDTH MODES

R1(R3)

R0(R2)

G0(G2)

R5(R7)

R4(R6)

R3(R5)

R2(R4)

R1(R3)

R0(R2)

G2(G4)

G1(G3)

B1(B3)

B0(R2)

G5(G7)

G4(G6)

G3(G5)

G2(G4)

G1(G3)

B3(B5)

B2(B4) DE VS

RES

HS B5(B7)B4

(B6)B3

(B5)B2

(B4)

R7(R1)

R6(R0)

B7(B1)

B6(B0)

G7(G1)

G6(G0)

R7(R1)

R6(R0)

CYCLE N-1 CYCLE N

RXIN0+/RXIN0- VESA(oLDI)

VESA(oLDI)

VESA(oLDI)

VESA(oLDI)

RXCLKIN+

RXCLKIN-

RXIN1+/RXIN1-

RXIN2+/RXIN2-

RXIN3+/RXIN3-



Serial Link Signaling and Data FormatThe serializer uses differential CML signaling to drive twist-ed-pair cable and single-ended CML to drive coaxial cable with programmable pre/deemphasis and AC-coupling. The deserializer uses AC-coupling and programmable channel equalization.Input data is scrambled and then 8b/10b coded (9b10b in high-bandwidth mode). The deserializer recovers the

embedded serial clock, then samples, decodes, and descrambles the data. In 3-channel mode, the first 21 bits contain video data. In 4-channel mode, the first 29 bits contain video data. In high-bandwidth mode, the first 24 bits contain video data, or special control signal packets. The last 3 bits contain the embedded audio channel, the embedded forward control channel, the parity bit of the serial word (see Figure 17 and Figure 18).

Figure 17. 3-Channel Mode Serial Data Format

Figure 18. 4-Channel Mode Serial Data Format

24 BITS

PACKETPARITY

CHECK BIT

ACB FCC PCBD0 D1

R0 R1 B5 HS VS DE

D20D19D18D17

MAX9281 NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY. ONLY DIN[17:0] AND ACB HAVE HDCP ENCRYPTION.

RGB DATA CONTROL BITS

DIN0 DIN1 DIN17 DIN18/HSDIN19/

VSDIN20/

DE

SERIAL DATA

INPUT PIN

INPUT SIGNAL

WS SCK SD RX/SDATX/SCL

AUDIO ENCODE

I2S/TDM AUDIO UART/I2C

FORWARDCONTROL

CHANNEL BIT

D23

32 BITS

PACKETPARITY

CHECK BIT

D24 D25 D26 D27 D28 ACB FCC PCB

R6 R7

D0 D1

R0 R1 B5 HS VS DE

D22D21D20D19D18

G6 G7 B6 B7

D17

RGB DATA CONTROL BITS RGB DATA

AUXCONTROL

BITS


VSDIN20/

DE DIN21 DIN22 DIN23 DIN24 DIN25 DIN26DIN27/CNTL1

DIN28/CNTL2

SERIAL DATA

INPUT PIN

INPUT SIGNAL


AUDIO ENCODE

I2S/ TDMAUDIO UART/ I2C

FORWARDCONTROL

CHANNEL BIT

MAX9281 NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY. ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.



Reserved Bit (RES)/CNTL1In 4-channel mode, the serializer by default serializes RES to serial data bit 27. Set DISRES (D4 of register 0x0D) = 1 to map CNTL1 to serial data bit 27.

Data-Rate SelectionThe serializer uses the DRS bit, and BWS input to set the RXCLKIN_ frequency range (Table 4). Set DRS = 1 for low data rate RXCLKIN_ frequency range of 6.25MHz to 16.66MHz. Set DRS = 0 for high data rate RXCLKIN_ frequency range of 12.5MHz to 104MHz.

High-Bandwidth ModeThe serializer uses a 27-bit high-bandwidth mode to support 24-Bit RGB at 104MHz pixel clock. Set BWS = open in both the serializer and deserializer to use high-bandwidth mode. In high-bandwidth mode, the serializer encodes HS, VS, DE and CNTL[3:0] to special packets.

Packets are sent by replacing a pixel before the rising edge and after the falling edge of HS, VS, DE signals. However, for CNTL[3:0], packets always replace a pixel before the transition of CNTL[3:0]. Keep HS, VS, and DE low pulse widths at least 2 pixel clock cycles. By default, CNTL[3:0] are sampled continuously when DE is low. CNTL[3:0] are sampled only on HS/VS transitions when DE is high . If DE triggering of encoded packets is not desired, set the serializer’s DISDETRIG = 0 and the CNTLTRIG bits to their desired value (register 0x15) to change the CNTL triggering behavior. Set DETREN = 0 on the deserializer when DE is not periodic.

Audio ChannelThe audio channel supports 8kHz to 192kHz audio sam-pling rates and audio word lengths from 8 bits to 32 bits (2 channel I2S) or 64 to 256 bits (TDM64 to TDM256). The audio bit clock (SCK) does not have to be syn-chronized with RXCLKIN_. The serializer automatically encodes audio data into a single bit stream synchronous with RXCLKIN_. The deserializer decodes the audio stream and stores audio words in a FIFO. Audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in I2S format. The audio channel is enabled by default. When the audio channel is disabled, the SD is treated as an auxiliary control signal.Since the encoded audio data sent through the serial link is synchronized with RXCLKIN_ (through ACB), low RXCLKIN_ frequencies limit the maximum audio sam-pling rate. Table 5 lists the maximum audio sampling rate for various RXCLKIN_ frequencies. Spread-spectrum settings do not affect the I2S/TDM data rate or WS clock frequency.

Figure 19. High-Bandwidth Mode Serial Data Format

Table 4. Data-Rate Selection Table

D23

27 BITS

PACKETPARITY

CHECK BIT

ACB FCC PCB

R6 R7

D0 D1

R0 R1 B5 HS VS DE

D22D21D20D19D18

G6 G7 B6 B7

D17

RGB DATA CONTROL BITSRGB DATA AUX CONTROL


VSDIN20/

DEDIN21 DIN22 DIN23 DIN24 DIN25 DIN26DIN27/CNTL1

DIN28/CNTL2

SERIAL DATA

INPUT PIN

INPUT SIGNAL


AUDIO ENCODE

I2S/TDM AUDIO UART/I2C

FORWARDCONTROL

CHANNEL BITCONTROL SIGNAL ENCODING

CDS/CNTL3

MS/CNTL0

27 BITS

SPECIAL SERIAL DATA PACKET

MAX9281 NOTE: VS/HS MUST BE SET AT DIN[20:18]. ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.

DRS BIT SETTING

BWS PIN SETTING

RXCLKIN_ RANGE (MHz)

0 (high data rate)

Low (3-channel mode) 16.66 to 104

Mid (high bandwidth mode) 36.66 to 104

High (4-channel mode) 12.5 to 78

1 (low data rate)

Low 8.33 to 16.66

Mid 18.33 to 36.66

High 6.25 to 12.5



Table 5. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies

+ Max WS rate is greater than 192kHz.*DRS = 0 RXCLKIN_ frequency is equal to 2x the DRS = 1 RXCLKIN_ frequency.

CH

AN

NEL

S BITS PER CHAN

RXCLKIN_ FREQUENCY(DRS = 0*)(MHz)

12.5 15.0 16.6 20.0 25.0 30.0 35.0 40.0 45.0 50.0 100

2

8 + + + + + + + + + + +

16 + + + + + + + + + + +

18 185.5 + + + + + + + + + +

20 174.6 + + + + + + + + + +

24 152.2 182.7 + + + + + + + + +

32 123.7 148.4 164.3 + + + + + + + +

4

8 + + + + + + + + + + +

16 123.7 148.4 164.3 + + + + + + + +

18 112.0 134.4 148.8 179.2 + + + + + + +

20 104.2 125.0 138.3 166.7 + + + + + + +

24 88.6 106.3 117.7 141.8 177.2 + + + + + +

32 69.9 83.8 92.8 111.8 139.7 167.6 + + + + +

6

8 152.2 182.7 + + + + + + + + +

16 88.6 106.3 117.7 141.8 177.2 + + + + + +

18 80.2 93.3 106.6 128.4 160.5 + + + + + +

20 73.3 88.0 97.3 117.3 146.6 175.9 + + + + +

24 62.5 75.0 83.0 100 125 150 175 + + + +

32 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + +

8

8 123.7 148.4 164.3 + + + + + + + +

16 69.9 83.8 92.8 111.8 139.7 167.6 + + + + +

18 62.5 75.0 83.0 100.0 125.0 150.0 175.0 + + + +

20 57.1 68.5 75.8 91.3 114.2 137.0 159.9 182.7 + + +

24 48.3 57.9 64.1 77.2 96.5 115.9 135.2 154.5 173.8 + +

32 37.1 44.5 49.3 59.4 74.2 89.1 103.9 118.8 133.6 148.4 +

COLOR CODING

192kHz



Audio Channel InputThe audio channel input works with 8-channel TDM and stereo I2S, as well as non-standard formats. The input format is shown in Figure 20.The period of the WS can be 8 to 256 SCK periods. The WS frame starts with the falling edge and can be low for 1 to 255 SCK periods. SD is one SCK period, sampled on the rising edge. MSB/LSB order, zero padding or any other significance assigned to the serial data does not affect operation of the audio channel. The polarity for WS and SCK edges is programmable.The following are examples of acceptable input formats:

Figure 21. 8-Channel TDM (24-Bit Samples, Padded with Zeros)

Figure 22. 6-Channel TDM (24-Bit Samples, No Padding)

Figure 20. Audio Channel Input Format

WS

SCK

SD

256 SCK

CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8

MSB 24-BIT DATALSB 8 BITS ZERO

32 SCK

WS

SCK

SD

SCK 144

24-BIT DATA

CH1 CH2 CH3 CH4 CH5 CH6

24 SCK

WS

SCK

SD

FRAME

0 1 2 N

16 TO 256 BITS



Reverse Control ChannelThe serializer uses the reverse control channel to receive I2C/UART and GPO signals from the deserializer in the opposite direction of the video stream. The reverse control channel and forward video data coexist on the same serial cable forming a bidirectional link. The reverse

control channel operates independently from the forward control channel. The reverse control channel is available 2ms after power-up. The serializer temporarily disables the reverse control channel for 500µs after starting/stop-ping the forward serial link.

Figure 23. Stereo I2S (24-Bit Samples, Padded with Zeros)

Figure 24. Stereo I2S (16-Bit Samples, No Padding)

32 SCK

WS

SCK

SD

64 SCK

LEFT CHANNEL

MSB 24-BIT DATALSB 8 BITS ZERO

RIGHT CHANNEL

WS

SCK

SD

32 SCK

LEFT CHANNEL

16-BIT DATA

RIGHT CHANNEL

16 SCK



Control Channel and Register ProgrammingThe control channel is available for the µC to send and receive control data over the serial link simultaneously with the high-speed data. The µC controls the link from either the serializer or the deserializer side to support video-display or image-sensing applications. The control channel between the µC and serializer or deserializer runs in base mode or bypass mode according to the mode selection (MS) input of the device connected to the µC. Base mode is a half-duplex control channel and the bypass mode is a full-duplex control channel. The total maximum forward or reverse control channel delay is 2Fs (UART) or 2 bit times (I2C) from the input of one device to the output of the other. I2C delay is measured from a START condition to START condition.

UART InterfaceIn base mode, the µC is the host and can access the registers of both the serializer and deserializer from either side of the link using the GMSL UART protocol. The µC can also program the peripherals on the remote side by sending the UART packets to the serializer or deserializer, with the UART packets converted to I2C by the device on the remote side of the link. The µC communicates with a UART peripheral in base mode (through INTTYPE register settings), using the half-duplex default GMSL UART protocol of the serializer/deserializer. The device addresses of the serializer and deserializer in base mode are programmable.When the peripheral interface is I2C, the serializer/dese-rializer converts UART packets to I2C that have device addresses different from those of the serializer or dese-rializer. The converted I2C bit rate is the same as the original UART bit rate.

The deserializer uses differential line coding to send signals over the reverse channel to the serializer. The bit rate of the control channel

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or STP ... · input (oLDI) and a CML serial...

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Transcript of MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or STP ... · input (oLDI) and a CML serial...