LTC6228/LTC6229 (Rev. B) - Analog DevicesThe LTC ®6228/LTC6229 are ... ventional leaded packages....

LTC6228/LTC6229

1Rev. B

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TYPICAL APPLICATION

FEATURES DESCRIPTION

0.88nV/√Hz 730MHz, 500V/µs, Low Distortion Rail-to-Rail Output Op

Amps with Shutdown

The LTC®6228/LTC6229 are single/dual very fast, low noise rail-to-rail output, unity gain stable op amps. They have a gain-bandwidth product of 890MHz and a slew rate of 500V/μs. The low input referred voltage noise of only 0.88nV/√Hz and low distortion performance of better than −100dB at 4VP-P even for signals as fast as 2MHz make them ideal for applications that require high dynamic range and deal with high slew rate signals, such as driving A/D converters. Additional features include Shutdown and the ability to enable/disable internal bias current cancel-lation to optimize noise performance.

The combination of low offset, low offset drift, high gain and high CMRR make the LTC6228 family the superior choice for wide dynamic range applications.

The LTC6228 family maintains excellent performance for supply voltages of 2.8V to 11.75V and the devices are specified at supplies of 3V, 5V and 10V(±5V). With an input range extending to the negative rail and an out-put range that encompasses the entire supply range, the operational amplifier can accommodate wide swinging signals, and single supply operation.

For space constrained PCB layouts, the LTC6228 is avail-able in a 2mm × 2mm DFN and the LTC6229 is available in a 3mm × 3mm DFN. The amplifiers are also available in con-ventional leaded packages. These amplifiers can be used as improved replacements for many high speed op amps to improve speed, noise, distortion and dynamic range.

LTC6228 Based Driver for the LTC2387-18 SAR ADC

APPLICATIONS

n Ultra Low Voltage Noise: 0.88nV/√Hz n Low Distortion at High Speeds:

HD2/HD3 < −100dBc (Av = +1, 4VP-P, 2MHz, RL = 1kΩ) n High Slew Rate: 500V/μs n GBW = 890MHz n –3dB Frequency (AV = +1): 730MHz n Input Offset Voltage: 250μV Max Across Temperature n Offset Drift :0.4μV/°C n Input Common Mode Range Includes Negative Rail n Output Swings Rail-to-Rail n Supply Current: 16mA/Channel Typ n Shutdown Supply Current = 500µA n Operating Supply Range: 2.8V to 11.75V n Large Output Current: 80mA Min n Very High Open Loop Gain: 5.6V/μV (135dB), RL = 1kΩ n Operating Temp Range: –40°C to 125°C n Singles in 8-Lead SOIC, TSOT-23, DC-6, Duals in

DD10, MS8

n Optical Electronics: Fast Transimpedance Amplifiers n Driving High Dynamic Range A/D Converters n Active Filters n Video Amplifiers n High Speed Differential to Single-Ended Conversion n Low Voltage Hi-Fi Amplification

All registered trademarks and trademarks are the property of their respective owners.

–

+0.1µFLTC6228

25ΩIN–

IN+

VCM

CLK

82pF

4.096V

0V

82pF

6228 TA01a

LTC2387-18

DCO

DALVDSINTERFACE

DB

TWOLANES

TESTPAT

PDSAMPLECLOCKCNVREFB

–

+LTC6228

25Ω

4.096V

0V

7.5V

–2.5V

System Performance: 2 x LTC6228 Driving LTC2387-18 8192 Point FFT, –1dBFS

fSMPL = 15Msps, fIN = 1MHz

7.3VP-P 1MHz INPUT SIGNALSNR = 93.4dBSFDR = 95dBTHD = –93.8dB

FREQUENCY (MHz)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5

–140

–120

–100

–80

–60

–40

–20

0

AMPL

ITUD

E (d

BFS)

6228 TA02

https://www.analog.com/LTC6228?doc=LTC6228-6229.pdf


https://www.analog.com

https://form.analog.com/Form_Pages/feedback/documentfeedback.aspx?doc=LTC6228-6229.pdf&product=LTC6228%20LTC6229&Rev=B





LTC6228/LTC6229

2Rev. B

For more information www.analog.com

ABSOLUTE MAXIMUM RATINGSTotal Supply Voltage (V– to V+) .................................12VInput Voltage (–IN, +IN, SHDN)....V– – 0.3V to V+ + 0.3VInput Current (–IN, +IN, SHDN) (Note 2) .............. ±10mAOperating Temperature Range

LTC6228I/LTC6229I (Note 4) ...............–40°C to 85°C LTC6228H/LTC6229H (Note 4) .......... –40°C to 125°C

Specified Temperature Range LTC6228I/LTC6229I (Note 4) ...............–40°C to 85°C LTC6228H/LTC6229H (Note 4) .......... –40°C to 125°C

Output Current (OUT, FB)(Note 3) ...................... ±100mAOutput Short-Circuit Duration .............Thermally LimitedStorage Temperature Range .................. –65°C to 150°CMaximum Junction Temperature .......................... 150°CLead Temperature (Soldering 10s) (MSOP/S8/TSOT Only) ......................................... 300°C

(Note 1)

1

2

3

4

8

7

6

5

TOP VIEW

SHDN

V+

OUT

V–

FB

–IN

+IN

V–

S8 PACKAGE8-LEAD PLASTIC SO

TJMAX = 150°C, θJA = 120°C/W (NOTE 7)

+–

1

2

3

6

5

4

TOP VIEW

S6 PACKAGE6-LEAD PLASTIC TSOT-23

TJMAX = 150°C, θJA = 192°C/W (NOTE 7)

V+

SHDN

–IN

OUT

V–

+IN+ –

TOP VIEW

OUT

–IN

SHDN

V+

+IN

V–

DC PACKAGE6-LEAD (2mm × 2mm) PLASTIC DFN

TJMAX = 150°C, θJA = 80°C/W (NOTE 7)EXPOSED PAD (PIN 7) IS V–, MUST BE SOLDERED TO PCB

4

57V–

6

3

2

1

TOP VIEW

11V–

DD PACKAGE10-LEAD (3mm × 3mm) PLASTIC DFN


10

9

6

7

8

4

5

3

2

1 V+

OUTB

–INB

+INB

SHDNB

OUTA

–INA

+INA

V–

SHDNA

1234

OUTA–INA+INA

V–

8765

V+

OUTB–INB+INB

TOP VIEW

MSE PACKAGE8-LEAD PLASTIC MSOP


+–+

–

9V–

PIN CONFIGURATION




LTC6228/LTC6229

3Rev. B


The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V,VCM = 0V, VSHDN = floating unless otherwise noted.

ORDER INFORMATION

ELECTRICAL CHARACTERISTICS (VS = ±5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage

l

–95 –250

20 95 250

μV μV

∆VOS Input Offset Voltage Match (LTC6229)

l

–140 –400

18 140 400

µV µV

TCVOS Input Offset Voltage Drift l 0.4 μV/°C

IB Input Bias Current (Note 6) Bias Cancellation Disabled

l

–40 –44

–16 μA μA

Bias Cancellation Enabled

l

–2.5 –4.1

0.6 2.5 4.1

μA μA

∆IB Input Bias Current Match (LTC6229) Bias Cancellation Disabled

l

–2 –3

0.3 2 3

µA µA


l

–3 –4

0.3 3 4

µA µA

IOS Input Offset Current Bias Cancellation Disabled

l

–0.55 –0.8

0.1 0.55 0.8

μA μA


l

–0.9 –1

0.1 0.9 1

μA μA

∆IOS Input Offset Current Match (LTC6229) Bias Cancellation Disabled

l

–1 –1.4

0.15 1 1.4

µA µA


l

–1.3 –1.6

0.25 1.3 1.6

µA µA

en Input Noise Voltage Spectral Density f = 1MHz 0.88 nV/√Hz

Integrated 1/f Noise 0.1Hz to 10Hz 0.94 μVP-P

in Input Current Noise Spectral Density f = 1MHz Bias Cancellation Disabled f = 1MHz Bias Cancellation Enabled

3 6.3

pA/√Hz pA/√Hz

CIN Input Capacitance Differential Mode Common Mode

3.5 1.5

pF pF

RIN Input Resistance Differential Mode Common Mode

2.6 4

kΩ MΩ

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC6228IS6#TRMPBF LTC6228IS6#TRPBF LTHGB 6-Lead TSOT-23 –40°C to 85°C

LTC6228HS6#TRMPBF LTC6228HS6#TRPBF LTHGB 6-Lead TSOT-23 –40ºC to 125°C

LTC6228IDC#TRMPBF LTC6228IDC#TRPBF LHGC 6-Lead 2mm × 2mm DFN –40°C to 85°C

LTC6228HDC#TRMPBF LTC6228HDC#TRPBF LHGC 6-Lead 2mm × 2mm DFN –40ºC to 125°C

LTC6228IS8#TRMPBF LTC6228IS8#TRPBF 6228 8-Lead SOIC-8 –40°C to 85°C

LTC6228HS8#TRMPBF LTC6228HS8#TRPBF 6228 8-Lead SOIC-8 –40ºC to 125°C

LTC6229IMS8E#PBF LTC6229IMS8E#TRPBF LTGHD 8-Lead MSOP –40ºC to 85°C

LTC6229HMS8E#PBF LTC6229HMS8E#TRPBF LTGHD 8-Lead MSOP –40ºC to 125°C

LTC6229IDD#PBF LTC6229IDD#TRPBF LHGF 10-Lead 3mm × 3mm DFN –40ºC to 85°C

LTC6229HDD#PBF LTC6229HDD#TRPBF LHGF 10-Lead 3mm × 3mm DFN –40ºC to 125°C

Consult ADI Marketing for parts specified with wider operating temperature ranges.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.




https://www.analog.com/media/en/package-pcb-resources/package/tape-reel-rev-n.pdf

LTC6228/LTC6229

4Rev. B


The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V,VCM = 0V, VSHDN = floating unless otherwise noted.ELECTRICAL CHARACTERISTICS (VS = ±5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSAVOL Large Signal Voltage Gain RL = 1kΩ to Half Supply VOUT = ±4V

l

120 113

135 dB dB

RL = 100Ω to Half Supply VOUT = ±3V

l

100 92

120 dB dB

CMRR Common Mode Rejection Ratio VCM = V– – 0.1 to V+ – 1.2V

l

100 94

110 dB dB

VCMR Input Common Mode Range l V– – 0.1 V+ – 1.2 V

PSRR+ Positive Power Supply Rejection Ratio V– = –1V, V+ = 1.8V to 10.75V

l

100 95

110 dB dB

PSRR– Negative Power Supply Rejection Ratio V+ = 1.5V, V– = –1.3V to –10.25V

l

101 99

126 dB dB

Supply Voltage Range (V+ – V–) (Note 5) l 2.8 11.75 VVOL Output Swing Low (VOUT – V–) No Load

l

8 16 20

mV mV

ISINK = 5mA

l

46 70 85

mV mV

ISINK = 25mA

l

140 220 280

mV mV

VOH Output Swing High (V+ – VOUT) No Load

l

27 50 60

mV mV

ISINK = 5mA

l

90 140 180

mV mV

ISOURCE = 25mA

l

250 340 450

mV mV

ISC Output Short-Circuit Current Sourcing

l

–130 –80 –65

mA mA

Sinking

l

80 60

140 mA mA

IS Supply Current per Channel

l

16 16.9 19.8

mA mA

ISD Disable Supply Current per Channel, Amplifier Off

VSHDN = V+ – 2.75V

l

500 610 770

μA μA

VL_SHDN SHDN Pin Input Voltage Low, Disable Amplifier l V+ – 2.75 V

VH_SHDN SHDN Pin Input Voltage High, Enable Amplifier l V+ – 1.6 V

VL_IBIAS SHDN Pin Input Voltage Low, Disable Bias Cancellation

l V+ – 1 V

VH_IBIAS SHDN Pin Input Voltage Low, Enable Bias Cancellation

l V+ – 0.35 V

IL_SHDN SHDN Pin Input Current, Disable Amplifier VSHDN = V+ – 2.75V l –10 –2.5 10 μA

IH_SHDN SHDN Pin Input Current, Enable Amplifier VSHDN = V+ – 1.6V l –10 –0.3 10 μA

IL_IBIAS SHDN Pin Input Current Low, Disable Bias Cancellation

VSHDN = V+ – 1V l –10 0.265 10 μA

IH_IBIAS SHDN Pin Input Current Low, Enable Bias Cancellation

VSHDN = V+ – 0.35V l –10 1 10 μA

IOSD Output Leakage Current in Shutdown VSHDN = V+ – 2.75V, OUT Shorted to V+ or V– 100 nA

BW –3dB Closed Loop Bandwidth AV = 1, RL = 1kΩ to Half Supply 730 MHz

GBW Gain-Bandwidth Product f = 5MHz, RL = 1kΩ to Half Supply

l

700 650

890 MHz MHz

tON Turn-On Time VSHDN = V+ – 2.75V to V+ – 1.6V 900 ns




LTC6228/LTC6229

5Rev. B


The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V,VCM = 0V, VSHDN = floating unless otherwise noted.

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V,VCM = VOUT = 2.5V, VSHDN = floating unless otherwise noted.

ELECTRICAL CHARACTERISTICS (VS = ±5V)

ELECTRICAL CHARACTERISTICS (VS = 5V, 0V)


tOFF Turn-Off Time VSHDN = V+ – 1.6V to V+ – 2.75V 500 ns

tS_0.1 Settling Time to 0.1% AV = 1, 2V Output Step, RL = 1kΩ 26 ns

AV = 1, 4V Output Step, RL = 1kΩ 34 ns


SR Slew Rate AV = +4, 8V Output Step (Note 8)

l

320 250

500 V/μs V/μs

FPBW Full Power Bandwidth VOUT = 8VP-P, AV = +2, THD < –40dBc 12.5 MHz

HD2/HD3 Harmonic Distortion, RL = 1kΩ to Half Supply, AV = +1

fC = 100kHz, VO = 4VP-P fC = 100kHz, VO = 2VP-P fC = 1MHz, VO = 4VP-P fC = 1MHz, VO = 2VP-P fC = 5MHz, VO = 4VP-P fC = 5MHz, VO = 2VP-P fC = 10MHz, VO = 2VP-P

–113/–119 –126/–131 –107/–114 –119/–132 –83/–96

–90/–113 –74/–89

dBc dBc dBc dBc dBc dBc dBc

Harmonic Distortion, RL = 100Ω to Half Supply, AV = +1

fC = 100kHz, VO = 4VP-P fC = 100kHz, VO = 4VP-P fC = 1MHz, VO = 4VP-P fC = 1MHz, VO = 2VP-P fC = 5MHz, VO = 4VP-P fC = 5MHz, VO = 2VP-P fC = 10MHz, VO = 2VP-P

–105/–106 –118/–124 –97/–107

–100/–114 –79/–75 –83/–82 –72/–68

dBc dBc dBc dBc dBc dBc dBc

∆G Differential Gain (NTSC) AV = 2, RL = 150Ω AV = +1, RL = 1kΩ

0.008 0.001

% %

∆θ Differential Phase (NTSC) AV = 2, RL = 150Ω AV = +1, RL = 1kΩ

0.004 0.09

Deg Deg



l

–105 –290

20 105 290

μV μV


l

–140 –400

18 140 400

µV µV

TCVOS Input Offset Voltage Drift l 0.4 μV/°CIB Input Bias Current (Note 6) Bias Cancellation Disabled

l

–40 –44

–16 μA μA


l

–3 –4.4

1 3 4.4

μA μA


l

–2 –3

0.3 2 3

µA µA


l

–3 –4

0.3 3 4

µA µA


l

–0.55 –0.8

0.1 0.55 0.8

μA μA


l

–0.9 –1

0.15 0.9 1

μA μA


l

–1 –1.4

0.15 1 1.4

µA µA


l

–1.3 –1.6

0.25 1.3 1.6

µA µA




LTC6228/LTC6229

6Rev. B








3 6.3

pA/√Hz pA/√Hz


3.5 1.5

pF pF


2.6 4

kΩ MΩ

AVOL Large Signal Voltage Gain RL = 1kΩ to Half Supply, VOUT = VCM ±2

l

120 115

140 dB dB

RL = 100Ω to Half Supply, VOUT = VCM ±2

l

106 100

120 dB dB

CMRR Common Mode Rejection Ratio VCM = V– – 0.1 to V+ – 1.2V

l

97 92

110 dB dB



l

100 95

110 dB dB


l

103 100

126 dB dB

Supply Voltage Range (V+ – V–) (Note 5) l 2.8 11.75 V

VOL Output Swing Low (VOUT – V–) No Load

l

7 18 32

mV mV

ISINK = 5mA

l

40 70 90

mV mV

ISINK = 25mA

l

150 220 300

mV mV

VOH Output Swing High (VCC – V+) No Load

l

26 48 58

mV mV

ISINK = 5mA

l

93 144 185

mV mV

ISOURCE = 25mA

l

255 347 459

mV mV

ISC Output Short-Circuit Current Sourcing

l

–110 –65 –52

mA mA

Sinking

l

70 45

110 mA mA


l

16.5 17.8 19.6

mA mA


VSHDN = V+ – 2.65V

l

300 380 430

μA μA




l V+ – 1 V


l V+ – 0.35 V





LTC6228/LTC6229

7Rev. B


The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3V, 0V,VCM = 1.5V, VSHDN = floating unless otherwise noted.




l

–110 –300

24 110 300

μV μV


l

–140 –400

18 140 400

µV µV

TCVOS Input Offset Voltage Drift l 0.4 μV/°C

IB Input Bias Current (Note 6) Bias Cancellation Disabled

l

–38 –44

–16 μA μA


l

–3.5 –4.3

1.5 3.5 4.1

μA μA


l

–2 –3

0.3 2 3

µA µA


l

–3 –4

0.3 3 4

µA µA






VSHDN = V+ – 1V l –10 0.265 10 μA


VSHDN = V+ – 0.35V l –10 1 10 μA




l

700 600

865 MHz MHz




SR Slew Rate AV = +4, 4V Output Step (Note 8) 350 V/μs

FPBW Full Power Bandwidth VOUT = 4VP-P, AV = +2, THD < –40dBc 18 MHz

HD2/HD3 Harmonic Distortion, RL = 1kΩ to Half Supply fC = 100kHz, VO = 2VP-P fC = 1MHz, VO = 2VP-P fC = 5MHz, VO = 2VP-P fC = 10MHz, VO = 2VP-P

–106/–130 –95/–105 –88/–114 –78/–90

dBc dBc dBc dBc

Harmonic Distortion, RL = 100Ω to Half Supply

fC = 100kHz, VO = 2VP-P fC = 1MHz, VO = 2VP-P fC = 5MHz, VO = 2VP-P fC = 10MHz, VO = 2VP-P

–112/–115 –99/–120 –83/–88 –70/–73

dBc dBc dBc dBc

∆G Differential Gain (NTSC) AV = 2, RL = 150Ω AV = +1, RL = 1kΩ

0.005 0.002

% %

∆θ Differential Phase (NTSC) AV = 2, RL = 150Ω AV = +1, RL = 1kΩ

0.007 0.018

Deg Deg




LTC6228/LTC6229

8Rev. B




l

–0.55 –0.8

0.1 0.55 0.8

μA μA


l

–0.9 –1

0.15 0.9 1

μA μA


l

–1 –1.4

0.15 1 1.4

µA µA


l

–1.3 –1.6

0.25 1.3 1.6

µA µA




3 6.3

pA/√Hz pA/√Hz


3.5 1.5

pF pF


2.6 4

kΩ MΩ

AVOL Large Signal Voltage Gain RL = 1kΩ to Half Supply, (VOUT = VCM ±1V)

l

118 113

130 dB dB

RL = 100Ω to Half Supply, (VOUT = VCM ±1V)

120 dB

CMRR Common Mode Rejection Ratio VCM = V– to V+ – 1.2V

l

95 91

110 dB dB



l

100 95

110 dB dB


l

101 99

126 dB dB

Supply Voltage Range (V+ – V–) (Note 5) l 2.8 11.75 V

VOL Output Swing Low (VOUT – V–) No Load

l

7 10 18

mV mV

ISINK = 5mA

l

48 74 100

mV mV

ISINK = 25mA

l

165 320 430

mV mV

VOH Output Swing High (VCC – V+) No Load

l

27 49 59

mV mV

ISINK = 5mA

l

106 166 213

mV mV

ISOURCE = 25mA

l

290 520 580

mV mV

ISC Output Short-Circuit Current Sourcing –67 mA

Sinking 84 mA


l

16.4 17.6 19

mA mA


VSHDN = V+ – 2.65V

l

260 305 350

μA μA






LTC6228/LTC6229

9Rev. B








l V+ – 1 V


l V+ – 0.35 V




VSHDN = V+ – 1V l –10 0.265 10 μA


VSHDN = V+ – 0.35V l –10 1 10 μA




l

700 560

845 MHz MHz



tS_0.1 Settling Time to 0.1% AV = 1, VCM = 1V, 1V Output Step, RL = 1kΩ

31 ns

SR Slew Rate AV = +4, 2V Output Step 200 V/μs

FPBW Full Power Bandwidth VOUT = 2VP-P, VCM = 1V, AV = –1, THD < –40dBc

22 MHz

HD2/HD3 Harmonic Distortion, RL = 1kΩ to VCM, VOUT = 1VP-P, VCM = 1.25V

fC = 100kHz fC = 1MHz fC = 5MHz fC = 10MHz

–106/–127 –110/–128 –82/–105 –77/–96

dBc dBc dBc dBc

Harmonic Distortion, RL = 100Ω to VCM, VOUT = 1VP-P, VCM = 1.25V

fC = 100kHz fC = 1MHz fC = 5MHz fC = 10MHz

–116/–123 –105/–132 –89/–98 –77/–86

dBc dBc dBc dBc

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The inputs are protected by back-to-back diodes. If any of the input or shutdown pins goes 300mV beyond either supply or the differential input voltage exceeds 0.7V, the input current should be limited to less than 10mA.Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output current is high.

Note 4: The LTC6228I/LTC6229I is guaranteed functional and specified over the temperature range of –40°C to 85°C. The LTC6228H/LTC6229H is guaranteed functional and specified over the temperature range of –40°C to 125°C.Note 5: Supply range voltage is guaranteed by power supply rejection ratio test.Note 6: The input bias current is the average of the currents through the non-inverting and inverting input pins.Note 7: Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are with short traces connected to the leads with minimal metal area.Note 8: Middle 2/3 of the output waveform is observed. RL = 1kΩ at half supply.




LTC6228/LTC6229

10Rev. B


TYPICAL PERFORMANCE CHARACTERISTICS

Offset Distribution Offset Distribution Offset Distribution

VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

VS = ±5VVCM = 0V TA = 25°C

INPUT OFFSET VOLTAGE (µV)–60–50–40–30–20–10 0 10 20 30 40 50 60

0

5

10

15

20

25

30

35

40

45

50

PERC

ENT

OF U

NITS

(%)

6228 G01

VOS vs Temperature, 10V Supply VOS vs Temperature, 5V Supply VOS vs Temperature, 3V Supply

Offset Voltage vs Input Common Mode Voltage Offset Voltage vs Output Current Warm Up Drift vs Time


0

5

10

15

20

25

30

35

40

45

50

PERC

ENT

OF U

NITS

(%)

6228 G02

VS = 5V, 0VVCM = 2.5VTA = 25°C


0

5

10

15

20

25

30

35

40

45

50

PERC

ENT

OF U

NITS

(%)

6228 G03

VS = 3V, 0VVCM = 1.5VTA = 25°C

VS = ±5VVCM = 0V5 DEVICES

TEMPERATURE (°C)–55 –35 –15 5 25 45 65 85 105 125

0

20

40

60

80

100

120

140

160

INPU

T OF

FSET

VOL

TAGE

(µV)

6228 G04TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 1250

20

40

60

80

100

120

140

160

INPU

T OF

FSET

VOL

TAGE

(µV)

6228 G05

VS = ±2.5VVCM = 0V5 DEVICES

TEMPERATURE (°C)–55 –35 –15 5 25 45 65 85 105 125

0

20

40

60

80

100

120

140

160

INPU

T OF

FSET

VOL

TAGE

(µV)

6228 G06

VS = 3V, 0VVCM = 1.5V5 DEVICES

TA = 125°C

TA = 25°C

TA = –55°C

VS = ±5V

TA = 85°C

INPUT COMMON MODE VOLTAGE (V)–6 –5 –4 –3 –2 –1 0 1 2 3 4 5

–40–30–20–10

0102030405060708090

100

OFFS

ET V

OLTA

GE (µ

V)

6228 G07

TA = 125°C

TA = 25°C

TA = –55°C

VS = ±5V

TA = 85°C

OUTPUT CURRENT (mA)–50 –40 –30 –20 –10 0 10 20 30 40 50

0

20

40

60

80

100

120

140

160

180

200

OFFS

ET V

OLTA

GE (µ

V)

6228 G08

VS = ±5VTA=25°C

TIME AFTER POWER UP (s)0 1 2 3 4 5 6 7 8

–10

0

10

20

30

40

50

CHAN

GE IN

OFF

SET

VOLT

AGE

(µV)

Warm–up Drift vs Time

6228 G09




LTC6228/LTC6229

11Rev. B


TYPICAL PERFORMANCE CHARACTERISTICS VS = ±5V, VCM = 0V, TA = 25°C, unless otherwise noted.

Input Bias Current vs Input Common Voltage, Bias Cancellation Disabled

Input Bias Current vs Input Common Mode Voltage, Bias Cancellation Enabled 0.1Hz to 10Hz Voltage Noise

Input Voltage Noise and Current Noise Spectral Densities vs Frequency Supply Current vs Supply Voltage

Supply Current vs Input Common Mode Voltage

Supply Current vs SHDN Pin Voltage

Input Bias Current vs SHDN Pin Voltage

SHDN Pin Current vs SHDN Pin Voltage

VS = ±5V

TA = –55°CTA = 25°C

TA = 85°C

TA = 125°C

INPUT COMMON MODE VOLTAGE (V)–5.1 –4.2 –3.3 –2.4 –1.5 –0.7 0.2 1.1 2.0 2.9 3.8

–30

–25

–20

–15

–10

–5

0

5

INPU

T BI

AS C

URRE

NT (µ

A)

6228 G10

VS = ±5V

TA = –55°C

TA = 25°C

TA = 85°C

TA = 125°C


–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

INPU

T BI

AS C

URRE

NT (µ

A)

6228 G11

1s/DIV

INPU

T VO

LTAG

E NO

ISE

(200

nV/

Div)

0.1Hz to 10Hz Voltage Noise

6228 G12

VS = ±5VTA=25°C

eN

iN,bias cancellation enabled

iN,bias cancellation disabled

FREQUENCY (Hz)0.1 1 10 100 1k 10k 100k 1M 10M100M

0.51

10

100

1k

5k

INPU

T CU

RREN

T NO

ISE

(pA/

√Hz)

INPU

T VO

LTAG

E NO

ISE

(nV/

√Hz)

Spectral Densities vs FrequencyInput Voltage Noise and Current Noise

6228 G13

VCM = VS/2

TOTAL SUPPLY VOLTAGE (V)0 2 4 6 8 10 12

0

2

4

6

8

10

12

14

16

18

20

SUPP

LY C

URRE

NT (m

A)

6228 G14

TA = 125°C

TA = 25°C

TA = –55°C

TA = 125°C

TA = 25°C

TA = –55°C


10

11

12

13

14

15

16

17

18

19

20

SUPP

LY C

URRE

NT (m

A)

6228 G15

VS = ±5VTA = 125°C

TA = 25°C

TA = –55°C

SHDN PIN VOLTAGE (V)–5 –4 –3 –2 –1 0 1 2 3 4 5

0

2

4

6

8

10

12

14

16

18

20

SUPP

LY C

URRE

NT (m

A)

6228 G16

VS = ±5V

TA = –55°C

TA = 125°C

TA = 25°C

TA = 85°C

SHDN PIN VOLTAGE (V)3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5.0

–20.0

–17.5

–15.0

–12.5

–10.0

–7.5

–5.0

–2.5

0

2.5

5.0

INPU

T BI

AS C

URRE

NT (µ

A)

SHDN Pin VoltageInput Bias Current vs

6228 G17

VS = ±5V

TA = –55°C

TA = 125°C

TA = 25°C

SHDN PIN VOLTAGE (V)–5 –4 –3 –2 –1 0 1 2 3 4 5

–20.0

–17.5

–15.0

–12.5

–10.0

–7.5

–5.0

–2.5

0

2.5

5.0

SHDN

PIN

CUR

RENT

(µA)

SHDN Pin VoltageSHDN Pin Current vs

6228 G18




LTC6228/LTC6229

12Rev. B



Minimum Supply VoltageOutput Saturation Voltage vs Load Current (Output High)

Output Saturation Voltage vs Load Current (Output Low)

Output Short Circuit vs Supply Voltage Open Loop Gain, VS = ±5V Open Loop Gain, VS = ±2.5V

Open Loop Gain, VS = ±1.5V Gain vs Frequency, AV = 1 Gain vs Frequency, AV = 2

VCM = 1V

TA = 125°C

TA = 25°C

TA = –55°C

TOTAL SUPPLY VOLTAGE (V)2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

–200

–160

–120

–80

–40

0

40

80

120

160

200

INPU

T OF

FSET

VOL

TAGE

(µV)

6228 G19

TA = 125°C

TA = –55°C

TA = 25°C

VS = ±5V

LOAD CURRENT (mA)0.001 0.01 0.1 1 10 100

0.01

0.1

1

OUTP

UT H

IGH

SATU

RATI

ON V

OLTA

GE (V

)

6228 G20

TA = 125°C

TA = –55°C

TA = 25°C

VS = ±5V

LOAD CURRENT (mA)0.001 0.01 0.1 1 10 100

0.01

0.1

1

OUTP

UT L

OW S

ATUR

ATIO

N VO

LTAG

E (V

)

6228 G21

SOURCE

SINKTA = –55°C

TA = –55°C

TA = 25°C

TA = 25°C

TA = 125°C

TA = 125°C

TA = 85°C

TA = 85°C

TOTAL SUPPLY VOLTAGE (V)2.8 3.7 4.6 5.5 6.4 7.3 8.2 9.1 10.0 10.9 11.8

–150

–110

–70

–30

10

50

90

130

170

210

250

SHOR

T CI

RCUI

T CU

RREN

T (m

A)

vs Supply VoltageOutput Short Circuit

6228 G22

TA = 25°C

RL = 1kΩRL = 100Ω

OUTPUT VOLTAGE (V)–5 –4 –3 –2 –1 0 1 2 3 4 5

–40

–32

–24

–16

–8

0

8

16

24

32

40

INPU

T OF

FSET

VOL

TAGE

(µV)

6228 G23

OUTPUT VOLTAGE (V)–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5

–40

–32

–24

–16

–8

0

8

16

24

32

40

INPU

T OF

FSET

VOL

TAGE

(µV)

6228 G24

TA = 25°C

RL = 1kΩRL = 100Ω

OUTPUT VOLTAGE (V)–1.5 –1 –0.5 0 0.5 1 1.5

–40

–32

–24

–16

–8

0

8

16

24

32

40

INPU

T OF

FSET

VOL

TAGE

(µV)

6228 G25

TA = 25°C

RL = 1kΩRL = 100Ω

VS = ±5VRL = 1kΩTA = 25°C

FREQUENCY (Hz)10k 100k 1M 10M 100M 1G

–12

–10

–8

–6

–4

–2

0

2

4

GAIN

(dB)

6228 G26

RF = RG = 301Ω CF = 2.7pF

VS = ±5V

RL = 1kΩ

TA = 25°C


–24

–21

–18

–15

–12

–9

–6

–3

0

3

6

9

GAIN

(dB)

6228 G27




LTC6228/LTC6229

13Rev. B



Open Loop Gain and Phase vs Frequency

Gain Bandwidth and Phase Margin vs Supply Voltage

Gain Bandwidth and Phase Margin vs Temperature

Output Impedance vs FrequencyCommon Mode Rejection Ratio vs Frequency

Power Supply Rejection Ratio vs Frequency

Slew Rate vs Temperature Series Output Resistor vs Capacitive Load, AV = 1

Series Output Resistor vs Capacitive Load, AV = 2

RL = 1kΩ TO HALF SUPPLYTA = 25 °C

VCM = HALF SUPPLY

GAIN BANDWIDTHPRODUCT

PHASE MARGIN

TOTAL SUPPLY VOLTAGE (V)2.80 4.29 5.78 7.27 8.77 10.26 11.75

820

830

840

850

860

870

880

890

900

910

920

45

47

48

50

51

53

54

56

57

59

60

GAIN

BAN

DWID

TH (M

Hz)

PHASE MARGIN (°)

6228 G29

GAINBANDWIDTH

PHASE MARGIN

RL = 1kΩ

TEMPERATURE (°C)–55 –35 –15 5 25 45 65 85 105 125

700

730

760

790

820

850

880

910

940

970

1000

10

15

20

25

30

35

40

45

50

55

60

GAIN

BAN

DWID

TH P

RODU

CT (M

Hz)

PHASE MARGIN (°)

6228 G30

VS = ±5VVS = ±2.5VVS = ±1.5V

VS = ±5 V

AV = 1

AV = 10AV = 2


0.01

0.1

1

10

80

OUTP

UT IM

PEDA

NCE

(Ω)

6228 G31

VS = ±5VTA = 25°C

FREQUENCY (Hz)100k 1M 10M 100M 500M0

10

20

30

40

50

60

70

80

90

100

110

COM

MON

MOD

E RE

JECT

ION

RATI

O (d

B)

6228 G32

VS = ±5VVCM = 0VTA = 25°C

PSRR+

PSRR–

FREQUENCY (Hz)100 1k 10k 100k 1M 10M 100M

–10

10

30

50

70

90

110

130

PSRR

(dB)

6228 G33

AV = 4, RL=1kΩ

SLEW RATE MEASURED ATMIDDLE 2/3 OF OUTPUT

RISING

FALLING

RISING

FALLING

RISING

VS = ±5V, VOUT = 8VP-P

VS = ±2.5V, VOUT = 4VP-P

VS = ±1.5V, VOUT = 2VP-P

FALLING

TEMPERATURE (°C)–55 –35 –15 5 25 45 65 85 105 125

100

200

300

400

500

600

700

SLEW

RAT

E (V

/µS)

6228 G34

+– RS

VIN

VOUT

CL1kΩ

RS = 20Ω

RS = 50Ω

RS = 10Ω

VS = ±5V

CAPACITIVE LOAD (pF)10 100 1000 10000

5

10

15

20

25

30

35

40

45

50

55

OVER

SHOO

T (%

)

6228 G35

+– RS

VIN

VOUT

CL

C1

1kΩ

301Ω301Ω

CAPACITIVE LOAD (pF)10 100 1000 10000

0

15

30

45

60

75

90

105

120

135

150

OVER

SHOO

T (%

)

6228 G36

RS = 10Ω, CF = 0pFRS = 20Ω, CF = 0pFRS = 50Ω, CF = 0pF

RS = 10Ω, CF = 2.7pFRS = 20Ω, CF = 2.7pFRS = 50Ω, CF = 2.7pF

VS = ±5V

VS = ±5VTA = 25 °CRL = 1kΩ

GainPhase

FREQUENCY (Hz)500k1M 10M 100M 1G

–505

10152025303540455055606570

PHAS

E (°

)GA

IN (d

B)

vs FrequencyOpen Loop Gain and Phase

6228 G28




LTC6228/LTC6229

14Rev. B



Distortion vs Frequency, AV = 1, ±5V Supply

Distortion vs Frequency, AV = 1, 5V Supply


Distortion vs Frequency, AV = 2, ±5V Supply



Maximum Undistorted Output Signal vs Frequency

0.1% Settling Time vs Output Step (Non-Inverting)

0.1% Settling Time vs Output Step (Inverting)

VS = ±5VTA=25°C

VOUT = 4VP–P RL = 100Ω, 3rd

VOUT = 4VP–P RL = 100Ω, 2nd

VOUT = 4VP–P RL =1kΩ, 2nd

VOUT = 4VP–P RL = 1kΩ, 3rd


VOUT = 2VP–P RL = 1kΩ, 2nd

FREQUENCY (Hz)100k 1M 10M

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

DIST

ORTI

ON (d

Bc)

±5V SupplyDistortion vs Frequency, AV = 1

6228 G37

VS = 5V,0V VOUT=2VP–PRL to Mid–Supply TA=25°C

RL = 1kΩ, 2nd

RL = 100Ω, 2nd

RL = 1kΩ, 3rd

RL = 100Ω, 3rd


–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

DIST

ORTI

ON (d

Bc)

5V SupplyDistortion vs Frequency, AV = 1

6228 G38

VS = 3V,0V VOUT=1VP–PVCM=1.25V RL to VCM TA=25°C

RL = 1kΩ, 2nd

RL = 1kΩ, 3rd

RL = 100Ω, 3rd

RL = 100Ω, 2nd

FREQUENCY (Hz)100k 1M 10M 50M

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

DIST

ORTI

ON (d

Bc)


6228 G39

VS = ±5VTA=25°C

VOUT = 4VP–P RL = 100Ω, 3rd

VOUT = 4VP–P RL = 100Ω, 2nd

VOUT = 4VP–P RL =1kΩ, 2nd



VOUT = 2VP–P RL = 1kΩ, 2nd


–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

DIST

ORTI

ON (d

Bc)

±5V SupplyDistortion vs Frequency, AV = 2

6228 G40

VS = 5V,0V VOUT=2VP–PRL to Mid–Supply TA=25°C

RL = 1kΩ, 2nd

RL = 100Ω, 2nd

RL = 1kΩ, 3rd

RL = 100Ω, 3rd


–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

DIST

ORTI

ON (d

Bc)


6228 G41

VS = 3V, 0VVCM = 1VVOUT = 1VP-PRL to VCMTA = 25°C

RL = 100Ω, 2ND

RL = 1kΩ, 2ND

RL = 1kΩ, 3RD

RL = 100Ω, 3RD

FREQUENCY (Hz)100k 1M 10M 50M

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

DIST

ORTI

ON (d

Bc)

6228 G42

VS = ±5V

VS = ±2.5V

VS = ±1.5V

AV = 2

AV = –1

AV = –1

AV = 2AV = –1

TA = 25°CRL = 1kΩHD2, HD3 < –40dBc

FREQUENCY (MHz)0.1 1 10 40

0

1

2

3

4

5

6

7

8

9

10

OUTP

UT V

OLTA

GE S

WIN

G (V

P-P)

6228 G43

Av = +1TA=25°CVS=±5V (5.5V/–4.5V for step size>7V)

OUTPUT STEP (V)–8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8

20

25

30

35

40

45

50

SETT

LING

TIM

E (n

s)

vs Output Step (Non–inverting)0.1% Settling Time

6228 G44

VIN

VOUT

1kΩ

+–

Av = –1TA=25°CVS=±5V

OUTPUT STEP (V)–8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8

20

25

30

35

40

45

50

SETT

LING

TIM

E (n

s)

vs Output Step (Inverting)0.1% Settling Time

6228 G45

VINVOUT

1kΩ

+–301Ω

301Ω

2.7pF




LTC6228/LTC6229

15Rev. B



SHDN Pin Response Time Large Signal Response

Small Signal Response Output Overdrive Recovery

SHDN Pin Response Time

VS = ±5VTA=25°CAV=1

1µs/DIV

Output0V

500mV/DIV

Input0V

500mV/DIV

SHDN2.25V

1V/DIV6228 G46

Large Signal Response

VS = ±5VAV=1RL=1kΩTA=25°C

20ns/DIV

0V1.5V/DIV

6228 G47

Small Signal Response

VS = ±5VRL=1kΩAV=1TA=25°C

5ns/DIV

Input 0

50mV/DIV

Output 0

50mV/DIV

6228 G48

Output Overdrive Recovery

VS = ±5VAV=2RF=RG=500ΩCF=2.7pFRL=1kΩTA=25°C

Output

Input

25ns/DIV

Output2V/DIV

Input1V/DIV

6228 G49




LTC6228/LTC6229

16Rev. B


PIN FUNCTIONSFB (SOIC-8 Only): Feedback Pin. Internally connected to OUT.

+IN: Non-Inverting Input of Amplifier. Valid input range is from V– to V+ – 1.2V

–IN: Inverting Input of Amplifier. Valid input range is from V– to V+ – 1.2V

OUT: Output of the Amplifier. Swings rail to rail and can typically source/sink more than 90mA of current.

SHDN: Shutdown Pin (Active Low). Referenced to V+. When taken 2.75V below V+, the amplifier shuts down and enters low power mode, with the outputs in a high impedance state. When taken to within 350mV of V+, bias current cancellation is enabled. When left floating, the amplifier is on but bias cancellation is not enabled.

V+: Positive Supply to Amplifier. Valid range is from 2.8V to 11.75V when V– is 0V.

V–: Negative Supply to Amplifier. Typically 0V. This can be made a negative voltage as long as 2.8V ≤ (V+ – V–) ≤ 11.75V




LTC6228/LTC6229

17Rev. B


Circuit Description

The LTC6228/LTC6229 have an input signal range that extends from the negative power supply to 1.2V below the positive power supply. Figure 1 depicts a simplified schematic of the amplifier. The input stage consists of PNP transistors Q1 and Q2. At the input stage, devices Q18 and Q19 act to cancel the bias current of the input pair when bias cancellation is enabled. Bootstrap transistor Q13 and R5 match the collector and emitter voltages of Q11 and Q12, thus enhancing gain by improving output impedance. By making the collector current of Q13 twice that of Q11 and Q12, the base currents of Q11 and Q12 do not contribute towards mismatch between the collec-tor currents of Q9 and Q8. This improves DC accuracy. A pair of complementary common emitter stages, Q15 and Q14, enables the output to swing to either rail. The SHDN Interface block translates the SHDN signal into 2 signals, pwr_dn for powering down the device (by deactivating current sources I1 - I4) and putting the output in a high impedance state (by shorting the bases of Q15/Q14 to the

supplies via M2 and M1), and disable_bias, which disables the input bias cancellation circuit, by shorting the base of Q19 to V– through M3.

Input Bias Current

The LTC6228 family has an input bias current of approxi-mately 16μA. For the LTC6228 and the LTC6229DD10, the input bias current can be reduced to under 2.5μA at room temperature when the SHDN pin voltage is taken to within 350mV of the positive power supply. This capabil-ity enables the input bias current cancellation circuitry, allowing the amplifiers to be used in DC applications involving source impedances.

When input bias current cancellation is enabled and the input common mode voltage is within approximately 500mV of V–, the bias cancellation is no longer effec-tive, because transistors Q18 and Q19 in Figure 1 enter saturation. The input bias current can then exceed 50μA or higher, which is more than the input bias current

APPLICATIONS INFORMATION

Figure 1. LTC6228 Simplified Schematic Diagram

SHDN

I2

6228 F01

V+

V–

V+

CCV–

V–

+

Q16

Q15

Q2

Q11

Q1

Q17 Q18

+IN

ESDD1

SHDNINTERFACE

BLOCK

pwr_dn

pwr_dn

disable_bias

I1+

pwr_dn

I4pwr_dn

I3pwr_dn

pwr_dn

–IN

ESDD4

ESDD6

ESDD5

OUT

V+

V+ V–

ESDD3

ESDD2

D5 D7

Q19

R1 R2 R3

R3 R4 R5

M1 C1

Q10Q9 Q8

Q14

Q13Q12

BUFFERAND

OUTPUT BIAS

C2

M2pwr_dn

disable_bias M3




LTC6228/LTC6229

18Rev. B


APPLICATIONS INFORMATIONwithout input bias cancellation. Additionally when input bias current cancellation is enabled, the current noise increases. The decision to use input bias cancellation should be made with the end application’s specifications and conditions in mind.

If the SHDN pin is left floating, input bias cancellation is not enabled, which may be suitable for many applications.

Output

The LTC6228 family has excellent output drive capability. The amplifiers can typically deliver more than 90mA of output current at a total supply of 10V, and can typically swing to within 320mV of the supply with load currents as high as 25mA. As the supply voltage to the amplifier decreases, the output current capability also decreases. Attention must be paid to keep the junction temperature of the IC below 150°C (refer to Power Dissipation section) when the output is in continuous short-circuit. The output of the amplifier has reverse-biased diodes connected to each supply. If the output is forced beyond either supply, extremely high currents will flow through those diodes, which may result in damage to the device.

Input Protection

The LTC6228 has a pair of back to back diodes (D5 and D7) to prevent the emitter base breakdown of the input transistors and limit the differential input to ±700mV. Unlike many other high performance amplifiers, the bases of the input pair transistors Q1 and Q2 are not connected to the pins through internal resistors to limit input current, since doing so would cause the noise to increase. For instance, a 100Ω resistor in series with each input generates 1.8nV/√Hz of noise, and the total amplifier noise voltage would rise from 0.88nV/√Hz to 2nV/√Hz. If the input differential voltage exceeds ±0.7V, current conducted though the protection diodes D5 and D7 should be limited to under 10mA. This implies 25Ω of protection resistance per quarter volt (250mV) of overdrive beyond ±0.7V. In addition, the input and shutdown pins

have reverse biased diodes connected to the supplies. The current in these diodes must be limited to under 10mA. The amplifiers should not be used as comparators or in other open loop applications.

ESD

The LTC6228 family has reverse biased ESD protection diodes on all inputs as shown in Figure 1. There is an additional clamp between the positive and negative sup-plies that further protects the device during ESD strikes.

Hot plugging of the device into a powered socket should be avoided since this can trigger the clamp resulting in larger currents flowing between the supply pins.

Capacitive Loads

Because the LTC6228/LTC6229 is designed for high bandwidth applications, the output has not been designed to drive capacitive loads directly. Load capacitance at the output creates a non-dominant pole in the open loop fre-quency response, worsening the phase margin. When driving capacitive loads, a resistor of 10Ω to 100Ω should be connected between the amplifier output and the capac-itive load to avoid ringing or oscillation. The feedback should be taken directly from the amplifier output. Higher voltage gain configurations tend to have better capaci-tive drive capability than lower gain configurations due to lower closed loop bandwidth. The graphs titled Series Output Resistor vs Capacitive Load demonstrate the tran-sient response of the amplifier when driving capacitive loads with various series resistors.

Feedback Components

When feedback resistors are used to set up gain, care must be taken to ensure that the non-dominant pole formed by the feedback resistors and the parasitic capaci-tance at the inverting input does not degrade stability. For example if the amplifier is set up in a gain of +2 configu-ration with gain and feedback resistors of 1k, a parasitic capacitance of 7pF (device + PC board) at the amplifier’s




LTC6228/LTC6229

19Rev. B



Figure 2. 7pF Feedback Cancels Parasitic Pole

inverting input will cause the part to oscillate, due to the pole formed at 45MHz. Adding a capacitor of 7pF across the feedback resistor as shown in Figure 2 will eliminate any ringing or oscillation. In general, if the resistive feed-back network results in a pole whose frequency lies within the closed loop bandwidth of the amplifier, a capacitor can be added in parallel with the feedback resistor to introduce a zero whose frequency is close to the frequency of the pole, improving stability.

Power Dissipation

Care must be taken to ensure that the junction tempera-ture of the die does not exceed 150°C.

The junction temperature, TJ, is calculated from the ambi-ent temperature, TA, power dissipation, PD, and thermal resistance, θJA:

TJ = TA + (PD • θJA).

The power dissipation in the IC is a function of the supply voltage, output voltage and load resistance. For a given supply voltage with output load connected to mid supply, the worst-case power dissipation PD(MAX) occurs when the supply current is maximum and the output voltage at half of either supply voltage for a given load resistance. PD(MAX) is approximately (since IS actually changes with output load current) given by:

PD(MAX) = (2 • VS • IS(MAX)) + (VS/2)2/RL

Example: For an LTC6228 in a 6-lead DC package operat-ing on ±5V supplies and driving a 500Ω load to ground, the worst-case power dissipation is approximately given by PD(MAX)/Amp = (10 • 19mA) + (5)2/500 = 240mW.

At the Absolute Maximum ambient operating temperature, the junction temperature under these conditions will be:

TJ = TA + (PD • θJA) = 125 + 0.24 • 80 = 144.2°C

which is slightly less than the absolute maximum junction temperature for the LTC6228/LTC6229.

Refer to the Pin Configuration section for thermal resis-tances of various packages

Board Layout and Bypass Capacitors

High speed and RF board layout techniques should be used due to the very high speeds of the signals involved. For the LTC6228 SOIC-8 package option, the feedback should be taken from the FB pin rather than from the output pin, to reduce signal trace length.

For high speed designs, minimizing parasitic inductance is important. The use of capacitors where the electrodes are terminated on the long side instead of the short side (for example the use of 0306 instead of 0603 compo-nents) can help in this regard.

Shutdown

The LTC6228/LTC6229 have shutdown pins (SHDN), which disable the amplifiers and reduce the quiescent current per channel to approximately 500µA. The SHDN pin needs to be driven at least 2.75V below V+ to disable amplifier operation. For total supply voltages of 5V and or less, the amplifier can be disabled at a pin voltage of V+ – 2.65V. During shutdown, the output transistors Q15 and Q14 in Figure 1 are placed into a high impedance state. If SHDN is left floating, the pin is internally biased to 1.2V below the positive supply, and the amplifier remains on.

6228 F02

7pF

1k

1k

CPAR

VIN

VOUT

–

+




LTC6228/LTC6229

20Rev. B



Figure 3.

Stray capacitances at the –IN and +IN pins should be made as low as possible to reduce stability degradation. For example, ground or supply planes on a PCB should not encompass the areas just beneath the input pins.

For single supply applications, it is recommended that high quality 0.1µF||1000pF ceramic bypass capacitors be placed directly between each V+ pin and its closest V– pin with short connections. The V– pins (including the Exposed Pad) should be tied directly to a low impedance ground plane with minimal routing. For dual (split) power supplies, it is recommended that additional high quality 0.1µF||1000pF ceramic capacitors be used to bypass V+ pins to ground and V– pins to ground, again with minimal routing.

Noise Considerations

The ultralow input referred voltage noise of 0.88nV/√Hz is equivalent to that of a 47Ω resistor at room temperature. As with all BJT input amplifiers, lowering input referred voltage noise is achieved by increasing the collector cur-rent of the input differential pair, which increases the input referred current noise.

Op amp input referred noise dominates the input referred noise of the gain stage when

REQ << en2/4KT

Resistor noise dominates the input referred noise of the gain stage when

REQ >> en2/4KT and REQ << 4KT/in2

Op amp input referred current noise dominates the input referred noise when

REQ >> 4kT/in2

To summarize, initially en dominates for low resistance val-ues. As the resistance increased, resistor noise starts to dominate, then on further increase current noise dominates.

With an input referred voltage noise spectral density of 0.88nV/Hz and an input referred current noise of 3pA/Hz (bias cancellation disabled), it is easy to see that the gain stage’s input referred noise is dominated by op amp volt-age noise when REQ << 47Ω and by resistor noise when

55Ω << REQ << 1.8kΩ.

Above an REQ of 1.8kΩ, input referred current noise dominates.

Distortion/Noise Trade-Off

As evident from the previous section, gain stage noise can be reduced by reducing REQ. However, reducing REQ, by reducing RF and RG, has its disadvantages. In addition to increasing power dissipation in the presence of large output signals, the use of smaller resistors for a given gain results in increased distortion, because the internal nonlinearities of the op amp worsen with increasing load current. In addition, smaller resistors decrease op amp gain and hence can affect bandwidth. The disadvantage, however of making the resistors too large is that parasitic capacitance can start to affect the gain at high frequen-cies. Hence when designing a system using the LTC6228, it is recommended that the resistor values be limited only by the system noise requirements, with the caveat that the effect of the impedances parasitic capacitances shouldn’t affect the gain below the intended bandwidth. For exam-ple, for a feedback resistor of 5k, a parasitic capacitor of 400fF will impact gain at frequencies above 79MHz.

6228 F03

RFRG

–

+LTC6228RS1

en

in

in

Figure 3 shows the LTC6228 in a typical gain configuration.

As can be seen, the input referred noise spectral density of the gain stage (eT) can be calculated by the following equations:

eT2 = en

2 + in2REQ2 + 4KTREQ

Where

REQ = RS1 + RG||RF

opamp voltage noise

opamp current noise

resistor thermal noise




LTC6228/LTC6229

21Rev. B


TYPICAL APPLICATIONS18-Bit High Speed ADC Driver

The ultralow noise and distortion performance of the LTC6228 makes it an excellent candidate for driving high speed high resolution ADCs with fast, large amplitude signals. Figure 4 shows a pair of LTC6228s driven by a dif-ferential input, driving an LTC2387-18, a 15Msps, 18-bit ADC. Figure 5 shows an FFT obtained with a –1dBFS, 1MHz input signal. The obtained SNR is 93.4dB, better than the LTC2387-18’s guaranteed SNR of 93dB, and close to its typical value of 95.7dB. Spurious free dynamic range is an excellent 95dB, close to the LTC2387-18’s guaranteed SFDR of 97dB.

High Speed Low Voltage Low Noise Instrumentation Amplifier

Figure 6 shows a three op amp instrumentation amplifier with a gain of 41V/V which can operate on a wide range

of supply voltage. An RC snubber is used at the common terminal of the 30Ω gain setting resistors to reduce the effects of any board induced layout coupling from the output of one amplifier to the negative input of the other. Figure 7 shows the measured frequency response of the instrumentation amplifier for a load of 1kΩ. Figure 8 shows the measured CMRR of the instrumentation amplifier, and Figure 9 shows the transient response for a 50mVP-P input square wave applied to the positive input, with the negative input grounded. The total supply voltage was 3.3V. The extremely low offset voltage and low 1/f noise at the LTC6229 inputs allow for wide band instru-mentation amplifier operation, down to DC. Note, the bias currents of the LTC6229 are higher than might appear in a traditional low speed instrumentation amplifier. High speed instrumentation such as in Figure 6 assume a cor-respondingly low enough impedance excitation.

–

+

0.1µFLTC6228

25ΩIN–

IN+

VCM

CLK

82pF4.096V

0V

82pF

6228 F04

LTC2387-18

DCO

DALVDSINTERFACE

DB

TWOLANES

TESTPAT

PDSAMPLECLOCKCNVREFB

–

+LTC6228

7.5V

–2.5V

25Ω

4.096V

0V

Figure 4. High Speed Driver for 18-Bit ADC

Figure 5. Measured Performance of LTC6228 Based Driver Driving the LTC2387-18

8192 Point FFT, –1dBFS fSMPL = 15Msps, fIN = 1MHz

7.3VP-P 1MHz INPUT SIGNALSNR = 93.4dBSFDR = 95dBTHD = –93.8dB

FREQUENCY (MHz)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5

–140

–120

–100

–80

–60

–40

–20

0

AMPL

ITUD

E (d

BFS)

6228 F05




LTC6228/LTC6229

22Rev. B


TYPICAL APPLICATIONS

Figure 6. High Speed Low Voltage Low Noise Instrumentation Amplifier

Figure 7. Instrumentation Amplifier Frequency Response

Figure 9. Transient Response

–

+U2

1/2 LTC6229–IN

6228 F06

–

+U1

1/2 LTC6229

R4750Ω

R6750Ω

R5750Ω

R7750Ω

+IN

VS+

VOUT

VS = ±1.65VGAIN = 41V/VISUPPLY = 49mABW = 24MHzen (1MHz) = 1.79nV/√Hz

VS+

VS–

VS–

R21.2k

R31.2k

R130Ω

R830Ω

R949.9Ω

C2200pF

–

+U3

LTC6228

C12.2pF

FREQUENCY (Hz)10k 100k 1M 10M 100M 500M

–40

–30

–20

–10

0

10

20

30

40

GAIN

(dB)

6228 F07

FREQUENCY (Hz)10k 100k 1M 10M 100M 500M

0

10

20

30

40

50

60

70

80

90

100CO

MM

ON M

ODE

REJE

CTIO

N RA

TIO

(dB)

6228 F08

Figure 8. Instrumentation Amplifier CMRR

50ns/DIV

OUTPUT1V/DIV

0V

INPUT25mV/DIV

0V

6228 F09




LTC6228/LTC6229

23Rev. B


TYPICAL APPLICATIONS

Figure 10. Wideband Differential to Single-Ended Converter

Figure 11. Frequency Response of Differential to Single-Ended Converter

Figure 12. Common Mode Gain vs Frequency

Figure 13. Pulse Response of the Differential to Single-Ended Converter

6228 F10

CF118pF

R1200Ω

R7348Ω

R349.9Ω

R5150Ω

R4100Ω

R649.9Ω

RO149.9Ω

CF218pF

VOUT

VIN1

VIN2

–5V

–

+ –

+LTC6228

5V

Wideband Differential to Single-Ended Converter

The combination of high slew rate and bandwidth enables the LTC6228 to be used as a translator for large signals at high frequencies.

Figure 10 shows the implementation of a wide band, dif-ferential to single-ended converter with a gain of –6dB

using just one LTC6228. Figure 11 shows the frequency response of the circuit for a differential input of 2VP-P. The bandwidth obtained was 50MHz. The common mode gain of the driver is shown in Figure 12, and is limited by the matching between the resistors in the circuit. Figure 13 shows the response of the driver to a 1VP-P differential square wave signal.

FREQUENCY(Hz)100kHz

GAIN

(dB)

0

–27

–3

–9

–15

–21

–6

–12

–18

–24

–30100MHz1MHz

6228 F11

10MHzFREQUENCY (Hz)

GAIN

(dB)

6228 F12

100k 100M10M1M

10

–80

0

–20

–40

–60

–10

–30

–50

–70

–90

USING 1% RESISTORS

200ns/DIV

100mV/DIV

6228 F13




LTC6228/LTC6229

24Rev. B


PACKAGE DESCRIPTION

.016 – .050(0.406 – 1.270)

.010 – .020(0.254 – 0.508)

× 45°

0°– 8° TYP.008 – .010

(0.203 – 0.254)

SO8 REV G 0212

.053 – .069(1.346 – 1.752)

.014 – .019(0.355 – 0.483)

TYP

.004 – .010(0.101 – 0.254)

.050(1.270)

BSC

1 2 3 4

.150 – .157(3.810 – 3.988)

NOTE 3

8 7 6 5

.189 – .197(4.801 – 5.004)

NOTE 3

.228 – .244(5.791 – 6.197)

.245MIN .160 ±.005

RECOMMENDED SOLDER PAD LAYOUT

.045 ±.005 .050 BSC

.030 ±.005 TYP

INCHES(MILLIMETERS)

NOTE:1. DIMENSIONS IN

2. DRAWING NOT TO SCALE3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

S8 Package8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610 Rev G)




LTC6228/LTC6229

25Rev. B


PACKAGE DESCRIPTION

2.00 ±0.10(4 SIDES)

NOTE:1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.60 ±0.10(2 SIDES)

0.75 ±0.05

R = 0.125TYP

R = 0.05TYP

1.37 ±0.10(2 SIDES)

13

64

PIN 1 BARTOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DC6) DFN REV C 0915

0.25 ±0.050.50 BSC

0.25 ±0.05

1.37 ±0.10(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.60 ±0.10(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGEOUTLINE

0.50 BSC

PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER

DC6 Package6-Lead Plastic DFN (2mm × 2mm)

(Reference LTC DWG # 05-08-1703 Rev C)




LTC6228/LTC6229

26Rev. B


1.50 – 1.75(NOTE 4)

2.80 BSC

0.30 – 0.45 6 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20(NOTE 3) S6 TSOT-23 0302

2.90 BSC(NOTE 4)

0.95 BSC

1.90 BSC

0.80 – 0.90

1.00 MAX0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:1. DIMENSIONS ARE IN MILLIMETERS2. DRAWING NOT TO SCALE3. DIMENSIONS ARE INCLUSIVE OF PLATING4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR5. MOLD FLASH SHALL NOT EXCEED 0.254mm6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.62MAX

0.95REF

RECOMMENDED SOLDER PAD LAYOUTPER IPC CALCULATOR

1.4 MIN2.62 REF

1.22 REF

S6 Package6-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1636)

PACKAGE DESCRIPTION




LTC6228/LTC6229

27Rev. B


0.25 ±0.05

2.38 ±0.05(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05(2 SIDES)2.15 ±0.05

0.50BSC

0.70 ±0.05

3.55 ±0.05

PACKAGEOUTLINE

DD Package10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

3.00 ±0.10(4 SIDES)

NOTE:1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10(2 SIDES)

0.75 ±0.05

R = 0.125TYP

2.38 ±0.10(2 SIDES)

15

106

PIN 1TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV C 0310

0.25 ±0.050.50 BSC

PIN 1 NOTCHR = 0.20 OR0.35 × 45°CHAMFER

PACKAGE DESCRIPTION




LTC6228/LTC6229

28Rev. B


MSOP (MS8E) 0213 REV K

0.53 ±0.152(.021 ±.006)

SEATINGPLANE

NOTE:1. DIMENSIONS IN MILLIMETER/(INCH)2. DRAWING NOT TO SCALE3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.18(.007)

0.254(.010)

1.10(.043)MAX

0.22 – 0.38(.009 – .015)

TYP

0.86(.034)REF

0.65(.0256)

BSC

0° – 6° TYP

DETAIL “A”

DETAIL “A”

GAUGE PLANE

1 2 3 4

4.90 ±0.152(.193 ±.006)

8

8

1

BOTTOM VIEW OFEXPOSED PAD OPTION

7 6 5

3.00 ±0.102(.118 ±.004)

(NOTE 3)

3.00 ±0.102(.118 ±.004)

(NOTE 4)

0.52(.0205)

REF

1.68(.066)

1.88(.074)

5.10(.201)MIN

3.20 – 3.45(.126 – .136)

1.68 ±0.102(.066 ±.004)

1.88 ±0.102(.074 ±.004) 0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.65(.0256)

BSC0.42 ±0.038

(.0165 ±.0015)TYP

0.1016 ±0.0508(.004 ±.002)

DETAIL “B”

DETAIL “B”CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29REF

MS8E Package8-Lead Plastic MSOP, Exposed Die Pad(Reference LTC DWG # 05-08-1662 Rev K)

PACKAGE DESCRIPTION




LTC6228/LTC6229

29Rev. B


REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 09/19 Added LTC6229 to data sheet. All

B 03/20 Corrected wording and values on various pages. 1, 9, 17, 20, 30

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.




LTC6228/LTC6229

30Rev. B

For more information www.analog.com ANALOG DEVICES, INC. 2019-2020

03/20www.analog.com

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6228 TA02a

R11MΩ

C10.055pF

(PARASITIC)

OUT

D1PHOTODIODE

SFH213

5

–5

5

–5

–5R71.21kΩ

J1ON-SEMI2SK932-22

–3dB BW = 4.6MHzINTEGRATED NOISE = 661µVRMSOVER 4.6MHz

–

+ –

+

R3604Ω

C31µF

LTC6228

100ns/DIV

200mV/DIV

6228 TA02c

RISE TIME = 77ns

OUTP

UT V

OLTA

GE N

OISE

(nV√

Hz)

0

200

400

600

800

1000

100kHz 1MHz 10MHz6228 TA02b








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https://www.analog.com/LT1806?doc=LTC6228-6229.pdf










https://www.analog.com/AD8099?doc=LTC6228-6229.pdf


https://www.analog.com/ADA4899-1?doc=LTC6228-6229.pdf








LTC6228/LTC6229 (Rev. B) - Analog DevicesThe LTC ®6228/LTC6229 are ... ventional leaded packages....

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Transcript of LTC6228/LTC6229 (Rev. B) - Analog DevicesThe LTC ®6228/LTC6229 are ... ventional leaded packages....