Xuan ‘Silvia’ Zhang Washington University in St. Louis

http://classes.engineering.wustl.edu/ese566/

Lecture 2 CMOS Circuits

Quantitative CMOS Model

•  Threshold Voltage

•  I-V Curve –  linear/triode

–  saturation

•  Parasitic Capacitance –  gate cap –  junction cap

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( )|2||2|0 FSBFTT VVV φφγ −−+−+=

20 lni

DA

nNN

qkT

=φ

( )22

2ds

dsthgsoxn

DVVVV

LWCI −−=

µ

( ) ( )dsthgsoxn

D VVVLWCI λ

µ+−= 1

22

00

12 φε

⎟⎟⎠

⎞⎜⎜⎝

⎛

+=

DA

DAsij NN

NNqC

CMOS Capacitance

•  Overlap (gate) Cap –  Cgso

•  Junction Cap –  Cdiff

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Outline

CMOS Inverter Combinational Logic Sequential Circuits Memory

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Inverter: Simple RC Model

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Inverter Layout

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Assumptions: 1.  All transistors are minimum length 2.  All gate have equal rise/fall time

(PMOS twice as wide) 3.  Normalize transistor width to

minimum NMOS

1α

2α

Inverter Voltage Transfer Characteristics (VTC)

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Inverter Noise Margin

•  VIH, VIL, VOH, VOL Definition –  where the dVout/dVin slope is -1

•  Noise Margin –  if range of output VOL to VOH is wider than the range of

input values VIL to VIH, then the inverter exhibits noise immunity. (|Voltage Gain|>1)

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Inverter Noise Margin

•  NMH, NML Definition

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Inverter Dynamic Power

•  Capacitive Power

•  Short-circuit Power

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Inverter Static Power

•  Sub-threshold Leakage

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Outline

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CMOS Duality

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CMOS Static Logic Style

•  For every set of input logic values, either pull-up or pull-down network connects to VDD or GND –  power rails would be shorted if both connected –  output would float (tri-state logic), if neither connected

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NAND/NOR Static Logic Gates

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Design More Complex Gates

•  Goal is to create a logic function f(x1, x2, …) –  can only implement inverting logic with one stage

•  Implement pull-down network –  write PD = /f(x1, x2, …) –  use parallel NMOS for OR of inputs –  use series NMOS for AND of inputs

•  Implement pull-up network –  write PU = f(x1, x2, …) = g(/x1, /x2, …) –  use parallel PMOS for OR of inverted inputs –  use series PMOS for AND of inverted inputs

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Complex Logic Gate Example

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Multi-Stage Static Logic

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CMOS Pass-Gate Logic Style

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CMOS Transmission Gate Multiplexer

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CMOS Tri-State Buffers

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Various Multiplexer Implementations

•  Delay, Area, Energy Trade-offs –  simple first-order analysis

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Larger Tri-State Multiplexers

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Homework #2

•  Posted on class website •  Due on 1/30 at 2:30pm •  Provide extension to the lecture

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RC Delay

•  Lumped Model –  C only –  RC model

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Elmore Delay Formula

•  Assumptions regarding the RC network –  the network has a single input node –  all the capacitors are between a node and the ground –  the network does not contain any resistive loops (tree)

•  Unique resistive path –  path resistance –  shared path resistance

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Questions?

Comments?

Discussion?

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Acknowledgement

N. Weste and D. Harris, “CMOS VLSI Design”, 2011 Jan Rabaey, “Digital Integrated Circuits”, 2006

Cornell University, ECE 5745 UC Berkeley, CS 230

MIT, 6.371

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