Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary...

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1 Lecture 15: Circuit Families Pseudo-nMOS Logic Dynamic, Domino, NP-Domino CVSL, LEAN, CPL Delay What makes a circuit fast? Logical effort is proportional to C/I pMOS are the enemy! Can we take the pMOS capacitance off the input? Various circuit families try to do this… B A 1 1 4 4 Y

Transcript of Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary...

Page 1: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Lecture 15: Circuit Families

•  Pseudo-nMOS Logic •  Dynamic, Domino, NP-Domino •  CVSL, LEAN, CPL

Delay

•  What makes a circuit fast? –  I = C dV/dt -> tpd ∝ (C/I) ΔV –  low capacitance –  high current –  small swing

•  Logical effort is proportional to C/I •  pMOS are the enemy!

–  High capacitance for a given current •  Can we take the pMOS capacitance off the input? •  Various circuit families try to do this…

BA

11

4

4

Y

Page 2: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Pseudo-nMOS •  In the old days, nMOS

processes had no pMOS –  Instead, use pull-up

transistor that is always ON •  In CMOS, use a pMOS that is

always ON –  Ratio issue –  Make pMOS about ¼

effective strength of pulldown network

0 0.3 0.6 0.9 1.2 1.5 1.80

0.3

0.6

0.9

1.2

1.5

1.8

P = 24

P = 4

P = 14

Vin

Vout

V out

V in 8/2

P/2 I ds

load

Pseudo-nMOS Gates •  Design for unit current on output

to compare with unit inverter. –  pMOS fights nMOS

•  Pseudo-nMOS draws power whenever Y = 0 –  Static power P = I•VDD

–  A few mA / gate * 1M gates would be a problem –  Use pseudo-nMOS sparingly for wide NORs

Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9

Y

gu = 8/3gd = 8/9gavg = 16/9pu = 10/3pd = 10/9pavg = 20/9

gu = 4/3gd = 4/9gavg = 8/9pu = 10/3pd = 10/9pavg = 20/9

finputs

Y

A BY

C

en

Page 3: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Cascode Voltage Switch Logic (CVSL) •  True and complementary input and outputs

–  Pull-up network simplified –  Requires f and its complement function

•  For a given input pattern one of the pulldown networks is ON and the other is OFF –  The feedback mechanism ensures that the PMOS load is turned

OFF when the corresponding pulldown network is ACTIVE –  No static power dissipation

Cascode Voltage Switch Logic (CVSL) •  Potential speed advantage because

logic is performed with nMOS transistors

•  Cross-coupled load sizing –  Large pMOS will slow down

transition (similar to Pseudo NMOS) –  Small pMOS slows lo-to-hi transition

•  Does not work well for wide NOR gates –  CVSL requires the complement

funciton (slow tall NAND pull-down)

XOR

Page 4: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Dynamic Logic

•  Dynamic gates uses a clocked pMOS pullup •  Two modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

φ

Static Pseudo-nMOS Dynamic

φ Precharge Evaluate

Y

Precharge

Footed vs Unfooted •  What if pulldown network

is ON during precharge? •  Use series evaluation

transistor to prevent fight.

φY

inputs

φY

inputs

footed unfooted

f f

Inverter NAND2 NOR2

1 1

A Y

2 2 1

B A

Y

A B 1 1 1

g d = 1/3 p d = 2/3

g d = 2/3 p d = 3/3

g d = 1/3 p d = 3/3

Y φ

φ φ

footed

unfooted

2 1

A Y

3 3 1

B A

Y

A B 2 2 1

g d = 2/3 p d = 3/3

g d = 3/3 p d = 4/3

g d = 2/3 p d = 5/3

Y φ

φ φ

3 2 2

A Y

φ

foot

precharge transistor

Page 5: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Monotonicity •  Dynamic gates require monotonically rising inputs during

evaluation, produce monotonically falling outputs

•  Illegal for one dynamic gate to drive another!

φ Precharge Evaluate

Y

Precharge

A

Output should rise but does not

violates monotonicity during evaluation

A

φ

A X

φ Yφ Precharge Evaluate

X

Precharge

A = 1

Y should rise but cannot

Y

X monotonically falls during evaluation

Domino Gates

•  Follow dynamic stage with inverting static gate –  Dynamic / static pair is called domino gate –  Produces monotonic outputs

φ Precharge Evaluate

W

Precharge

X

Y

Z

A

φ

B C

φ φ φ

C

AB

W X Y Z =X

ZH H

A

W

φ

B C

X Y Z

domino AND

dynamicNAND

staticinverter

Page 6: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Domino Optimizations

•  Each domino gate triggers next one, like a string of dominos toppling over

•  Gates evaluate sequentially but precharge in parallel –  Thus evaluation is more critical than precharge –  HI-skewed static stages can perform logic

•  1.5 – 2x faster than static CMOS (widely used in µPs)

S0

D0

S1

D1

S2

D2

S3

D3

φ

S4

D4

S5

D5

S6

D6

S7

D7

φ

YH

High Skew NAND gate Better than 8-input dynamic MUX

NP-Domino •  Cascade N and P Domino stages

–  N-stage (precharge), P-stage (pre-discharge) –  Remove Static Inverter stage

Page 7: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Dual-Rail Domino

•  Domino only performs non-inverting functions: –  AND, OR but not NAND, NOR, or XOR

•  Dual-rail domino solves this problem –  Takes true and complementary inputs –  Produces true and complementary outputs

sig_h sig_l Meaning 0 0 0 1 1 0 1 1

Y_h

f

φ

φ

inputs

Y_l

f

Y_hφ

φ

Y_lA_h

B_hB_lA_l

= A*B= A*B

Leakage

•  Dynamic node floats high during evaluation –  Transistors are leaky (IOFF ≠ 0) –  Dynamic value will leak away over time –  Formerly miliseconds, now nanoseconds!

•  Use keeper to hold dynamic node –  Must be weak enough not to fight evaluation

CLK

VOut

Precharge

Evaluate

CL

Clk

Clk

Out

A

Mp

Me

Page 8: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Conditional Keepers •  Conditional Keepers are typically 1/10 of pull-down network

–  Large keeper provides high noise immunity, •  but slower pull-down…contention (fights) pull down path

–  In wide fan-in OR gates and multiplexers •  keepers must be stronger due to high leakage

–  Use keeper smaller than minimum sized transistor in small dynamic gates –  Burn in or programmable keepers

Charge Sharing •  Dynamic gates suffer from

charge sharing

•  Solution:

B = 0

AY

φ

x

Cx

CY

A

φ

x

Y

Charge sharing noise

Yx Y DD

x Y

CV V VC C

= =+

B A

Y φ

x

Page 9: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Clock Feedthrough and Back-Gate Coupling

CL

Clk

Clk

B

A

OutMp

Me

-0.5

0.5

1.5

2.5

0 0.5 1

A,B &Clk

Out

Time, ns

Vol

tage

Clock feedthrough

CL

Clk

Clk

B

A

OutMp

Me

CLCL

Clk

Clk

B

A

OutMp

Me

-0.5

0.5

1.5

2.5

0 0.5 1

A,B &Clk

Out

Time, ns

Vol

tage

Clock feedthrough

Pass Transistor Circuits

•  Use pass transistors like switches to do logic –  Inputs drive diffusion terminals as well as gates

•  CMOS + Transmission Gates: –  2-input multiplexer –  Gates should be restoring

•  Remove pMOS –  N Transistors –  No static power dissipation

A

B

S

S

S

Y

A

B

S

S

S

Y

B

B

A

F = AB

0

VDD

In

Outx

0.5µm/0.25µm0.5µm/0.25µm

1.5µm/0.25µm

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

Volta

g e[V

]

xOut

In

VDD

In

Outx

0.5µm/0.25µm0.5µm/0.25µm

1.5µm/0.25µm

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

Volta

g e[V

]

xOut

In

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

Volta

g e[V

]

xOut

In

Page 10: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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LEAP

•  LEAn integration with Pass transistors –  Use weak pMOS feedback to pull fully high –  Ratio constraint

B

S

SA

YL

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

t ag e

[V]

Time [ps]

3.0

M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

t ag e

[V]

Time [ps]

3.0

0 100 200 300 400 5000.0

1.0

2.0

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Vol

t ag e

[V]

Time [ps]

3.0

M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

XM2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

CPL

•  Complementary Pass-transistor Logic –  Dual-rail form of pass transistor logic –  Avoids need for ratioed feedback –  Optional cross-coupling for rail-to-rail swing

•  Alternate representation of CPL

B

S

S

S

S

A

B

AY

YL

L

Page 11: Lecture 15: Circuit Families · 3 Cascode Voltage Switch Logic (CVSL) • True and complementary input and outputs – Pull-up network simplified – Requires f and its complement

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Circuit Families

Comparison of circuit families for 2-input Muxes