Lecture 06: Current Mirrors - ECLIPSE Cluster · Lecture 06: Current Mirrors Analog IC Design Dr....

Lecture 06: Current MirrorsAnalog IC Design

Dr. Ryan Robucci

Department of Computer Science and Electrical Engineering, UMBC

Spring 2015

Dr. Ryan Robucci Lecture VI 1 / 26

Lowered Resistance Looking into Source

The functional description of a

current mirror is that it should

�copy� a current.

Iout = Iin

A current mirror can also have a

gain α

Iout = αIin


Dependence on Output Voltage

A good current mirror will have only a small dependence on Vout:

Iout = αIin + βVout where β is ideally ZERO.

If β is small, Rout does not depend on the load.


Basic Current Mirror

Key Characteristics:

Current Input, Current output

Rin, Rout

Input Voltage Range,

Output Voltage Range

Gain

Linearity


Behavior

Two transistors with the same

build and the same gate, drain,

source, and bulk potentials

conduct the same current.

The gate and drain voltages

both have an impact on

current, but the gate matters

more.


Mirror Node Behavior

Mirror Node Behavior:dVMdt = Iin−Ids1

CM

DC condition:

assume sat, λ = 0

Iin = Ids1 = k ′2

(WL

)1V 2

ov1

Vov1 =√

2Iink ′(W

L )1

Feedback Computes Inverse of IDS(Vg )Function! Answers: �What gate voltage

is required to conduct a speci�ed cur-

rent?�Computed� Gate Voltage Applied to M2:

De�ne: VM = Vov1 +VTH1

Iout = k ′2

(WL

)2V 2

ov2

Iout = k ′2

(WL

)2

(VM −VTH2)2

Iout = k ′2

(WL

)2

(Vov1 +VTH1−VTH2)2

Iout =

k ′2

(WL

)2

(√2Iin

k ′(WL )1

+VTH1−VTH2

)2

If VTH1 == VTH2,

Iout =(W

L )2

(WL )

1

Iin


Saturation assumptions

Revisit the assumptions of saturation.

M1:

Vd1 > Vg1−VTH1

(1) Note Vd1 = Vg1

(2) Vd1 > Vd1−VTH1 (obviously true if VTH1 > 0)

∴Vd1 > Vg1−VTH1

Key Analog Knowledge on Diode-Connected FETs:

Diode connected transistor in above-Vt operation mode is always in

saturation

M2:

Vd2 > Vg1−VTH2

Vout > Vov2 (Vov2 determined by Iout ,W2,L2)

Vout >√

2Ioutk ′(W

L )2

= Vout,min

Saturation condition constrains allowable output range


E�ect of Channel Length Modulation (E�ect of DrainVoltage)

Now considering Channel Length Modulation and computing VM

then Iout as before:

Iout = Iin

(WL

)1(

WL

)2

1+ λVds2

1+ λVds1

Even if λ1 == λ2 and can have 1+λVds21+λVds1

6= 1 since there is no

guarantee that Vds1 == Vds2.



Assume: W1 = W2 = W ; L1 = L2 = L ;λ1 = λ2 = λ

Examine λ1 e�ect with VDS2 held �xed:

dIoutdIin

=dIoutdVM︸︷︷︸GM2

dVM

dIin︸︷︷︸RIN

Rin (determines ∆VM in DC):

iin = vM

gm1 +1

rds1︸︷︷︸gds1

Rin = vM

iin= 1

gm1+gsd1

Rin ≈ 1gm1

if gm1� 1rds1

GM2:

Gm2 =−gm2



dIoutdIin

=dIoutdVM︸︷︷︸GM2

dVM

dIin︸︷︷︸RIN

dIoutdIin

= −gm2

gm1+gds1

?≈ −gm2

gm1︸︷︷︸ideally

(WL )

2

(WL )

1

Ideally gds1 is small so that we can ignore it:gdsgm

∝Iλ√2I

k ′(WL )

= λ0L0L

√12 Ik′(WL

)by keeping W

L constant and increasing L, the e�ect of gds on the

VM calculation is reduced

otherwise, the current mirror gain is K(WL )

2

(WL )

1

where K = gm1

gm1+gsd1and 0 < K < 1



Intuitive Explanation for K:

ideal ∆VM is calculated according to inverse of gm1

when ∆VM is calculated according to inverse of gm1 +gds1,∆VM is smaller

So, gds1causes reduction in output current

Now examine the current mirror's behavioral dependence on output

voltage



Examine dependence on output voltage with input current (and

VM) �xed:

dIoutdVout

= (Rout)−1 = (rds1)−1

to make Iout independent of RL and Vout

Rout should be large, making L2 large helps:

Rout = rds2 = 1λ2I

; λ2 = λ0L0L2


Drain Voltage Matching

?: represents known load resistor or known

output voltage

For best current matching, want Vd1 = Vd2 and L1 = L2in addition to Vg1 = Vg2.

Several non-ideal second-order behaviors are better matched in

parallel when transistor dimensions and all voltages match.

as Iin increases, Vm increases => Vd1 increases

Vout decreases if set by resistor or is �xed by another load

Iout = Iin(W

L )1

(WL )

2

1+λVds21+λVds1

predicts degraded behavior


Drain Voltage Matching

Iout = Iin(W

L )1

(WL )

2

1+λVds21+λVds1

Since VDS2 and VDS1 can't match at all currents

, may at least achieve VD1 = VD2 at some bas point

given Vout,bias design Vov1:

VM = Vov1 +VTH1 = Vout,bias

Vov1 = Vout,bias −VTH1√√√√√ 2I

k ′

(W

L

)1︸︷︷︸

= Vout,bias −VTH1

design WL


Cascoded-Output Mirrors

To increase output resistance, and make the output current less

sensitive to output voltage, a cascode can be used:

Rout ≈ gsr2ds (good)

Rin ≈ 1gm

This Rout is good, but lets study the current to current transfer

function:


Current-to-current Transfer Function

As Iin increases,

VM increases to support the additional current in M1

VS4 decreases to support the additional current in M4

as a result Vd1 increases yet Vd2 decreases

Iout = Iin(W

L )1

(WL )

2

1+λVds21+λVds1

predicts poor behavior (but not as bad as

prev.)

As before, we can at least design M3 to get VD2 = VD1 at a

speci�ed bias current

VD1 ≈ Vov1 +VTH1 = VM

VD2 ≈ Vcas −VTH3−Vov3

so, set Vcas = [VM ] +VTH3 +Vov3 = [Vov1 +VTH1] +VTH3 +Vov3Dr. Ryan Robucci Lecture VI 16 / 26

Output Range

For precision matching biasing:

Vcas = 2Vov +2VTH (big O)

Vout,min = Vcas −VTH3

Vout,min = 2Vov +VTH (big O)

if high Rout is needed rather than precision matching,

may set Vcas = Vov2 +VTH3 +VOV 3

Vout,min = Vcas −VTH3 = Vov2 +VOV 3

Vout,min = 2Vov (big O)


Self Biasing

Easy design that generates Vc

Since Vgs3 ≈ Vgs4 and Vg3 = Vg4

Vx ≈ VM

=>

The varying Vc keeps lower drain

voltages matched

Iout = Iin(W

L )1

(WL )

2

1+λVds21+λVds1

predicts good current matching

behaviorVC = 2Von +2VTH (big O)

Vout,min = 2Von +VTH (big O)

Rin ≈ 2 1gm

Input Voltage:VTH1 +VOV 1 +VTH3 +VOV 3

2VTH +2VOV (big O)


Wide-Range Biasing

Output Resistance:

Rout ≈ gs4rds4rds2Rout ≈ gsr

2ds (big O)

Input Resistance:

Rin ≈ 1gm1

Why?

?:Super FET with e�ective drain conductance (gm3rds3) rds1Rin = 1

gm1+1

(gm3rds3)rds1

E�ect of Vg1 of on current is much larger than that of a

changing Vd3 on the cascode structure


Wide-Range Biasing

Lower Rin is good for current input port

less dependence on Vin

holds Vin �xed

lowers input node time constant

Output Range:

Vout > Vcas −VTH3 = Vout,min

if Vcas = VOV 3 +VTH2 +VOV 4 +VTH4

Vout,min = Vov2 +VTH2 +VOV 4

Vout,min = 2Vov +VTH (big O)

Input Voltage:

Vin = Vov1 +VTH1

For both transistors to be in saturation (above-threshold) a lower

bound on the input voltage is Vin > Vov1 +Vov3

So, we requireVov3 < VTH1. Design(WL

)3AND Vcas accordingly

Design(WL

)3,Vcas according to maximum input current


Other Biasing Circuits (1)

Want Vcas ≈ VM −VTH1 +VTH3 +VOV 3

VCAS −VM =−VTH1 +VTH3 +VOV 3 = VR

so, set R = −VTH1+VTH3+VOV3Iin

then, Rin ≈ R + 1gm1

(derive as practice)

Input voltage: VTH1 +VOV 1 +VTH3 +VOV 3


Other biasing Circuits (2)


Other Biasing Circuits (3)

Vcas = (VTH5 +VOV 5) + (VTH6 +VOV 6)− (VTH7 +VOV 7)

make(WL

)7large, so large that Vov7 ≈ 0

then Vcas ≈ Vov +2VTH


Multiplying Mirrors

Multiplying W's in output leg creates a current multiplication:

Multiply W2& W4 by Mlet Iout = M · IinVov1 =

√2Iin

k ′(WL )

1

Vov2 =√

2Ioutk ′(W

L )2

=

√2[M·Iin]

k ′[M·(WL )

1]

∴ biasing is maintained as output leg widths are increased


Bidirectional Current Mirror

Iout = I1 + Iin− I2∂ Iout∂ Iin

=that of the mirror


Active Cascode Current Mirror

Uses feedback to increase output resistance (derived in HW)

Will discuss feedback later.


Lecture 06: Current Mirrors - ECLIPSE Cluster · Lecture 06: Current Mirrors Analog IC Design Dr....

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