ISSCC 2014 / SESSION 17 / ANALOG TECHNIQUES /...
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290 • 2014 IEEE International Solid-State Circuits Conference ISSCC 2014 / SESSION 17 / ANALOG TECHNIQUES / 17.3 17.3 A 0.9V 6.3μW Multistage Amplifier Driving 500pF Capacitive Load with 1.34MHz GBW Wanyuan Qu 1 , Jong-Pil Im 2 , Hyun-Sik Kim 1 , Gyu-Hyeong Cho 1 1 KAIST, Daejeon, Korea, 2 ETRI, Daejeon, Korea As process scales down, low-voltage, low-power, multistage amplifiers capable of driving a large capacitive load with wide bandwidth are becoming more important for various applications. The conventional frequency compensation methods, however, are based on cumbersome transfer function derivations or complicated local loop analysis [1]-[3], inhibiting intuitive understanding. An approach is presented in this paper, which generates insight for the poles and zeros through distinctive compensation analysis, and is applicable to large- number-stage amplifiers. The approach applies feedback theory and simplifies high-frequency Miller amplifiers, thereby reducing orders of circuits and improving insight. Since Miller compensation generates a large equivalent input capacitance by input-shunt-feedback, a simple Miller compensation amplifier equates a control system with plant H 2 and feedback element C m2 , as shown at the top of Fig. 17.3.1. Using feedback theory [4], the closed-loop gain of the control system is given by V o (s)/V 1 (s)=A vƒ =A ∞ T/(1+T)+A 0 /(1+T)≈A ∞ T/(1+T), where T is the loop gain of Miller feedback loop and A ∞ is the ideal closed-loop gain assuming T=∞. The A 0 is usually negligible since it is the direct feed-through when T=0. Here, we can see that A ∞ =g m2 /sC m2 and To get more insight, it is justifiable to focus only on the high-frequency loop gain T HF because an amplifier’s bandwidth and gain/phase margins only depend on the high-frequency behavior near unity gain-bandwidth (GBW), while the low- frequency behavior affects an amplifier’s DC accuracy. By ignoring all low-fre- quency components, T HF reduces to H 2 . That is, T HF =lim ƒ→GBW T=H 2 if GBW>>1/R o2 C m2 , C m2 >>C p2 and C L >>C p2 . Then, the amplifier’s gain at high frequency can be rewritten as This equation presents an insightful result. The original complex second-order equation is decomposed into the product of two first-order equations: A ∞2 and H 2 /(1+H 2 ). Here A ∞2 has a pole at the origin, while H 2 /(1+H 2 ) is the unity-feedback behavior of H 2 . In the bode plot of Fig. 17.3.1 top right, H 2 /(1+H 2 ) has a band- limiting pole at g mL /C L . Therefore, setting GBW=g m2 /C m2 =g mL /2C L is desirable and the resulting phase margin is around 60°. By applying the above method recursively, simple design equations can be obtained for nested Miller compensation (NMC) amplifiers without delving into lengthy equations. For the NMC shown at the bottom of Fig. 17.3.1, the inner- loop can be designed in the same manner as above and H 1 =A ∞2 H 2 /(1+H 2 ) from the block diagram. Thus, H 1 /(1+H 1 ) introduces two limiting poles (strictly, a pair of complex poles with damping factor of 1/√2) at the outer loop, as shown in Fig. 17.3.1 bottom right. Hence, setting GBW=gm 1 /C m1 =g m2 /2C m2 =g mL /4C L achieves 60° phase margin yielding a 3 rd -order Butterworth frequency response. Similarly, applying the method more times gives a five-stage NMC yielding a 5th- order Butterworth frequency response: Clearly, the more Miller feedback applied to the multistage amplifier, the larger the expected GBW reduction. Although prior studies have proposed various solutions to extend the GBW [1]-[3], the principles behind those circuits can be difficult to grasp. Using the above method, it is easy to note that all prior studies extend GBW by reducing the number of Miller feedbacks and insert a zero into T HF to enlarge the Miller loop bandwidth. For example, impedance-adapting- compensation (IAC) adds a passive zero [1], while active-zero-compensation (AZC) [2] and damping-factor-control [3] insert an active zero. That is, multistage amplifier design reduces to T HF design for maximum unity-feedback bandwidth to reduce complexity. Figures 17.3.2 and 17.3.3 compare the block diagrams and T HF bode plots of prior studies and this work. For IAC of Fig. 17.3.2 top left, T 1_HF ≈ H 1 and T 1_HF is stabilized by adding a zero 1/R a C a and pushing the original second pole 1/R o2 C p2 down to 1/R o2 C a . Bandwidth ω 1 is enlarged by g m2 R a times, while a band-limiting pole occurs at ω L1 =1/R a C p2 . There is a trade-off in choosing R a since a larger R a enlarges ω 1 at the cost of a less stable Miller feedback loop. In the AZC of Fig. 17.3.2 top right, T 2_HF ≈ H 2 C m /C p1 because current-buffer Miller compensation forms a common-gate amplifier with high-frequency gain of C m /C p1 . Here, an active zero is added to H 2 with the second pole untouched, so the bandwidth ω 2 is extended. However, ω 2 is limited by its third pole, ω L2 =g mb /C z , which results from the loading effect of active zero circuit. Also, AZC is not applicable to low-voltage design due to the current-buffer transconductance-boosting scheme, which aims to push the current-buffer pole g mc /C m beyond ω 2 . In Fig. 17.3.2 bottom, we present a local-feedback-enhanced compensation (LEC) scheme for three-stage amplifiers with large capacitive loads. LEC also adds an active zero but pushes the band-limiting pole higher, making a larger bandwidth ω 3 achievable. Here, the active zero is generated by a local feedback loop. The effect of the zero can be evaluated from the impedance of node p, Zp, which is 1/g mb at low frequencies and gradually increases as shunt-feedback weakens at high frequencies. Since a direct connection of R z to node p severely limits the achievable Z p , thereby limiting the effect of the zero, a no-loading local feedback has been implemented. This scheme isolates R z from node p and pushes the band-limiting pole to ω L3 =P1=g mb R op /C z R z . As shown in Fig. 17.3.3, ω L3 is extended by R op /R z times compared to that of [2]. Therefore, ω 3 can exceed ω 1 and ω 2 under the same C L and power constraints. Figure 17.3.4 shows an example of the circuit implementation of the proposed three-stage LEC amplifier. The first, second and third stages are implemented by M100-108, M201-202, and M301-302, respectively. The local feedback stage consists of M401-408, R z and C z . The slew helper contains M501-503. M403- 406 is the no-loading sensing circuit, which is a unity-gain buffer using current mirror. Node p’ equates the node p. R z and C z form the desired zero. M402 shields the large M401 from node p and reduces C pb . Current bleeder M408 increases the g ma /g mb gain. M202 and M302 generate feed-forward paths and improve slew-operation for the 2 nd and 3 rd stages. The 3 rd stage, however, needs further slew enhancement because M302 gate is a slow-transition node. By sensing the voltage of p’ through M501, M503 turns on quickly during the output rising transition and turns off in steady state. The LEC amplifier can operate at low power supply where multistage amplifiers are mostly required. Figure 17.3.5 shows the measured loop gain, step response, load capacitance and supply voltage variations. At C L =500pF, the amplifier achieved a GBW of 1.34MHz and phase margin of 52.7° with extrapolated DC gain >100dB. In the input step response test, the LEC in a unity-feedback configuration without slew helper showed an average slew rate (SR) and average 1% settling time (T S ) of 0.48V/μs and 2.53μs, while the LEC with slew helper achieved 0.62V/μs and 1.12μs, respectively. The rising overshoot was also greatly suppressed with the slew helper. The stable load capacitance C L range is 100pF to 500pF. When C L is small gain peaking occurs at around 40MHz and degrades the amplifier’s stability. For example, when C L =33pF, a high frequency ringing (~40MHz with 70mV pp ) is superimposed on the step response. This result is consistent with our simplified analysis method. The gain peaking comes from the unity-feedback behavior of T 3_HF . Compared to prior studies with a single band-limiting pole, T 3_HF contains a pair of complex limiting poles (P1&P2) because the poles are maximally extended near the vicinity of optimal design. The complex poles can generate excessive gain peaking when C L is small. Also as shown, the amplifier is functional from 0.7V to 1.8V supplies and the GBW is almost unchanged from 0.9V to 1.8V supplies. The results verify the applicability of LEC to low-voltage applications. Figure 17.3.6 presents a performance summary. Compared with other works, LEC shows improved FOM S (1.07×), FOM L (2.15×), LC-FOM S (2.87×) and LC-FOM L (4.08×). The chip is fabricated using a 0.18μm CMOS process with an area of 0.007mm 2 . References: [1] X. Peng, et al., “Impedance adapting compensation for low-power multistage amplifiers,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 445-451, Feb. 2011. [2] Z. Yan, et al., “A 0.016mm 2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with > 0.95MHz GBW,” ISSCC Dig. Tech. Papers, pp. 368-370, Feb. 2012. [3] K.N. Leung, et al., “Damping-factor-control frequency compensation technique for low-voltage low-power large capacitive load applications,” ISSCC Dig. Tech. Papers, pp. 158-159, Feb. 1999. [4] R.D. Middlebrook, “Design-Oriented Analysis of Feedback Amplifiers,” Proc. National Electronics Conference, vol. 20, pp.234-238, Oct. 1964. 978-1-4799-0920-9/14/$31.00 ©2014 IEEE T= H 2 (R o2 1 sC p2 ) (R L 1 sC L )+1 sC m2 +(R o2 1 sC p2 ) GBW = g m1 C m1 g m2 2C m2 g m3 3.2C m3 g m4 5.2C m4 g mL 10.4C L
Transcript of ISSCC 2014 / SESSION 17 / ANALOG TECHNIQUES /...
290 • 2014 IEEE International Solid-State Circuits Conference
ISSCC 2014 / SESSION 17 / ANALOG TECHNIQUES / 17.3
17.3 A 0.9V 6.3μW Multistage Amplifier Driving 500pF Capacitive Load with 1.34MHz GBW
Wanyuan Qu1, Jong-Pil Im2, Hyun-Sik Kim1, Gyu-Hyeong Cho1
1KAIST, Daejeon, Korea, 2ETRI, Daejeon, Korea
As process scales down, low-voltage, low-power, multistage amplifiers capableof driving a large capacitive load with wide bandwidth are becoming more important for various applications. The conventional frequency compensationmethods, however, are based on cumbersome transfer function derivations orcomplicated local loop analysis [1]-[3], inhibiting intuitive understanding. Anapproach is presented in this paper, which generates insight for the poles andzeros through distinctive compensation analysis, and is applicable to large-number-stage amplifiers. The approach applies feedback theory and simplifieshigh-frequency Miller amplifiers, thereby reducing orders of circuits and improving insight.
Since Miller compensation generates a large equivalent input capacitance byinput-shunt-feedback, a simple Miller compensation amplifier equates a controlsystem with plant H2 and feedback element Cm2, as shown at the top ofFig. 17.3.1. Using feedback theory [4], the closed-loop gain of the control system is given by Vo(s)/V1(s)=Avƒ=A∞T/(1+T)+A0/(1+T)≈A∞T/(1+T), where T isthe loop gain of Miller feedback loop and A∞ is the ideal closed-loop gain assuming T=∞. The A0 is usually negligible since it is the direct feed-throughwhen T=0. Here, we can see that A∞=gm2/sCm2 and
To get more insight, it is justifiable to focus only on the high-frequency loop gainTHF because an amplifier’s bandwidth and gain/phase margins only depend onthe high-frequency behavior near unity gain-bandwidth (GBW), while the low-frequency behavior affects an amplifier’s DC accuracy. By ignoring all low-fre-quency components, THF reduces to H2. That is, THF=limƒ→GBWT=H2 ifGBW>>1/Ro2Cm2, Cm2>>Cp2 and CL>>Cp2. Then, the amplifier’s gain at high frequency can be rewritten as
This equation presents an insightful result. The original complex second-orderequation is decomposed into the product of two first-order equations: A∞2 andH2/(1+H2). Here A∞2 has a pole at the origin, while H2/(1+H2) is the unity-feedbackbehavior of H2. In the bode plot of Fig. 17.3.1 top right, H2/(1+H2) has a band-limiting pole at gmL/CL. Therefore, setting GBW=gm2/Cm2=gmL/2CL is desirable andthe resulting phase margin is around 60°.
By applying the above method recursively, simple design equations can beobtained for nested Miller compensation (NMC) amplifiers without delving intolengthy equations. For the NMC shown at the bottom of Fig. 17.3.1, the inner-loop can be designed in the same manner as above and H1=A∞2 H2/(1+H2) fromthe block diagram. Thus, H1/(1+H1) introduces two limiting poles (strictly, a pairof complex poles with damping factor of 1/√2) at the outer loop, as shown inFig. 17.3.1 bottom right. Hence, setting GBW=gm1/Cm1=gm2/2Cm2=gmL/4CL
achieves 60° phase margin yielding a 3rd-order Butterworth frequency response.Similarly, applying the method more times gives a five-stage NMC yielding a 5th-order Butterworth frequency response:
Clearly, the more Miller feedback applied to the multistage amplifier, the largerthe expected GBW reduction. Although prior studies have proposed varioussolutions to extend the GBW [1]-[3], the principles behind those circuits can bedifficult to grasp. Using the above method, it is easy to note that all prior studiesextend GBW by reducing the number of Miller feedbacks and insert a zero intoTHF to enlarge the Miller loop bandwidth. For example, impedance-adapting-compensation (IAC) adds a passive zero [1], while active-zero-compensation(AZC) [2] and damping-factor-control [3] insert an active zero. That is, multistage amplifier design reduces to THF design for maximum unity-feedbackbandwidth to reduce complexity.
Figures 17.3.2 and 17.3.3 compare the block diagrams and THF bode plots ofprior studies and this work. For IAC of Fig. 17.3.2 top left, T1_HF ≈ H1 and T1_HF isstabilized by adding a zero 1/RaCa and pushing the original second pole 1/Ro2Cp2
down to 1/Ro2Ca. Bandwidth ω1 is enlarged by gm2Ra times, while a band-limitingpole occurs at ωL1=1/RaCp2. There is a trade-off in choosing Ra since a larger Ra
enlarges ω1 at the cost of a less stable Miller feedback loop.
In the AZC of Fig. 17.3.2 top right, T2_HF ≈ H2Cm/Cp1 because current-buffer Millercompensation forms a common-gate amplifier with high-frequency gain ofCm/Cp1. Here, an active zero is added to H2 with the second pole untouched, sothe bandwidth ω2 is extended. However, ω2 is limited by its third pole,ωL2=gmb/Cz, which results from the loading effect of active zero circuit. Also, AZCis not applicable to low-voltage design due to the current-buffer transconductance-boosting scheme, which aims to push the current-buffer polegmc/Cm beyond ω2.
In Fig. 17.3.2 bottom, we present a local-feedback-enhanced compensation(LEC) scheme for three-stage amplifiers with large capacitive loads. LEC alsoadds an active zero but pushes the band-limiting pole higher, making a largerbandwidth ω3 achievable. Here, the active zero is generated by a local feedbackloop. The effect of the zero can be evaluated from the impedance of node p, Zp,which is 1/gmb at low frequencies and gradually increases as shunt-feedbackweakens at high frequencies. Since a direct connection of Rz to node p severelylimits the achievable Zp, thereby limiting the effect of the zero, a no-loading localfeedback has been implemented. This scheme isolates Rz from node p and pushes the band-limiting pole to ωL3=P1=gmbRop/CzRz. As shown in Fig. 17.3.3,ωL3 is extended by Rop/Rz times compared to that of [2]. Therefore, ω3 canexceed ω1 and ω2 under the same CL and power constraints.
Figure 17.3.4 shows an example of the circuit implementation of the proposedthree-stage LEC amplifier. The first, second and third stages are implemented byM100-108, M201-202, and M301-302, respectively. The local feedback stageconsists of M401-408, Rz and Cz. The slew helper contains M501-503. M403-406 is the no-loading sensing circuit, which is a unity-gain buffer using currentmirror. Node p’ equates the node p. Rz and Cz form the desired zero. M402shields the large M401 from node p and reduces Cpb. Current bleeder M408increases the gma/gmb gain. M202 and M302 generate feed-forward paths andimprove slew-operation for the 2nd and 3rd stages. The 3rd stage, however, needsfurther slew enhancement because M302 gate is a slow-transition node. Bysensing the voltage of p’ through M501, M503 turns on quickly during the outputrising transition and turns off in steady state. The LEC amplifier can operate atlow power supply where multistage amplifiers are mostly required.
Figure 17.3.5 shows the measured loop gain, step response, load capacitanceand supply voltage variations. At CL=500pF, the amplifier achieved a GBW of1.34MHz and phase margin of 52.7° with extrapolated DC gain >100dB. In theinput step response test, the LEC in a unity-feedback configuration without slewhelper showed an average slew rate (SR) and average 1% settling time (TS) of0.48V/μs and 2.53μs, while the LEC with slew helper achieved 0.62V/μs and1.12μs, respectively. The rising overshoot was also greatly suppressed with theslew helper. The stable load capacitance CL range is 100pF to 500pF. When CL issmall gain peaking occurs at around 40MHz and degrades the amplifier’s stability. For example, when CL=33pF, a high frequency ringing (~40MHz with70mVpp) is superimposed on the step response. This result is consistent withour simplified analysis method. The gain peaking comes from the unity-feedbackbehavior of T3_HF. Compared to prior studies with a single band-limiting pole,T3_HF contains a pair of complex limiting poles (P1&P2) because the poles aremaximally extended near the vicinity of optimal design. The complex poles cangenerate excessive gain peaking when CL is small. Also as shown, the amplifieris functional from 0.7V to 1.8V supplies and the GBW is almost unchanged from0.9V to 1.8V supplies. The results verify the applicability of LEC to low-voltageapplications.
Figure 17.3.6 presents a performance summary. Compared with other works,LEC shows improved FOMS (1.07×), FOML (2.15×), LC-FOMS (2.87×) and LC-FOML (4.08×). The chip is fabricated using a 0.18μm CMOS process with anarea of 0.007mm2.
References:[1] X. Peng, et al., “Impedance adapting compensation for low-power multistageamplifiers,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 445-451, Feb. 2011.[2] Z. Yan, et al., “A 0.016mm2 144μW three-stage amplifier capable of driving1-to-15nF capacitive load with > 0.95MHz GBW,” ISSCC Dig. Tech. Papers, pp.368-370, Feb. 2012.[3] K.N. Leung, et al., “Damping-factor-control frequency compensation technique for low-voltage low-power large capacitive load applications,” ISSCCDig. Tech. Papers, pp. 158-159, Feb. 1999.[4] R.D. Middlebrook, “Design-Oriented Analysis of Feedback Amplifiers,” Proc.National Electronics Conference, vol. 20, pp.234-238, Oct. 1964.
978-1-4799-0920-9/14/$31.00 ©2014 IEEE
T=H2(Ro2 1 sCp2 )
(RL 1 sCL )+1 sCm2 +(Ro2 1 sCp2 )
GBW = gm1
Cm1
gm2
2Cm2
gm3
3.2Cm3
gm4
5.2Cm4
gmL
10.4CL
291DIGEST OF TECHNICAL PAPERS •
ISSCC 2014 / February 11, 2014 / 2:15 PM
Figure 17.3.1: Simplified analysis method for simple Miller compensation(SMC) and nested Miller compensation (NMC).
Figure 17.3.2: Block diagrams of the three-stage amplifiers of [1], [2] and thiswork.
Figure 17.3.3: Bode plots of simplified high-frequency loop gain THF of theMiller feedback loop for [1], [2] and this work.
Figure 17.3.5: Measured AC (upper, left) and transient (upper, right) respons-es, load capacitance (lower, left) and supply voltage (lower, right) variations.
Figure 17.3.6: Performance summary and benchmark of the state-of-the-artmultistage amplifiers.
Figure 17.3.4: Circuit schematic and device sizes of the LEC amplifier.
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• 2014 IEEE International Solid-State Circuits Conference 978-1-4799-0920-9/14/$31.00 ©2014 IEEE
ISSCC 2014 PAPER CONTINUATIONS
Figure 17.3.7: Chip micrograph of the LEC amplifier.
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