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290 2014 IEEE International Solid-State Circuits Conference

ISSCC 2014 / SESSION 17 / ANALOG TECHNIQUES / 17.3

17.3 A 0.9V 6.3W Multistage Amplifier Driving 500pF Capacitive Load with 1.34MHz GBW

Wanyuan Qu1, Jong-Pil Im2, Hyun-Sik Kim1, Gyu-Hyeong Cho1

1KAIST, Daejeon, Korea, 2ETRI, Daejeon, Korea

As process scales down, low-voltage, low-power, multistage amplifiers capableof driving a large capacitive load with wide bandwidth are becoming more important for various applications. The conventional frequency compensationmethods, however, are based on cumbersome transfer function derivations orcomplicated local loop analysis [1]-[3], inhibiting intuitive understanding. Anapproach is presented in this paper, which generates insight for the poles andzeros through distinctive compensation analysis, and is applicable to large-number-stage amplifiers. The approach applies feedback theory and simplifieshigh-frequency Miller amplifiers, thereby reducing orders of circuits and improving insight.

Since Miller compensation generates a large equivalent input capacitance byinput-shunt-feedback, a simple Miller compensation amplifier equates a controlsystem with plant H2 and feedback element Cm2, as shown at the top ofFig. 17.3.1. Using feedback theory [4], the closed-loop gain of the control system is given by Vo(s)/V1(s)=Av=AT/(1+T)+A0/(1+T)AT/(1+T), where T isthe loop gain of Miller feedback loop and A is the ideal closed-loop gain assuming T=. The A0 is usually negligible since it is the direct feed-throughwhen T=0. Here, we can see that A=gm2/sCm2 and

To get more insight, it is justifiable to focus only on the high-frequency loop gainTHF because an amplifiers bandwidth and gain/phase margins only depend onthe high-frequency behavior near unity gain-bandwidth (GBW), while the low-frequency behavior affects an amplifiers DC accuracy. By ignoring all low-fre-quency components, THF reduces to H2. That is, THF=limGBWT=H2 ifGBW>>1/Ro2Cm2, Cm2>>Cp2 and CL>>Cp2. Then, the amplifiers gain at high frequency can be rewritten as

This equation presents an insightful result. The original complex second-orderequation is decomposed into the product of two first-order equations: A2 andH2/(1+H2). Here A2 has a pole at the origin, while H2/(1+H2) is the unity-feedbackbehavior of H2. In the bode plot of Fig. 17.3.1 top right, H2/(1+H2) has a band-limiting pole at gmL/CL. Therefore, setting GBW=gm2/Cm2=gmL/2CL is desirable andthe resulting phase margin is around 60.

By applying the above method recursively, simple design equations can beobtained for nested Miller compensation (NMC) amplifiers without delving intolengthy equations. For the NMC shown at the bottom of Fig. 17.3.1, the inner-loop can be designed in the same manner as above and H1=A2 H2/(1+H2) fromthe block diagram. Thus, H1/(1+H1) introduces two limiting poles (strictly, a pairof complex poles with damping factor of 1/2) at the outer loop, as shown inFig. 17.3.1 bottom right. Hence, setting GBW=gm1/Cm1=gm2/2Cm2=gmL/4CLachieves 60 phase margin yielding a 3rd-order Butterworth frequency response.Similarly, applying the method more times gives a five-stage NMC yielding a 5th-order Butterworth frequency response:

Clearly, the more Miller feedback applied to the multistage amplifier, the largerthe expected GBW reduction. Although prior studies have proposed varioussolutions to extend the GBW [1]-[3], the principles behind those circuits can bedifficult to grasp. Using the above method, it is easy to note that all prior studiesextend GBW by reducing the number of Miller feedbacks and insert a zero intoTHF to enlarge the Miller loop bandwidth. For example, impedance-adapting-compensation (IAC) adds a passive zero [1], while active-zero-compensation(AZC) [2] and damping-factor-control [3] insert an active zero. That is, multistage amplifier design reduces to THF design for maximum unity-feedbackbandwidth to reduce complexity.

Figures 17.3.2 and 17.3.3 compare the block diagrams and THF bode plots ofprior studies and this work. For IAC of Fig. 17.3.2 top left, T1_HF H1 and T1_HF isstabilized by adding a zero 1/RaCa and pushing the original second pole 1/Ro2Cp2down to 1/Ro2Ca. Bandwidth 1 is enlarged by gm2Ra times, while a band-limitingpole occurs at L1=1/RaCp2. There is a trade-off in choosing Ra since a larger Raenlarges 1 at the cost of a less stable Miller feedback loop.

In the AZC of Fig. 17.3.2 top right, T2_HF H2Cm/Cp1 because current-buffer Millercompensation forms a common-gate amplifier with high-frequency gain ofCm/Cp1. Here, an active zero is added to H2 with the second pole untouched, sothe bandwidth 2 is extended. However, 2 is limited by its third pole,L2=gmb/Cz, which results from the loading effect of active zero circuit. Also, AZCis not applicable to low-voltage design due to the current-buffer transconductance-boosting scheme, which aims to push the current-buffer polegmc/Cm beyond 2.

In Fig. 17.3.2 bottom, we present a local-feedback-enhanced compensation(LEC) scheme for three-stage amplifiers with large capacitive loads. LEC alsoadds an active zero but pushes the band-limiting pole higher, making a largerbandwidth 3 achievable. Here, the active zero is generated by a local feedbackloop. The effect of the zero can be evaluated from the impedance of node p, Zp,which is 1/gmb at low frequencies and gradually increases as shunt-feedbackweakens at high frequencies. Since a direct connection of Rz to node p severelylimits the achievable Zp, thereby limiting the effect of the zero, a no-loading localfeedback has been implemented. This scheme isolates Rz from node p and pushes the band-limiting pole to L3=P1=gmbRop/CzRz. As shown in Fig. 17.3.3,L3 is extended by Rop/Rz times compared to that of [2]. Therefore, 3 canexceed 1 and 2 under the same CL and power constraints.

Figure 17.3.4 shows an example of the circuit implementation of the proposedthree-stage LEC amplifier. The first, second and third stages are implemented byM100-108, M201-202, and M301-302, respectively. The local feedback stageconsists of M401-408, Rz and Cz. The slew helper contains M501-503. M403-406 is the no-loading sensing circuit, which is a unity-gain buffer using currentmirror. Node p equates the node p. Rz and Cz form the desired zero. M402shields the large M401 from node p and reduces Cpb. Current bleeder M408increases the gma/gmb gain. M202 and M302 generate feed-forward paths andimprove slew-operation for the 2nd and 3rd stages. The 3rd stage, however, needsfurther slew enhancement because M302 gate is a slow-transition node. Bysensing the voltage of p through M501, M503 turns on quickly during the outputrising transition and turns off in steady state. The LEC amplifier can operate atlow power supply where multistage amplifiers are mostly required.

Figure 17.3.5 shows the measured loop gain, step response, load capacitanceand supply voltage variations. At CL=500pF, the amplifier achieved a GBW of1.34MHz and phase margin of 52.7 with extrapolated DC gain >100dB. In theinput step response test, the LEC in a unity-feedback configuration without slewhelper showed an average slew rate (SR) and average 1% settling time (TS) of0.48V/s and 2.53s, while the LEC with slew helper achieved 0.62V/s and1.12s, respectively. The rising overshoot was also greatly suppressed with theslew helper. The stable load capacitance CL range is 100pF to 500pF. When CL issmall gain peaking occurs at around 40MHz and degrades the amplifiers stability. For example, when CL=33pF, a high frequency ringing (~40MHz with70mVpp) is superimposed on the step response. This result is consistent withour simplified analysis method. The gain peaking comes from the unity-feedbackbehavior of T3_HF. Compared to prior studies with a single band-limiting pole,T3_HF contains a pair of complex limiting poles (P1&P2) because the poles aremaximally extended near the vicinity of optimal design. The complex poles cangenerate excessive gain peaking when CL is small. Also as shown, the amplifieris functional from 0.7V to 1.8V supplies and the GBW is almost unchanged from0.9V to 1.8V supplies. The results verify the applicability of LEC to low-voltageapplications.

Figure 17.3.6 presents a performance summary. Compared with other works,LEC shows improved FOMS (1.07), FOML (2.15), LC-FOMS (2.87) and LC-FOML (4.08). The chip is fabricated using a 0.18m CMOS process with anarea of 0.007mm2.

References:[1] X. Peng, et al., Impedance adapting compensation for low-power multistageamplifiers, IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 445-451, Feb. 2011.[2] Z. Yan, et al., A 0.016mm2 144W three-stage amplifier capable of driving1-to-15nF capacitive load with > 0.95MHz GBW, ISSCC Dig. Tech. Papers, pp.368-370, Feb. 2012.[3] K.N. Leung, et al., Damping-factor-control frequency compensation technique for low-voltage low-power large capacitive load applications, ISSCCDig. Tech. Papers, pp. 158-159, Feb. 1999.[4] R.D. Middlebrook, Design-Oriented Analysis of Feedback Amplifiers, Proc.National Electronics Conference, vol. 20, pp.234-238, Oct. 1964.

978-1-4799-0920-9/14/$31.00 2014 IEEE

T=H2(Ro2 1 sCp2 )

(RL 1 sCL )+1 sCm2 +(Ro2 1 sCp2 )

GBW = gm1Cm1

gm22Cm2

gm33.2Cm3

gm45.2Cm4

gmL10.4CL

291DIGEST OF TECHNICAL PAPERS

ISSCC 2014 / February 11, 2014 / 2:15 PM

Figure 17.3.1: Simplified analysis method for simple Miller compensation(SMC) and nested Miller compensation (NMC).

Figure 17.3.2: Block diagrams of the three-stage amplifiers of [1], [2] and thiswork.

Figure 17.3.3: Bode plots of simplified high-frequency loop gain THF of theMiller feedback loop for [1], [2] and this work.

Figure 17.3.5: Measured AC (upper, left) and transient (upper, right) respons-es, load capacitance (lo