Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

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Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt

Transcript of Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Page 1: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Introduction to Wafer fabricationProcess

Presented byAsst.Prof. Dr. Rardchawadee Silapunt

Page 2: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Outlines

Clean room 1

Wafer Fab Process

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Page 3: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Outlines

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Clean room 1

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Clean Room @ TMEC

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Page 5: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

It took time to install cleanroom

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PLAY MOVIE

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Outlines

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Wafer Fab Process

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Page 7: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Processing line @ TMEC

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Furnace

Plasma CVD

PhotolithographyCleaning Process

Implanter

Dry EtchingSputtering

Metrology

Down to 0.5μm Technology

Page 8: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Overview to Lithography process

What is Lithography Process?

The word come from the Greek “Lithos” and “Graphia”

Lithos = Stones , Graphia = to write

It means “ Writing on stones”.

In Semiconductor, stones are Silicon wafers and our patterns are written with a light-sensitive polymer called “Photoresist”

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Page 9: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Overview to Lithography process

9 Steps of Lithography process.

1. Wafer preparation

2. Coat with Photoresist

3. Prebake, Softbake

4. Align and Exposure

5. Post-Exposure Bake (PEB)

8. Etch or Implant

6. Development

7. Postbake, Hardbake

9. Photoresist strip

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Page 10: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Photolithography Problem

Light Diffraction is occur during photolithography process.

OPC patterns are used to reduce the error in photolithography process.

(a) (b)

(c) (d)

Without OPC With OPC

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Page 11: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

How to patterning circuit

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Wafer

Processing - Film Deposition - Photolithography- Etching- Implantation

Integrated Circuit (IC)

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Processing line

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p-type wafer

p-type

Silicon Wafer

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Processing line

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Film Deposition

Initial oxidation: O2/H2 (Thickness: 420 nm)

p-type

SiO2

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Processing line

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p-type

Photoresist (PR)

Coater Stepper Developer

Photolithography

Page 15: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

PR is made up of a resin R, the photoactive compound M, the solvent S, and component appears during exposure which are exposure products P.

The exposure products generated by the reaction of M with UV light.!!

Applying Beer’s Law, the absorption coefficient is then,

M0 = initial PAC concentration (non-exposed)A = bleachable absorption coefficients of Dill parametersB = Non-bleachable absorption coefficients of Dill parameters

Other non-bleachable components of the PR such as dye are added to B

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Photoresist Characteristic

Processing line

Page 16: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

T(0)

T(∞)

Where several assumptions are made in solving this differential equation and I x t is the

optical dose. If D is the resist thickness, the Dill parameters can be measured by:

is the initial slope of the transmittance vs dose curve

is transmittance at theair-resist interface

Two transmittance curves for Kodak 820 resist 365 nm. The curves are for a convection oven post-apply bake of 30 minutes at the temperatures shown

T(0) is the transmittance of the unexposed resist, and

T(∞) is the transmittance of the completely exposed resist

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Processing lineDill Paramaters of Photoresist

Page 17: Introduction to Wafer fabrication Process Presented by Asst.Prof. Dr. Rardchawadee Silapunt.

Simulation of Plasma Etching

Processing line

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Etching

p-type

Dry etch oxidePhotoresist (PR)

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Processing line

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Etching

Isotropic Etch Directional Etch Vertical Etch

Directionality of Etcing Process

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Processing line

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Etching

Wet Etching

Two Kinds of Etching Method

Dry Etching- by Wet chemical solution- Isotropic etching

- by Plasma- Anisotropic etching

Vertical E/R ~ Horizontal E/R Pure Chemical Reaction High

Selectivity CD Loss or Gain

Vertical E/R >> Horizontal E/R Ion assisted Relatively low

Selectivity No CD bias

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Processing line

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Implantation

p-type

Photoresist (PR)

n-well implantation : Phosphorus

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CMP removes material from uneven topography on a wafer surface until a flat (planarized) surface is created.

CMP combines the chemical removal effect of an acidic or basic fluid solution withthe "mechanical" effect provided by polishing with an abrasive material.

Processing line

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Chemical Mechanical Planarization (CMP)

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Processing line

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How to patterning a CMOS !!!

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