Integrated Regulation for Energy-Efficient Digital Circuits

Elad Alon1 and Mark Horowitz2

1UC Berkeley2Stanford University

Technology (μm)

Scaling and Supply Impedance

• CMOS scaling led to lower supply voltages and constant (or increasing) power consumption

• Forces drastic drop in supply impedance• Vdd ↓, Idd ↑ |Zrequired| ↓↓

• Today’s chips:• |Zrequired| ≈ 1 mΩ!

• Hard to achieve across a broad frequency range

Re

qu

ired

Imp

eda

nc

e (Ω

)

Impedance Requirements of High-Performance Processors

0.10.20.30.40.50.6

10-3

10-2

10-1

100

Technology (m)

Req

uir

ed Im

ped

ance

()

Required Impedance vs. Technology for High-performance Microprocessors

Power Distribution and Regulation

• Significant resources spent to meet impedance requirement

• Active regulation can be used to reduce impedance• E.g., Active/switched decoupling

• But, these regulators increase total power• Prevents adoption in today’s power-limited chips

Power-Neutral Regulation

• Gate delay depends on Vdd

• So Vdd needs to be greater than some Vmin

• Supply variations force higher nominal voltage• Causes extra power dissipation

• Goal: make regulator power less than power recovered from lower noise

Vmin

Vnom

Vdd

Outline

• Regulator Topology

• Regulator Design

• Experimental Verification

• Conclusions

Linear Regulators

Vdd LoadVreg

Chip

+

-

+- Vref

Series Regulator

LoadVreg

Chip

+

-

+- Vref

Shunt Regulator

Vdd

Series Regulator Efficiency

• Clearly won’t meet efficiency goal:• Regulator doesn’t really change noise on Vdd

• So still need same margin

• But added an extra Vdrop from variable resistor…

+

-

Vref

Load

Vdd

Vreg

Vdd

Vreg

Vdrop

Noise

Shunt Regulator Efficiency

• Regulator can only pull current out of supply • Need to burn significant static current to counter

noise in both directions• Again, clearly inefficient

• Need to allow shunt to deliver energy to the load• Not just dissipate it

Load

+

-Vref

Vreg

Ishunt

Ishunt

Itotal

Iload

0

max(Inoise)

max(Inoise)

Push-Pull Shunt Regulator

• Use an additional, “shunt” supply to push current into Vreg

• Regulator capable of countering large variations• But regulator loss set mostly by average variation

• Similar to Active Clamp* for board VRMs• Build on previous work to improve on-die impedance

Load

+

-

Vref

Vreg

Vshunt

+-

Ipush

Ipull

Ipush

Iload

0

Ipull

*A.M. Wu and S.R. Sanders, “An Active Clamp Circuit for Voltage Regulation Module (VRM) Applications,” Transactions on Power Electronics. Sept. 2001.

Outline

• Regulator Topology

• Regulator Design• Shunt Supply Network• Minimizing Static Power

• Experimental Verification

• Conclusions

Regulator Design Challenges

• Vshunt is not free• Takes resources away

from main supply

• Increases lossLoad

+

-

Vref

Vreg

Vshunt

+-

Ipush

Ipull

• Need to minimize quiescent output current• Otherwise regulator too inefficient

• Need GHz bandwidth feedback path• With minimum feedback circuit power• Output stage in particular is challenging

Shunt Supply Resource Allocation

• Finite number of pins, metal lines for power• Need to allocate resources between main and shunt supplies

• For resistive losses:

• If ensure that Vshunt only handles transients• Resistive losses of main supply not heavily affected

Vdd Vss Vdd Vss Vdd Vss Vdd Vss Vdd Vss Vshunt Vss Vdd Vss Vshunt Vss

,shunt loadshunt main

load shunt load shunt

I Ip p

I I I I

Quiescent Output Current

• Went to push-pull topology to minimize quiescent current• But many designs have significant Istatic

• To ensure output devices are off when Vreg is quiet

• Use non-linear switching to control the output stage

Vref

Vgn

Vgp

Vshunt

Vreg

Istatic

Comparator Feedback with Dead-Band

• Use comparators in feedback path to generate full-swing drive signals

• To avoid limit cycle:• Offset thresholds to

create dead-band

Vshunt

Vreg

vVref-V

+

-

+

-

vVrefV

Ipush

Ipull

Output Stage Design

• Needs good supply rejection• Vshunt will be noisy

• Needs to burn minimal static power• To meet efficiency goal

• Requirements on output stage:

• Needs low td,on

• To maintain voltage- positioned response

Vshunt

Vreg

vVref-V

+

-

+

-

vVrefV

Ipush

Ipull

td,on

Replica Biased Output Stage

• Replica loop sets gate bias (Vbias)

• Minimal current spent in feedback amplifier for efficiency• High impedance amp – add buffer between Vbias and

switching node

Switched Source Follower Buffer

• Source follower Mp_sf used to isolate Vbias

• Turned on only when pushing current

• But, waiting for Isf to charge Vgn too slow

• Mp_up turned on during transition

Ibuf

Vgn

Outline

• Regulator Topology

• Regulator Design

• Experimental Verification

• Conclusions

Test-Chip Details

• 65nm SOI AMD test-chip

• Regulator uses same power distribution scheme as processor• With reallocation for Vshunt

• On-chip noise generator and perf. monitor for testing Regulator

Circuits Scan/Config.

Processor

Measured Results

• Regulator reduces broadband noise by ~30%• Total power dissipation actually reduced by

up to ~1.4%

6 8 10 12 14

5

10

15

20

25

30

35

Unregulated Supply Noise (%)

No

ise

Red

uct

ion

(%

)

6 8 10 12 14

0.82

0.84

0.86

0.88

0.9

0.92

0.94

Eff

icie

ncy

Unregulated Supply Noise (%)

UnregulatedRegulated

Impedance with Faster Process

• Process was in development• Low device ft

• Measurement matches simulation with slower devices

107

108

109

1010

-50

-40

-30

-20

-10

0

Frequency (Hz)N

orm

aliz

ed Im

ped

ance

(||Z

||/R lo

ad)

Production processTest-chip processUnregulated

• Expect to reach ~50% noise and ~4% power reduction in production process with higher ft

Outline

• Regulator Topology

• Regulator Design

• Experimental Verification

• Conclusions

Conclusions

• To be adopted, on-chip regulation must not increase total power

• Can in fact build power-neutral regulator• Push-pull topology with second supply• Switched source-follower output stage

• Measured 30% noise reduction with no power penalty• In fact, reduced power by ~1.4%

Acknowledgements

• This work was funded in part by C2S2 (www.c2s2.org)

• AMD Sunnyvale Design Center