IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30,...

8
IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays BRYAN D. AGKLAND, MEMBER, IEEE, AND NEIL H. WESTE, MEMBER, Abstract—Contour (polygon)fillingis a primitive required in many application areas of raster scan graphics. The bit-map memory in a frame-store display is computationally well suited to this task, as it provides a large scratch pad working space. In this paper, a number of contour filling algorithms based on the read/write properties of the frame-store memory are compared with the classical "ordered-edge- list" approach. Performance is evaluated on a microcomputer con- trolled frame-store display system in terms of ability to fill correctly, execution speed and processor memory requirements. A new algorithm, based on a more exact definition of an object edge, is presented. This algorithm, denoted edge flag algorithm, is implemented within the frame-store memory. It features high speed, in conjunction with minimal CPU memory requirements, making it ideally suited to hardware or microcode (firmware) implementation. Index Terms—Animation, filled colored shapes, frame-store, graphics, polygon fill, raster scan. I. INTRODUCTION R ASTER scan display systems have used a base of tele- vision display technology and decreasing memory prices to arrive at a position of high importance in information display systems. One of the most popular ways to electronically gen- erate images on this raster is to use a frame-store memory which essentially stores a television frame in digital form. The capability to represent filled colored shapes is an attribute which sets the frame-store display apart from most other graphic display systems. The generation of these filled shapes from simple outline descriptions is thus a key task, finding application in such areas as computer aided design, cartoon animation, 2 -D and 3 -D scene construction, information dis- play, and TV games. The classical approach to contour filling [1] is to process a set of polygon edge lists in scan-line order, and from these, derive a set of interior horizontal line segments which are plotted to the screen. All processing is done within the host computer-independent of the display device. With the inclusion of a read/write frame-store memory, much of the processing (sorting) involved in contour filling can be elimi- nated by using the frame store as a working data memory. Algorithms in this class typically plot a conventional vector outline into a single-bit plane of the frame store known as a "working plane." Filling is then completed by processing the plane as though it were a large array. In this case, most of the execution time is spent interrogating portions of the working Manuscript received October 23, 1979; revised February 29, 1980 and May 29, 1980. The authors are with the Image Processing and Display Research Group, Bell Laboratories, Holmdel, NJ 07733. plane to supply the algorithm with sufficient information to distinguish between a true edge, an already filled interior, and artifacts of the line drawing algorithm. This paper describes some existing contour filling algorithms and examines their suitability in terms of various frame-store architectures. Performance is compared in terms of execution speed and memory requirements as measured on an existing microcomputer controlled frame-store display system. A new contour filling algorithm denoted "edge flag," based on frame-store interrogation, is proposed. The algorithm features high-speed, in conjunction with, minimal CPU memory re- quirements, making it particularly suitable for hardware or firmware implementation. A specific firmware implementation using a bipolar bit slice interpreter is described. By suitably matching this new algorithm to high performance frame-store hardware, plotting speeds necessary for real-time animation have been attained. II. SOME EXISTING FILL ALGORITHMS A. Ordered Edge List {OEL) As mentioned previously, the classical approach to contour (polygon) filling is span 1 generation from a set of ordered edge lists [1]. The algorithm proceeds in scan-line order, adding and/or deleting entries from an "active edge list"—a table of those edges which intersect the current scan line. Based on results from the previous line, a difference equation is used to evaluate the intersection point of each active edge with the current scan line. These intersection points are then ordered by increasing jt-value to produce a set of interior spans which are plotted into the frame-store memory on the current scan line. An alternative approach is to first decompose each polygon into a set of trapezoids or triangles [2], [3]. This adds a further processing overhead, but resolves each polygon into convex shapes. This can considerably reduce the amount of edge sorting, since only one span is active for any given scan line per polygon. The main advantage of the OEL approach is that all pro- cessing is done within the host computer making the system display device independent. In addition, each active pixel (picture element) is visited only once. This is important in re- 1 A span is defined as a horizontal line segment bounded by two screen end points. 0018-9340/81/0100-0041S00.75 © 1981 IEEE

Transcript of IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30,...

Page 1: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41

The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

B R Y A N D . A G K L A N D , M E M B E R , IEEE, A N D N E I L H . W E S T E , M E M B E R , ΙΕΕΕ

Abstract—Contour (polygon) filling is a primitive required in many application areas of raster scan graphics. The bit-map memory in a frame-store display is computationally well suited to this task, as it provides a large scratch pad working space. In this paper, a number of contour filling algorithms based on the read/write properties of the frame-store memory are compared with the classical "ordered-edge-list" approach. Performance is evaluated on a microcomputer con­trolled frame-store display system in terms of ability to fill correctly, execution speed and processor memory requirements. A new algorithm, based on a more exact definition of an object edge, is presented. This algorithm, denoted edge flag algorithm, is implemented within the frame-store memory. It features high speed, in conjunction with minimal CPU memory requirements, making it ideally suited to hardware or microcode (firmware) implementation.

Index Terms—Animation, filled colored shapes, frame-store, graphics, polygon fill, raster scan.

I. I N T R O D U C T I O N

RASTER scan display systems have used a base of tele­vision display technology and decreasing memory prices

to arrive at a position of high importance in information display systems. One of the most popular ways to electronically gen­erate images on this raster is to use a frame-store memory which essentially stores a television frame in digital form. The capability to represent filled colored shapes is an attribute which sets the frame-store display apart from most other graphic display systems. The generation of these filled shapes from simple outline descriptions is thus a key task, finding application in such areas as computer aided design, cartoon animation, 2 - D and 3 - D scene construction, information dis­play, and TV games. The classical approach to contour filling [1] is to process a set of polygon edge lists in scan-line order, and from these, derive a set of interior horizontal line segments which are plotted to the screen. All processing is done within the host computer-independent of the display device. With the inclusion of a read/write frame-store memory, much of the processing (sorting) involved in contour filling can be elimi­nated by using the frame store as a working data memory. Algorithms in this class typically plot a conventional vector outline into a single-bit plane of the frame store known as a "working plane." Filling is then completed by processing the plane as though it were a large array. In this case, most of the execution time is spent interrogating portions of the working

Manuscript received October 23, 1979; revised February 29, 1980 and May 29, 1980.

The authors are with the Image Processing and Display Research Group, Bell Laboratories, Holmdel, NJ 07733.

plane to supply the algorithm with sufficient information to distinguish between a true edge, an already filled interior, and artifacts of the line drawing algorithm.

This paper describes some existing contour filling algorithms and examines their suitability in terms of various frame-store architectures. Performance is compared in terms of execution speed and memory requirements as measured on an existing microcomputer controlled frame-store display system. A new contour filling algorithm denoted "edge flag," based on frame-store interrogation, is proposed. The algorithm features high-speed, in conjunction with, minimal C P U memory re­quirements, making it particularly suitable for hardware or firmware implementation. A specific firmware implementation using a bipolar bit slice interpreter is described. By suitably matching this new algorithm to high performance frame-store hardware, plotting speeds necessary for real-time animation have been attained.

II. S O M E E X I S T I N G F I L L A L G O R I T H M S

A. Ordered Edge List {OEL)

As mentioned previously, the classical approach to contour (polygon) filling is span 1 generation from a set of ordered edge lists [1]. The algorithm proceeds in scan-line order, adding and/or deleting entries from an "active edge list"—a table of those edges which intersect the current scan line. Based on results from the previous line, a difference equation is used to evaluate the intersection point of each active edge with the current scan line. These intersection points are then ordered by increasing jt-value to produce a set of interior spans which are plotted into the frame-store memory on the current scan line.

An alternative approach is to first decompose each polygon into a set of trapezoids or triangles [2], [3]. This adds a further processing overhead, but resolves each polygon into convex shapes. This can considerably reduce the amount of edge sorting, since only one span is active for any given scan line per polygon.

The main advantage of the O E L approach is that all pro­cessing is done within the host computer making the system display device independent. In addition, each active pixel (picture element) is visited only once. This is important in re-

1 A span is defined as a horizontal line segment bounded by two screen end points.

0018-9340/81/0100-0041S00.75 © 1981 IEEE

Page 2: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

4 2 IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981

ducing execution time where I / O transfer time is a limiting factor. Ordered edge list filling is ideally suited to smooth shaded picture rendition, since both ends of a span are com­puted before the span is drawn and hence, intensities between endpoints may be interpolated according to some shading al­gorithm.

A disadvantage of this technique is the large amount of processing involved in maintaining and sorting the various lists. This can be expensive in terms of execution time and memory requirements—especially when the number of edges (vertices) is large. Nonpolygonal contours are generally not catered for because of the difficulty associated with including the contour drawing process as an integral part of the filling algorithm.

B. Seed Fill

Much of the processing described above can be eliminated by allowing the computer to use the frame store as a working memory. In the seed-fill algorithm [4], [5], a connected con­tour of the shape to be filled is first drawn into the working plane of the frame store. A seed point, known to be in the in­terior of the shape, is then selected. The algorithm then de­termines the extent of the figure by continually examining points adjacent to known interior points. As interior points are identified, they are filled in the working plane. Providing filled points (boundaries) are not crossed, the algorithm will always remain inside the object being filled.

Points are typically examined in a series of horizontal scans (although any comprehensive scan sequence could be used) to minimize the amount of software record keeping. In order to guarantee connectivity in complex shapes, a stack is main­tained which records those portions of the contour not yet filled. Once the process is complete, the filled shape is copied from the working plane into the bit planes needed for the specified color. Alternatively, if the hardware permits, the interior may be plotted directly to the appropriate bit planes as it is being constructed in the working plane.

Advantages of seed filling include reduced processing in the host computer and the ability to fill any arbitrary planar connected contour (i.e., not limited to polygons). Execution time is limited, however, by the large amount of I / O transfer to the frame store. Some pixels are visited many times— especially in complex shapes. In addition, the algorithm is essentially pixel based and does not readily take advantage of frame-store bandwidth improvements (see Section VI). A serious drawback of seed filling is the need to find an initial interior point. While this presents no problem in an interactive situation, in the general case, some other form of contour filling algorithm must be invoked in order to supply this initial seed point. A further disadvantage is the catastrophic failure of the algorithm in the event of a memory read error. This often results in the filling of the entire screen. Nonplanar (inter­secting) shapes must be filled by supplying a separate seed point for each disjoint interior region. Note that some mathematically planar shapes can be rendered nonplanar by the quantizing effect of the frame-store display. An example of this is shown in Fig. 1. Here the intersecting angle of two vectors is so acute that one pixel has been isolated by the dig­itized vector representation.

ISOLATED PIXEL

Fig. 1. Nonplanar distortion caused by quantization.

C. Parity Check

Another type of fill algorithm based on frame-store inter­rogation uses what is termed a parity check to determine the interior of a contour drawn in the working plane. A pixel is assigned to the interior of the shape if a line drawn from that pixel to the boundary of the screen intersects the contour an odd number of times. Problems arise due to the quantizing effect of the frame-store representation in determining just what constitutes an intersection with the contour.

Pavlidis [6] describes a number of parity check algorithms of varying complexity, ranging from a trivial parity check which fails on most polygons, to a detailed two-pass check which, it is claimed, always fills correctly. In particular, he describes an algorithm designated A3, in which the area en­compassing the contour is searched in scan-line order, each contour/line segment being compared with intervals above and below to determine the local properties of the contour. A set of labels is used to mark each interval, and these in turn de­termine whether or not the parity count should be incremented. As with seed filling, the filled contour can either be copied from the working plane at the completion of the algorithm or plotted directly to the appropriate bit planes as the fill proceeds.

Advantages of parity check filling include the ability to fill arbitrary connected contours, even nonplanar shapes like the one shown in Fig. 2. Unfortunately, most algorithms of this class fail under certain pathological conditions due to am­biguities in determining the true position of an edge from a frame-store contour. The mode of failure depends on the exact nature of the algorithm, but is usually less severe than that which occurs when seed filling. Like seed filling, the algorithm is generally pixel-based and, therefore, spends most of its time interrogating the frame store. As mentioned previously, this can degrade performance where display I / O time is a limiting factor.

III. E D G E FILL

Both seed-fill and parity-check algorithms begin with a conventional outline drawing assuming this to be an adequate representation of the contour to be filled. In actual fact, a line drawing is a very poor representation of the edge of a two-dimensional object. There is a fundamental difference between a pixel-based line and true edge, viz. a line has finite width (= 1 pixel), whereas an edge is a mathematical boundary having zero width. Using a line drawing to represent the boundary of a filled shape inevitably leads to ambiguities. Consider, for example, the rectangle shown in Fig. 3(a). It has coordinates (0, 0), (3, 2). An outline representation of this rectangle consists of the four vectors (0, 0), (3, 0); (3, 0), (3, 2); (3, 2), (0, 2); and (0, 2), (0, 0). If this outline is filled, as

Page 3: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

ACKLAND AND WESTE: EDGE FLAG A L G O R I T H M — F I L L METHOD 4 3

PIXEL (A,B)

Fig. 2. Example of a nonplanar polygon.

0 1 2 3 4 (b)

Fig. 3. Conventional pixel/coordinate representation.

shown in Fig. 3(b), the result is a rectangle having an area of 12 square units—even though the original rectangle has a mathematical area of only 6 square units. Note that this in­consistency is not caused by quantization effects—all the coordinates were whole integers. Rather, it is a symptom of using a pixel of finite area to represent a mathematical coor­dinate.

Suppose we modify the coordinate system so that an integral coordinate value represents a line passing between rows or columns of pixels rather than through them. This is shown in Fig. 4(a). A convention is adopted whereby pixel (a, b) is that pixel immediately to the right and above coordinate position (a, b). The rectangle (0 ,0 ) y (3,2) now appears as shown in Fig. 4(b). Note that its display area is now 6 square units—con­sistent with the mathematical description.

Edge fill is a technique whereby a parity-check type algo­rithm is used in conjunction with the above coordinate system to achieve filling directly from the mathematical description of the contour. As with seed-fill and parity-check techniques, the filled shape is first generated in a frame-store working plane and then copied into the appropriate bit planes. A statement of the algorithm is as follows:

FOR each edge DO BEGIN

FOR each scanline intersecting the edge DO BEGIN

complement all pixels whose midpoint lies to the right of (has an χ value greater than) the intersection point

END END

Β + 2

B«M

Β

B - 1

m -CO-ORDINATE

PAIR (A,B)

A - 1 A A + 1 A+2 (a)

0 1 2 3 4 (b)

Fig. 4 . Modified coordinate system.

( A )

(C )

Fig. 5. Example of edge fill in progress.

Fig. 5(a) - (d) shows the various stages in the filling of a simple triangle. The algorithm correctly fills any connected contour. Edges may be straight lines (as in the case of a poly­gon) or any other continuous function (e.g., conic, spline curve). The only CPU processing involved in filling a shape is the generation of the outline contour. By processing each edge in an incremental fashion, integer arithmetic techniques [7] can be used to simply define complex mathematical shapes. Use of integer arithmetic also allows simple difference equation processors to be built to implement a wide range of outline functions in hardware. In addition, the algorithm requires no data storage making it well suited to microcode implementa­tion.

A disadvantage of edge filling as described above is that shapes having many edges crossing the same scanline cause

Page 4: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

44 IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981

some pixels to be visited many times in the course of filling. This limits execution speed, since the algorithm tends to be I / O bound (host computer processing having been reduced to a minimum). Performance can be further improved by only complementing one pixel per edge/scan intersection and using the "working plane to color plane copy" routine to complete the fill. This algorithm, referred to as edge flag filling is stated as follows.

ft 1 2 3 4 5 6 7 8 9 10 11 12

(a) 9 10 11 12

A. Outline Contour

FOR each edge D O BEGIN

FOR each scanline intersecting the edge D O BEGIN

complement the left-most pixel whose midpoint lies to the right of (has an χ value greater than) the intersection point

E N D E N D

B. Fill

FOR each scanline intersecting the polygon D O BEGIN

inside: = FALSE FOR χ == 0 (left) to JC = xmax (right) D O BEGIN

IF scanline (x) is set T H E N negate inside IF inside T H E N set scanline (JC) in color planes ELSE reset scanline (x) in color planes

E N D E N D

Note that this algorithm is very similar to conventional parity-check routines. The difference lies in the generation of an unambiguous contour which requires the most trivial parity check to accomplish correct filling. Fig. 6 shows a simple parity check technique being used to fill the triangle (0,2) , (8,7) , (11, 0) from two different outline representations. Errors caused by using parity fill in conjunction with a conventional vector outline are shown in Fig. 6(a). The same contour is parity filled in Fig. 6(b) using the edge flag algorithm together with the modified coordinate system.

Note that although every pixel has to be visited at least once, the definition phase of the polygon is proportional to the cir­cumference of the shape. This has particular benefits if the fill portion can be completed automatically.

IV. P E R F O R M A N C E T E S T S

In order to evaluate their relative performance, both in terms of execution speed and memory requirements, some of these contour filling algorithms were implemented on an existing frame-store display system shown in Fig. 7. The system consists o f a 5 1 2 X 5 1 2 X 8 frame-store connected to a color monitor via a 1Κ X 24 bit color map. One plane of the frame store has been designated as a working plane—the other seven being used to generate 128 colors out of a possible 2 2 4 . The frame-store display is supported by a stand-alone LSI-11 micro-

0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 1£ 13

( C ) (d)

Fig. 6. (a) Attempted parity fill based on conventional vector outline, (b) Parity fill using edge flag technique.

512X512X8 COLOR FRAME STORE MONITOR

t t DISPLAY COLOR

PROCESSOR MAP

TO OTHER g Ζ t » P E R I P H E R A L S * f * Q - B U S

L S I - 1 1 BIT-PAD 28Κ MEMORY (DATA TABLET)

Fig. 7. Display system.

computer running LSX (a single user version of the Bell Sys­tem U N I X . 2 Among the peripherals connected to the LSI-11 is a data tablet used for interactive picture generation.

Comparison of the various filling techniques was based on four test pictures shown in Fig. 8 (a ) - (d ) . The first is a simple triangle of large area. The second is a more complex figure having about 40 vertices including reentrant sides. The third is an example of the use of many sided polygons to give fine detail. The last is a more complex picture consisting of many polygons-about 900 vertices in all. More detail is given in Table I.

Parameters measured were 1) the ability to correctly fill, 2) execution time, and 3) host computer memory requirements. All algorithms were coded in the C programming language.

V . R E S U L T S

As mentioned previously, different algorithms work opti­mally with differing hardware configurations. The hardware system shown in Fig. 7 supports two modes of addressing the frame store-word access and pixel access. In pixel access mode, each pixel is read or written separately with the ability to op-

2 UNIX is a Bell Laboratories' operating system.

Page 5: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

ACKLAND AND WESTE. EDGE FLAG A L G O R I T H M — F I L L METHOD 4 5

(c)

Fig. 8. Test pictures, (a) TEST 1.

erate on more than one color plane at a time. In word access mode, 16-bit word transfer is used—one word representing 16 horizontally contiguous pixels in one plane. All the algorithms described in Sections II and III are capable of using pixel ac­cess. Some, but not all, gain significant advantage from the word access mode. To ensure a fair comparison, it was decided to initially compare all algorithms using pixel mode only. This maximizes I / O transfer which in turn tends to slow down working plane based routines.

Table II compares execution time for five different algo­rithms based on the four test pictures. For these algorithms which fill a colored shape in two steps (fill in working plane then copy to bit planes), a second (bracketed) figure represents fill time only. All algorithms correctly filled TEST1-TEST3 . Parity check failed on some of the polygons contained in TEST4 while seedfill failed catastrophically due to incorrect seed point selection.

Results show that under these conditions, the ordered edge list (classical) approach gives the shortest fill time—it being the only algorithm guaranteed to visit each pixel only once. This indicates that I / O transfer time is masking the effect of processing complexity. The seed fill and parity check routines are six-eight times slower than the ordered edge list—even when working plane copy time is not included. Edge fill is also slow, but much of its time is-spent in working plane copy. Note that on TEST1 and TEST3, the fill time of the edge fill routine is not much greater than that of the ordered edge list. Note also, however, that edge fill breaks down on TEST2 where a large number of vertical reentrants cause this algorithm to visit some pixels many times. The edge flag technique shows con­siderable improvement over edge fill, especially for more complex pictures.

Table III shows the amount of program space occupied by

(d)

TEST 2. (c) TEST 3. (d) TEST 4 .

T A B L E I T E S T PICTURE DATA

TEST1 TEST2 TEST3 TEST4

Total

Number of

Vertices

3 40 82 900

Number

of

Polygons

1 1 1 21

each routine, while Table IV shows data storage requirements for the four test pictures. Memory requirements may not be a limiting factor in a large host but are extremely important when considering microcode implementation. As expected, the ordered edge list algorithm requires a significant amount of memory space—especially the fill routine which does the sorting. Note that additional data storage space is required to hold the edge lists. The seed fill algorithm shows some im­provement, but once again, significant data storage may be required to successfully fill complex shapes. The parity check filler uses the most code which is also reflected in its execution time. Clearly, the complexity of the pixel interrogation routines used in this algorithm outweighs any gain achieved by elimi­nating the sort process.

Both the edge fill and edge flag algorithms show greatly reduced code requirements with no data storage overhead. The fill routine requires only 300 bytes of compiled code and is, therefore, a possible candidate for microcode implementa­tion.

Page 6: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

4 6 IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981

T A B L E II PIXEL A C C E S S EXECUTION T I M E

Execution

Time (sec) TEST1 TEST2 TEST3 TEST4

Seed Fill 69.6 (50.0) 90.6 (65.8) 94.3 (69.6) -

Ordered

Edge-List

8.2 12.0 12.9 17.9

Parity Check

(A3)

76.5 (56.6) 78.0 (56.6) 95.0 (70.3) 112.3

Edge-Fill 28.4 (8.8) 70.2 (49.7) 44.9 ( 20.2) 52.0

Edge-Flag 17.5 19.0 22.5 24.5

T A B L E III CODE MEMORY R E Q U I R E M E N T S (BYTES)

BYTES

LOADED HEADER FILL I/O

WORKING

PLANE COPY TOTAL

Seedfill 290 728 - 188 1206

Ordered

Edge-Li st

136 1588 36 - 1760

Parity Check

(A3)

200 2064 188 2452

Edge-Fill 132 300 188 620

Edge-Flag 132 280 - 198 610

V I . H A R D W A R E O P T I M I Z A T I O N

The results discussed in Section V were all obtained by re­stricting the algorithms to pixel access mode, i.e., transferring only one pixel per 1 / O operation. Seed filling and parity check are essentially pixel based routines and therefore not likely to gain from any hardware optimization. Ordered edge list filling generates horizontal spans and can, therefore, take advantage of the horizontal word structure of the frame store. Even greater speedup can be obtained by using a hardware span generator. The two edge filling routines are also well suited to use word access mode since pixel interrogation is highly or­dered.

To illustrate this effect and compare these two classes of filler under hardware matched conditions, further results were taken as shown in Table V . This time, edge flag speed was measured operating with word access I / O and the ordered edge list routine had the use of a hardware span generator—a special purpose hardware vector generator used for drawing horizontal segments on a single scan line. Note the enormous speedup compared to the results presented in Table I I . Both these algorithms show similar execution times—the ordered

T A B L E IV DATA M E M O R Y R E Q U I R E M E N T S (BYTES)

BYTES

USED TEST1 TEST2 TEST3 TEST4

Seed-fill 8 24 40 20

Ordered 66 880 1800 1800

Edge-List

Parity Check 2624 2624 2624 2624

(A3)

Edge-Fill 0 0 0 0

Edge-Flag 0 0 0 0

T A B L E V H A R D W A R E M A T C H E D EXECUTION TIN

Execution

Time (sec) TEST1 TEST2 TEST3 TEST4

Ordered 0.9 2.43 2.72 10.4

Edge-List

Edge-Flag 1.79 2.97 2.46 6.2

edge list being the better for simple shapes of large area. For more complex shapes, however, processing time becomes im­portant and the edge flag algorithm yields the faster result.

As described in Section III, the edge flag algorithm consists of two parts—an unambiguous contour generation followed by a simple parity fill. The parity fill can actually be imple­mented in hardware directly on the video stream as shown in Fig. 9. Execution times measured using this direct hardware fill approach are given in Table VI. As previously mentioned, the time to define each polygon with edge flag is proportional to the outline distance, the fill being a rather mechanical ex­ercise completed each frame. This is in contrast to a depen­dence on the area of a polygon in all other algorithms.

VII. M I C R O C O D E I M P L E M E N T A T I O N

The speed and efficiency of the edge flag algorithm make it suitable for direct microcode implementation in a raster scan graphics processor. This technique has been used to generate polygon fill routines for G U M B I [8]—a Graphic User Mi-croprogrammable Bit-Slice Interpreter developed at Bell Laboratories as a front-end processor for frame-store display systems. GUMBI functions as a hardware interpreter—ac­cepting high-level commands from a general purpose host and converting these into basic frame-store picture manipulation operations. It is a horizontally microcoded machine, designed around the AMD2900 series of bit-slice microprocessor components and runs with a microinstruction cycle time of 200 ns.

Page 7: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

ACKLAND AND WESTE: EDGE FLAG ALGORITHM—FILL METHOD 4 7

FILL ν MODE^

COLOR PLANE

FRAME-STORE VIDEO

VIDEO. CLOCK

D 0

Τ H-SYNC

Fig. 9. Hardware parity fill.

.VIDEO OUT

and no data storage requirements, making it ideally suited to microcode implementation in a graphics processor. In addition, a generalized version may form the basis for an LSI circuit implementation, especially if a difference processor was in­cluded. In applications where shapes do not overlap (e.g., IC layout) a further increase in speed can be obtained using a hardware parity fill in conjunction with a firmware contour generator. This approach has yielded speeds suitable for real-time animation.

R E F E R E N C E S

TABLE VI EDGE FLAG H A R D W A R E FILL

Execution

Time (sec) TEST1 TEST2 TEST3 TEST4

Edge Flag 0.24 0.35 0.25 2.45

T A B L E VII EDGE FLAG-FIRMWARE H A R D W A R E FILL

Execution

Time (ms) TEST1 TEST2 TEST3 TEST4

Edge Flag 2.3 5.3 6.5 155

[1] W. Newman and R. Sproull, Principles of Interactive Computer Graphics. New York: McGraw-Hill, 1973.

[2] C. W. Reynolds, "A multiprocessor approach to computer animation," Undergrad. Thesis, Dep. Elec. Eng. and Comput. Sci., Mass. Inst. Technol., Cambridge, Aug., 1975.

[3] W. D. Little and R. Heuft, "An area shading graphics display system," IEEE Trans. Comput. vol. C-28, pp. 528-531, July 1979.

[4] A. R. Smith, "Paint," NY Inst. Tech., Comput. Graphics Lab., Tech. Memo 7, July 1978.

[5] H. Lieberman, "How to color in a coloring book," Comput. Graphics, vol. 12, pp. 111-116, Aug. 1978.

[6] T. Pavlidis, "Filling algorithms for raster graphics," Dep. Elec. Eng. and Comput. Sci., Princeton Univ., Princeton, NJ, Rep. 238, Jan. 1978.

[7] J. Raamot, "Microprocessor applications of integer arithmetic," Proc. IEEE, vol. 66, pp. 238-244, Feb. 1978.

[8] N. Weste and B. Ackland, "GUMBI-A graphic user microprogrammable bit-slice interpreter," in Proc. COMPCON Fall, Washington, DC, Sept. 1979, pp. 232-237.

Table VII lists execution speeds for the four test pictures of Fig. 8. These results were obtained using firmware outline contour generation in conjunction with hardware parity fill. 504 bytes of microcode were required to implement the contour generation in this manner.

The results of Table VII are particularly significant in that they show simple polygonal filled shapes being drawn in less than one raster scan frame period (30 ms). Here is a hard­ware/software structure capable of doing simple real-time animation on a color frame store display system.

VIII. C O N C L U S I O N S

The classical ordered-edge-list filler and several algorithms based on frame-store interrogation have been compared in terms of execution speed and host memory requirements. Results have shown that fill time tends to be dominated by pixel I / O transfer time making the OEL the most attractive approach. A new algorithm (edge flag), based on a more fundamental description of an object edge, has been described. This technique gives a performance comparable to O E L without the associated processing overheads.

Both the OEL and edge flag algorithms benefit considerably from hardware optimization. This emphasizes the need to match the software/hardware combination. Note that there are differences in execution speed of up to 50:1 between Table II and Table V.

The edge flag algorithm offers high speed, minimal code,

4) Ψ

Bryan D. Ackland (S'77-M'78) was born in Ade­laide, Australia, on February 13, 1952. He re­ceived the B.Sc. degree in physics from Flinders University, South Australia in 1972 and the B.E. and Ph.D. degrees in electrical engineering from the University of Adelaide, South Australia in 1975 and 1979, respectively.

From 1971 to 1972 he was an experimental offi­cer in the Underwater Detection Systems Group at Weapons Research Establishment, Salisbury, South Australia. His doctoral research was con­

cerned with the effective use of cache memory hierarchies in small high-speed computers. From 1977 to 1978 he participated in the formation of Micro­computer Systems Design—a small business producing frame-store terminals. In 1978 he joined Bell Laboratories as a member of the Technical Staff in the Image Processing and Display Research Group at Holmdel, NJ. His current interests include raster graphics, small machine architecture, and integrated MOS design.

Dr. Ackland is a member of the IEEE Computer Society.

Neil H. Weste (S'76-M'77) was born in Renmark, South Australia, on April 12, 1951. He received the B.Sc. degree in 1973, the B.E. (Elec.) degree in 1974, and the Ph.D. degree in electrical engineer­ing in 1978 from the University of Adelaide, South Australia.

In 1977 he joined the Image Processing and Display Research Department of Bell Laborato­ries, Holmdel, NJ as a member of the Technical Staff. He commenced research on new display ar­chitectures for visual services and CAD related

Page 8: IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1… · IEEE TRANSACTIONS ON COMPUTERS, VOL. C-30, NO. 1, JANUARY 1981 41 The Edge Flag Algorithm—A Fill Method for Raster Scan Displays

48 IEEE T R A N S A C T I O N S ON C O M P U T E R S , VOL. C-30, N O . 1, J A N U A R Y 1981

problems and IC design aid systems. His present interests include structured high-level language VLSI design automation systems, architectures, and al­gorithms for special purpose processors, VLSI circuit design, raster graphics, and herpetology. His Ph.D. dissertation covered the implementation of a color display based IC design station for MOS design. The thesis covered the fields of color display architecture, design aid software, and the design of linear MOS

op-amps. During his Ph.D. candidature, he spent a total of nine months at the University of Edinburgh, Scotland, designing linear MOS op-amps for CCD signal processing applications and consulting on this subject to the Wolfson Microelectronics Liaison Unit. The result of the raster-scan display research led to the formation of a business (Microcomputer Systems Design) to man­ufacture microprocessor controlled frame store displays.

Dr. Weste is a member of the IEEE Computer Society.

Measuring Designer Performance to Verify Design Automation Systems

DONALD E. T H O M A S , M E M B E R , I E E E , A N D D A N I E L P. S IE WIO R E K , M E M B E R , I E E E

Abstract—Design automation at the register transfer level of design is still in its infancy, and it is not yet completely understood what the appropriate measures used in directing the automated design process should be. To establish these measures, results of these design auto­mation systems must be compared with some near optimal designs. A set of statistically based experiments is developed to estimate near optimal designs. A method is demonstrated for gathering data on de­signer performance, specifically at the different levels of systems de­sign, and in general, for calibration of other design automation systems where the intuitive designer still performs more capably than the present design algorithms. An analysis of variance is used to indicate the relative importance of various decisions in a system design. It is shown that the algorithm to be implemented and the hardware design style account for 90 percent of the variation in the results. Thus, se­lecting the design style (e.g., distributed, microprocessor, pipelined, etc.) is the most important parameter for a design automation system.

index Terms—Analysis of variance, design automation, design of experiments, design styles, register transfer level design.

I . I N T R O D U C T I O N

COMPUTER-aided design (CAD) systems have reduced the time and cost of the design process by making a

computer perform many of the routine and often mundane tasks of logic design. Historically, such systems were limited to bookkeeping and consistency checking. Occasionally, op­timization techniques for combinatorial logic (e.g., Quine-McCluskey [1 ]) were incorporated into these systems. But with the advent of MSI /LSI /VLSI chips and the demand for more

Manuscript received December 18, 1978; revised June 10, 1980. This work was supported by the National Science Foundation under Grant GJ-32758X.

The authors are with the Departments of Electrical Engineering and Computer Science, Carnegie-Mellon University, Pittsburgh, PA 15213.

complex systems, design automation began to move from the logic design level to the register transfer (RT) level [2] and higher.

The digital system design process is a long chain of decisions starting from an abstract systems level considering various alternative system organizations, down to specifying the fan-out capability of each transistor at the circuit level in an LSI design (Fig. 1). The higher levels of conceptual design (prob­lem specification, system level organization, and algorithm creation) have long been the role of the creative designer. Design aids such as the PMS representation [2], queueing level performance simulation [3], and reliability analysis [4] have been developed for these levels of design. The lower level of design (placement, routing, testing) have enjoyed a fair amount of success in automation [5], although optimality still remains elusive.

Recent research has been aimed at the generation of "near optimal" algorithmic and register transfer level designs [6], [7]. Design automation of these levels of design is still in its infancy and it is not yet known what the appropriate measures used in directing the automated design process should be. To establish these measures, results of these design automation systems must be compared with some "near optimal" designs. In some cases, analytic bounds of the optimal solution can be shown to exist. However, when the design task becomes too complex, there may be no other method to evaluate the auto­mated design algorithms than by statistical experimenta­tion.

A design system has been produced which will explore se­rial-parallel tradeoffs at the algorithmic and RT levels of de­sign [8]. The alternative implementations can be evaluated as per the designer's constraints. Using these evaluations as di-

0018-9340/81/0100-0048500.75 © 1981 IEEE