IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 25, NO. 1, JANUARY 1, 2013 67

10 Gb/s Error-Free Operation of All-SiliconIon-Implanted-Waveguide Photodiodes at 1.55 μm

Richard R. Grote, Kishore Padmaraju, Student Member, IEEE, Brian Souhan, Jeffrey B. Driscoll,Keren Bergman, Fellow, IEEE, and Richard M. Osgood, Jr., Fellow, IEEE

Abstract— The error-free operation of an all-Si ion-implantedCMOS-compatible waveguide p-i-n photodiode (PD) is exper-imentally demonstrated at 1.55 µm with 2.5 and 10 Gb/s datarates. Detector sensitivity as a function of bias voltage is measuredfor PDs of two different lengths, 250 µm and 3 mm. Thephotocurrent increase caused by bringing the PD into a highlyabsorbing state vi a forward biasing is also measured, and it isshown that a resulting 15 dB improvement in receiver sensitivitycan be expected. The limiting factors of the device frequencyresponse are analyzed, and the measured PDs are shown tohave comparable dark currents, responsivities, and sensitivitiesto reported Ge PDs.

Index Terms— Integrated optoelectronics, optical receivers,photodiodes, silicon.

I. INTRODUCTION

INTEGRATED photodiodes (PDs) operating in the C-bandare of paramount importance for the realization of on-

chip optical links as they enable the terminal optical-to-electronic (OE) data conversion required for Si photonics.These PDs, as realized on the silicon-on-insulator (SOI) plat-form, must be high-speed and CMOS-compatible to supportthe high-data-rate conversion of optical signals in highlyconfined single-mode Si-“wire” waveguides (SiWG) to theelectrical data signals that can be processed by monolithi-cally integrated electronics. However, there exists an inher-ent difficulty in integrating a material that absorbs in theC-band into a CMOS-compatible SOI-based process dueto material constraints. Recently, there has been significantprogress towards this goal with the hybrid integration ofIII-V materials [1], and with the integration of Ge [2]–[4].Although these solutions have produced high-performancedevices, Ge integration requires a large number of fabricationsteps, a high thermal budget, and the need for a Ge back-endprocess to produce low dislocation density devices [2], while

Manuscript received August 3, 2012; revised September 24, 2012; acceptedOctober 2, 2012. Date of publication October 10, 2012; date of current versionDecember 20, 2012. This work was supported in part by the InterconnectFocus Center, one of five research centers funded under the Focus CenterResearch Program, a Semiconductor Research Corporation (SRC) and DARPAprogram. The authors acknowledge support from the Columbia Optics andQuantum Electronics IGERT under NSF Grant DGE-1069420.

The authors are with the Department of Electrical and ComputerEngineering, Columbia University, New York, NY 10027 USA (e-mail:rrg2130@columbia.edu; kp2362@columbia.edu; brian.souhan@gmail.com;jbdrisco@gmail.com; bergman@ee.columbia.edu; osgood@columbia.edu).

Color versions of one or more of the figures in this letter are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LPT.2012.2223664

(a)

(b)

(c)

LFan-out taperSi+ implant

Doped “wings”

520 nm

220 nm

50 nm

1.5µm

520 nm

Contact Pad

Fig. 1. (a) Cross section of the SiWG PD. The channel waveguide sectionis Si+ ion implanted, while the wings are doped p and n to form a p-i-nphotodiode. The fundamental quasi-TE mode is overlaid. (b) Top view ofthe device (not drawn to scale), showing the PD region with L = 250 μmor 3 mm, and the cleaved faced fan-out tapers used for input coupling fromthe lensed tapered fiber (LTF). (c) Experimental setup for measuring detectorsensitivity.

hybrid III-V integration requires modifications to the standardCMOS process.

Devices that use methods other than intrinsic materialabsorption for photodetection, referred to as extrinsic PDs,have been demonstrated, including: internal photoemissionPDs utilizing a SiWG-Schottky contact [5], [6], surface-stateabsorption in both crystalline [7] and deposited poly-Si PDs[8], and PDs that utilize sub-bandgap-defect-state absorptionvia ion implantation of the SiWG [9]–[21]. Although theseextrinsic SiWG PDs are simpler to fabricate, they typicallyhave much lower responsivities (∼mA/W) as compared tointrinsic PDs (0.8 to 1 A/W for Ge [2]) as well as lowerabsorption coefficients which require a substantially longer

1041–1135/$31.00 © 2012 IEEE

68 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 25, NO. 1, JANUARY 1, 2013

device length. Ion-implanted PDs have shown the best overallperformance of these extrinsic SiWG PDs, while only requir-ing one additional implantation step and no high-temperatureprocessing. Various implantation species have been used toinduce absorption, including H+ [9], He+ [10], Ar+ [11],Se+ [12], and B+ [21]; however, Si+ implanted SiWG PDs[13]–[21] have the largest reported responsivities of theseion-implanted PDs. Recently, Si+ ion-implanted SiWG p-i -nPDs have been demonstrated with a bandwidth of > 35 GHzand responsivities of 0.5 to 10 A/W [16]. These devices arefully CMOS-compatible, and have responsivities which arecomparable to intrinsic PDs. Due to their weak absorptioncoefficient of 8–23 dB/cm, Si+ implanted SiWG PDs haverecently found use as in-line power monitors because of theirability to generate photocurrent without attenuating a largefraction of the optical power [19]; resonant cavity enhance-ment (RCE) has also been employed to decrease the devicefootprint while maintaining a large external quantum efficiency[17], [20]–[23].

In this letter, error-free operation [bit-error-rate (BER)≤ 10−12] is demonstrated for Si+ ion-implanted SiWG p-i -nPDs at 2.5 Gb/s for 250 μm and 3 mm device lengths Land at 10 Gb/s for the 250 μm device length [18]. Thesensitivity as a function of bias voltage is measured, andthe frequency response limitations of the device are investi-gated. It is shown that, by decreasing the device capacitance,40 Gb/s operation is achievable. Additionally, the photocur-rent increase caused by bringing the diode into a highlyabsorbing state via forward biasing, as reported in [15]–[17],is measured and it is shown that a 15 dB improvementin receiver sensitivity can be expected. To the best of ourknowledge, this is the first systems level exploration ofan extrinsic SiWG PD on the SOI platform, as well asthe first demonstration of error-free operation of such adevice.

II. MEASUREMENTS AND RESULTS

A. Experimental Setup

The measured Si+ ion-implanted SiWG p-i -n PDs werefabricated on the CMOS line at MIT Lincoln Laboratory,as described in [15], with dimensions given in Fig. 1. Theexperimental setup for measuring the sensitivity of thesePDs is shown in Fig. 1(c), with a 10 Gb/s or 2.5 Gb/s231−1 pseudorandom bit sequence (PRBS) of non-return-to-zero (NRZ) data being generated by a pulse-pattern generator(PPG). The PPG is then used to drive a LiNbO3 modulator(MOD), which imprints the electrical signal onto a 1.55 μmoptical carrier. The modulated light signal is sent to an erbium-doped fiber amplifier (EDFA) followed by a square passbandfilter, to reduce the amplified spontaneous emission noise. Theoptical eye is monitored through a 10/90 tap on a digital com-munications analyzer (DCA), and a variable optical attenuator(VOA) is used to attenuate the power being launched on-chipfor BER measurements. Another tap, with a 1/99 split, sendsthe signal to an optical power meter (PM) to accurately moni-tor the power being launched on chip from the lensed-taperedfiber (LTF). The PD is electrically contacted with 40-GHz

2.5 Gb/s

-12

-10

-8

-6

-4

-2

0

log(

BER

)

10 Gb/s

Off-Chip Power (dBm)

15V10V5V

Vbias

2.5 Gb/sL = 250 µm L = 3 mm

(a) (b) (c)

5 10 15 20 5 10 15 20 5 10 15 20

Fig. 2. Receiver sensitivity curves for (a) the L = 250 μm device at 2.5 Gb/s,(b) the L = 250 μm device at 10 Gb/s, and (c) the L = 3 mm device at2.5 Gb/s. The launch power shown in dBm is the power launched on-chipfrom the LTF, not including facet loss.

rated probes, and a bias tee is utilized to apply a DC bias. Thedemodulated electrical data signal is sent to a transimpedanceamplifier (TIA), followed by a limiting amplifier (LA), andthe signal from the LA is sent to either a bit-error-rate tester(BERT) (for BER measurements, shown in Fig. 2) or a DCA(for eye diagram measurements, shown in Fig. 3).

B. Detector Sensitivity

The receiver sensitivity curves for the L = 250 μm deviceat 5 V, 10 V, and 15 V biases are shown in Fig. 2(a)–(b)for 2.5 Gb/s and 10 Gb/s data reception, respectively. Receiversensitivity curves for the L = 3 mm device at 2.5 Gb/s areshown in Fig. 2(c). The power shown in Fig. 2 is the powerbeing launched on-chip from the LTF (measured on the1/99 tap), and does not take into account facet loss from thefan-out tapers [Fig. 1(b)]. The facet loss is estimated to be15 dB/facet for our devices based on measurements of thetotal fiber-to-fiber insertion loss. However, since the facet losshas previously been reported to be as low as 7 dB ± 2 dB/facet[14], the sensitivity of the device is conservatively estimatedto be decreased by 7 to 15 dB from the on-chip launch power.The discrepancy between our measured facet loss and thepreviously reported value is believed to be due to imperfectionsin the facet caused by polishing.

Error-free operation is demonstrated at 10 Gb/s for a 15 Vbias, and at 2.5 Gb/s at 15 V and 10 V biases. For theL = 250 μm device the sensitivity at 2.5 Gb/s is measuredto be 7.4 dBm and 12.3 dBm for the 15 V and 10 V biases,respectively. At 10 Gb/s, the sensitivity is 11.1 dBm whenbiased at 15 V. For the L = 3 mm device, the sensitivity at2.5 Gb/s is measured to be 11.7 dBm at 15 V bias. The datapoints in Fig. 2 have been fit with the complimentary errorfunction [24] using nonlinear least-squares curve fitting.

The eye diagrams for the detected signal after the TIA-LA are shown in Fig. 3, with the error-free cases shownin a red outline. Error-free operation is achievable at lowerbias voltages; however, a number of improvements in thedevice geometry are required, as discussed in the followingsections.

GROTE et al.: ERROR-FREE OPERATION OF ALL-SILICON ION-IMPLANTED-WAVEGUIDE PHOTODIODES 69

Fig. 3. Eye Diagrams for the L = 250 μm and L = 3 mm devices for 5 V,10 V, and 15 V reverse biases, taken after the TIA-LA. Red outlines signifyerror-free operation.

C. L1, L2, and Initial State Photocurrent

The photocurrent generated in the Si+ implanted PDs isbelieved to be due to interstitial clusters that form afterprocessing the devices at 475 °C [15], which allow for mid-bandgap transitions of photo-excited carriers. It has previouslybeen shown that these absorbing defects have two stable states,which are labeled L1 and L2 [15]. The PD can be broughtinto the L1 state, which has a weak absorption coefficient ofα = 8 dB/cm, by heating at 250 °C for 10 s. Subsequently,the PD can be brought into the L2 state, which has a largerabsorption coefficient of α = 18–23 dB/cm, by forward biasingthe device at 200 mA/cm of device length [16].

The receiver sensitivity measurements presented in theprevious section were performed without regard to the absorp-tion state of the PD. Subsequent to these measurements, thephotocurrent and dark current versus reverse bias voltage Vbiasare measured in this unknown “intial” state in Fig. 4(a) forthe L = 250 μm device. The DC photocurrent is found bylaunching a 17 dBm CW signal on-chip from a LTF andmeasuring the generated photocurrent on a picoammeter asa function of Vbias. These measurements are repeated forthe L1 and L2 state with the results shown in Fig. 4(a).It is noted that the photocurrent in the L1 state is ≈ 5 nA,which is smaller than the dark current for Vbias > 5 V, andthus the curve follows the dark current very closely. Thephotocurrent measurements show that a > 15 dB receiversensitivity improvement at all measured bias voltages can beexpected by operating the PDs in the L2 state as compared tothe initial state.

The dark current shown in Fig. 4(a) ranges from 6.7 nA at5 V reverse bias to 136.2 nA at 15 V reverse bias, which issubstantially less than the 10’s of μAs reported for typical GePDs [2], [3]. The dark current in Ge PDs results from dis-location defects in the Ge layer; however, CMOS-compatibleGe PDs fabricated by selective-area deposition have recentlybeen demonstrated with 3 nA of dark current at 1V bias [4].These devices require a large number of fabrication steps,

DarkInitialL1L2

0 5 10 1510-8

10-6

10-4

10-2

100

Vbias

I (m

A)

(a)(a)(b)

101 102 103

L (µm)

fRCftrfvgftotal

20

40

60

80

100

f 3dB (G

Hz)

Fig. 4. (a) Measured photocurrent for the L = 250 μm device in the initial,L1, and L2 states plotted on a log scale as a function of Vbias at λ = 1.55 μm.(b) Calculated 3-dB frequency of the PD as a function of device length L(on a log scale), decomposed into its constituent components. The two pointsindicate the time responses of the L = 250 μm and L = 3 mm devices. Inset:The eye diagram of the L = 3 mm device shows that the PD is RC-time-constant limited.

back-end Ge integration, and a thermal budget of 630 °C,while achieving comparable dark current and responsivity tothe simpler-to-fabricate Si+ ion implanted SiWG PDs.

III. DISCUSSION

Assuming that the PD is being operated in the L2 state,and taking into account the 7 to 15 dB facet loss, the on-chip sensitivity for the SiWG PD is predicted to be between−20 and −12 dBm for BER = 10−9 at 10 Gb/s with 15 Vbias. Thus, the Si+ implanted SiWG PD on-chip sensitivity iscomparable to the −14 dBm sensitivity of the Ge PD measuredin [3] for BER = 10−9 at 10 Gb/s with 3.2 V bias. Whilethe device footprint and bias voltage required for the Si+implanted SiWG PD are large compared to the Ge PD fora comparable sensitivity, the footprint can be decreased byutilizing RCE [17], [20]–[23] and the required bias voltagecan be lowered by redesigning p-n doped wings, or by usinga metal-semiconductor-metal (MSM) configuration to achievea larger internal field for the same applied bias.

The calculated 3 dB frequency of the diode as a function ofL is shown in Fig. 4(b), where the 3 dB frequency has beendecomposed into its constituent components: the transit-time-limited bandwidth ftr , the group-velocity-limited bandwidthfvg, and the RC-time-constant limited bandwidth fRC. The ftr

limit is calculated to be ≈ 97 GHz with an assumed carriersaturation velocity of intrinsic Si (vsat = 1 × 107 cm/s).This calculation is performed using the LaserMOD softwarepackage from RSoft Design Group, Inc. [25], which numeri-cally solves the Boltzmann transport and Poisson equationsfor a two-dimensional cross-section of the PD [Fig. 1(a)].The group velocity limited bandwidth is calculated usingvg = 7 × 109 cm/s and the method given in refs. [16], [24],while the RC-time-constant-limited bandwidth is found bylinearly fitting the measured device capacitance values forthe L = 250 μm and L = 3 mm devices [15] to find acapacitance per unit length of 0.53 fF/μm, and assuming

70 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 25, NO. 1, JANUARY 1, 2013

a 50 � load. The total frequency response is approximatedby ftotal ≈ (

f −2RC + f −2

vg + f −2tr

)−1/2.It can be seen from Fig. 4(b) that the total electrical band-

width of this device geometry follows the RC-time-constant-limit, deviating only at short devices lengths of L < 200 μm.The RC-time-constant limits the PD electrical response to≈ 21 GHz for the L = 250 μm device, and ≈ 2.1 GHz forthe L = 3 mm device. The eye diagram of the L = 3 mmdevice before the TIA-LA is shown in Fig. 4(inset), whereit can be seen that the decay time of the signal is longerthan the bit slot. For a 2.5 Gb/s signal, the bit slot is400 ps, while the decay time for a 2.1 GHz RC-limited devicecorresponds to ≈ 470 ps. Thus, the device-geometry testedis RC-time-constant-limited. At L = 3 mm the frequencyresponse limitation causes a sensitivity penalty as comparedto the L = 250 μm device which outweighs the increasein responsivity gained by increasing L. Device capacitancemust be minimized to overcome this sensitivity penalty forthe L = 3 mm device, and for the L = 250 μm device tooperate at higher data rates.

Towards this effort, the frequency response of these devicescan be increased by optimizing the device geometry todecrease the total device capacitance. If the capacitance of theL = 3 mm device is decreased to ≤ 0.362 pF, the frequencyresponse is limited to 8.8 GHz by vg, resulting in receiversensitivity improvement for 2.5 Gb/s operation. Similarly, theL = 250 μm capacitance must be decreased to 70.7 fF for a50 GHz frequency response, which is sufficient for 40 Gb/soperation. The absolute limit for the frequency response ofthe L = 250 μm device is the transit time limit, whichrequires C ≤ 35.4 fF. Devices capacitances of ∼1 fF havebeen reported for Ge PDs [4], while similar capacitances areachievable for Si+ implanted PDs.

IV. CONCLUSION

Error-free operation of an all-Si ion-implanted PD operatingat 1.55 μm has been demonstrated for 2.5 Gb/s and 10 Gb/sdata reception. For the L = 250 μm device error-free operationwas achieved with 15 V bias at 10 Gb/s and with 15 V and10 V biases at 2.5 Gb/s, while error-free operation for theL = 3 mm device was shown with 15 V bias at 2.5 Gb/s.

Present Ge PDs generally offer better performance; how-ever, they impose the significant burden of a challengingmaterials system. It has been shown that Si+ implanted PDshave dark currents, responsivities, and sensitivities comparableto those of reported Ge devices. A significant improvementin frequency response can be achieved by reducing devicecapacitance and a > 15 dB improvement in receiver sensitivitycan be expected by operating the PDs in the L2 state, whichwill make Si+ implanted PDs competitive with Ge PDs. Theperformance of Si+ implanted PDs, and the ease with whichthey can be integrated into a standard CMOS process flow,makes them an excellent candidate for usage as receivers andin-line power monitors in the Si photonics platform.

ACKNOWLEDGMENT

The authors would like to thank M. W. Geis andS. J. Spector for device fabrication and design.

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