:= Id + Ipk ∆

∑

= n 1

∞

2 Ipk ( )sin n π ∆ ( )cos n ω tn π

Influence of Skin Effect on MOSFET Losses

Alan Elbanhawy William Newberry Fairchild Semiconductor Fairchild Semiconductor 3001 Orchard parkway Running Hill Road

San Jose CA, 95134 South Portland ME, 04106 USA USA

aelbanhawy@fairchildsemi.com William.newberry@fairchildsemi.com

Abstract-As the Personal Computer makers push for DC-DC converters delivering 200 Amps at 1V within the next three years, the semiconductor manufacturers are pushing to optimize their MOSFET by improving both the silicon and the packages to provide switching devices suitable for these challenges. In this paper we will address the parasitic resistance attributed to the package alone and in isolation from the silicon on-resistance. We will show that in most of the traditional packages this resistance has a very strong frequency dependant component. This means that at a switching frequency of about a few Megahertz, this parasitic resistance will constitute a large percentage of the total device on-resistance. Based on this observation, we will concentrate on the synchronous buck converter and we will derive conduction loss equations that are frequency dependent and calculate actual losses and examine several effects that follow.

I. INTRODUCTION

This paper explores the influence of skin effect on power MOSFET parasitic resistance. Formulae will be derived to express the package parasitic resistance as a function of frequency and power loss will be calculated to demonstrate the percentage error that results if we do not take this effect into account

II. SYNCHRONOUS BUCK CONVERTER Fig. 1 depicts a simplified synchronous buck converter. This topology is the workhorse of the Personal Computer (PC) DC-DC converters, which offers an excellent combination of simplicity of operation, high efficiency and the all-important low cost. We will concentrate on the conduction losses in both the high side (HS) & low side (LS) MOSFETs. The frequency effects of the dynamic losses will not be addressed in this paper. The switching current in both of these devices are a rectangular wave that may be simplified to that in Fig. 2. The drain current waveform may be simplified as a simple rectangular waveform. The Fourier series of this waveform may be written as:

(1)

Where n is the harmonic number, ω is the frequency in radians, ∆ is the duty cycle and Ipk=Peak current.

HS MOSFET

LS MOSFET

Lf1 2

CfRload

0

Vcc

PWM Controllerand Driver

Vout

Fig. 1 Synchronous Buck Converter Switching Current:

∆Ts Ts t

Ipk i(t)

Fig. 2 Drain current waveform

III. PACKAGE PARASITIC RESISTANCE The parasitic resistance is usually between 60µΩ for the BGA 5.5x5 mm package to about 2.2mΩ for the SO8 package. This is a very small value that may be ignored in other small signal applications but in modern power circuits this represents an appreciable part of the total on-resistance of the switching device, which is the MOSFET for the purposes of this paper. To accurately determine the parasitic resistance it was important to isolate the package from the MOSFET. To

23131-4244-0136-4/06/$20.00 '2006 IEEE

measure the resistance over frequency we chose to employ finite element analysis (FEA). This has the advantage of allowing us to determine very small resistance values without the need for special test equipment and fixturing. It also eliminated any error which will be introduced by the test environment. A harmonic analysis was used to model the magnetic field surrounding the package. Resistance is then determined by extracting the real part of the characteristic impedance (Zo). Where:

(2) Therefore:

(3) Fig. 3 shows the D2PAK and all it's constituents that affect the simulation. As can clearly be seen this is a fairly complex structure, which cannot readily yield a closed form function describing the parasitics. The approach we have taken was to fit a curve to the results of the finite element analysis performed at various frequencies. This curve then describes the parasitic resistance as a function of frequency. This is done so we can introduce this function in the loss equations which ultimately allows us to study the effect of this phenomenon on the predicted losses using DC on-resistance as it is performed today.

Fig. 3 Finite Element Model for D2PAK

Fig. 4 shows two curves. The first in black is the calculated value of the parasitic resistance using finite element analysis and the red curve is the plot of the fit function. The

fit functions are available in Table 1. We have chosen to extend the simulation to 100MHz to account for close examination of the loss equations up to a very high harmonic number. Fig. 4 shows this effect clearly. The value of Rds goes up by a full order of magnitude by changing the switching frequency from 30KHz to a mere 10MHz. This effect is very significant in switching MOSFETs since the device's on-resistance Rdson is in the range of a few mΩ to start with.

Fig. 4 Package parasitic resistance as a function of the

switching frequency Fig. 5 depicts the Fourier series approximation of the drain current shown in equation (1) above with two different numbers of harmonics. The red curve was done using only 20 harmonics while the blue curve is done using 200 harmonics. We will use a number of harmonics >= 100 harmonics in this approach as it represents more faithfully the actual waveform.

Fig. 5 The square fourier series (1) fon n=20 and n=200

Using finite element simulation, we can calculate the parasitics at different frequencies up to 100MHz. Fig. 4 shows the result of such a simulations where the data points

22

**

imagreal

imagimagrealreal

IIIVIV

R++

=

imagreal

imagreal

jIIjVV

Z++

=0

−−

++

=imagreal

imagreal

imagreal

imagreal

jIIjII

jIIjVV

*

22

)**(**

imagreal

imagrealrealimagimagimagrealreal

IIIVIVjIVIV

+−++

=

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:= Pc Id2 Rdson ∆

:= Ptref Ipk2 ∆ ( )Rdson DC

:= PcDC Ipk2 ∆ ( )Rdson DC

:= ErrorPercent100 ( ) − Ipk2 ∆ ( )Rdson DC Pcf

Ipk2 ∆ ( )Rdson DC

are marked Rds. In order to interpolate the results at any frequency in between DC and 100MHz, we fitted these data points to the equations in Table 1. As you can see clearly in Table 1, the equations are in different format. This is due to the variation of cross-sectional geometry encountered by the current due to the different package styles. One further point, below the minimum skin frequency, approximately 30KHz for the packages used, the skin effect is zero. Therefore, these equations should be used to calculate the parasitic resistance for frequency f, where 30KHz ≤ f ≤100MHz. The DC value of the parasitic resistance is taken directly from the raw data.

Table 1 Package Parasitic Resistance Formula

SO8 09916.8085494.9275894.94F

DS eR−

−=

DPAK 32 0000024.0000486.003483.093761.14706.0 FFFFRDS +−++=

D2PAK

32 00005.001438.014452.490789.0 FFFRDS −++=

BGA 5x5.5 mm

49568.17374922.8 59179.030982.095504.0FF

DS eeR−−

−−=

IV. THE CONDUCTION LOSS EQUATIONS

The conduction losses, Pc, may be calculated as follows:

(4)

Where ∆ is the duty cycle, Id is the drain current and Rdson is the total on resistance of the MOSFET which comprises the package parasitic resistance and the silicon on-resistance. Now if we substitute Id from equation (1) above into (2) we get:

(5)

Where Pcf is the frequency dependant conduction loss. In synchronous buck converters, we have two switching MOSFETs, the high side MOSFET (HS) and the Low side MOSFET (LS). The HS MOSFET has a duty cycle of ∆ and the LS has a duty cycle of (1-∆). We will be calculating the conduction power dissipation in both cases using the Fourier series (5) and the classical (4) way and comparing the results. Using equation (5) above, one may calculate the conduction losses Pcf where:

Rdson(DC) = DC value of the combined silicon and package resistance Rdson(f) = The value of the combined silicon and package resistance at all other frequencies ∆ = Duty cycle n = Harmonic number A. High Side MOSFET The conduction losses may be written as follows:

(6)

Where: Ptref = DC conduction losses which we will use as the reference value and Ipk, ∆ and Rdson(DC) are as indicated above. Let us now write an equation for the percentage error between the DC calculations and the AC calculations using Fourier Series.

(7)

(8) Where Pcf can be calculated from equation (5) above.

Fig. 6 Conduction loss (z-axes) as a function of the fundamental switching frequency f and the silicon on-

resistance for an SO8 Package Fig. 6 shows clearly that the conduction losses for a device, in an SO8 package, are heavily dependant on the switching frequency and this effect must be taken into consideration when choosing a package for the HS MOSFET

∆+∆= ∑∞

=122

2222 )()sin(2)(:

n nfRdsonnIpkDCRdsonIpkPcf

ππ

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Fig. 7 The percentage error (z-axes) as a function of the

switching frequency f and the silicon on-resistance for an SO8 Package

B. Low Side MOSFET The conduction losses will still be calculated using equation (4) except for the fact that the duty cycle for the LS MOSFET is (1-∆). This means that the LS MOSFET is on for almost 87.5% of the total period making the harmonic content very small. As can be seen in Fig. 9 the percentage error is rather small (8%) compared to that of the HS MOSFET (65%).

Fig. 8 Conduction loss (z-axes) as a function of the

fundamental switching frequency f and the silicon on-resistance for an SO8 Package

Fig. 9 The percentage error (z-axes) as a function of the switching frequency f and the silicon on-resistance for an

SO8 Package Fig. 10 shows how the summation of all the harmonics ultimately results in the desired rectangular drain current waveform observed in the synchronous buck converter. We have chosen to ignore the effect of the ramp in current due to the output filter inductor to simplify the calculations and make them more manageable. The ramp current generally represents about 10%-20% of the full load current making this an acceptable approximation

Fig. 10 Synthesis of the square wave from the individual

sine waves

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V. CONCLUSION

• The Package parasitic resistance represent an appreciable part of the MOSFET on-resistance in power applications

• The package parasitic resistance possesses a very strong frequency dependence due to the skin effect phenomenon

• Higher fundamental switching frequency will result in higher parasitic resistance and hence higher conduction losses

• The DC conduction losses calculated using equation (4) above produces an error that can be as large as 100% depending on the package and the fundamental switching frequency

• When choosing the switching frequency for a given application, it is mandatory to examine this above mentioned effect to weigh the pros and cons of such a selection

• New packages have been developed by several manufacturers that address this problem with varying degrees of success. The BGA package from Fairchild has overall excellent parasitics and

as such is quite suitable for high frequency high power applications

• As the DC-DC converters are expected to perform at higher efficiencies, particularly in the notebook field, all loss mechanisms must be placed under the microscope in an attempt to minimize their effect and provide the overall solution that fully utilizes all the advantages made so far in MOSFET design

• Both with breakthroughs in silicon and in innovative packaging, these new switching devices continue to deliver improvement in performance at very reasonable prices.

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