1 .O-V and 1.5-V Operation of 4-GHz Tuned Amplifiers Implemented in a 0. l-pm CMOS Technology on Bulk and SO1 Substrates*

Yo-Chuol Ho, Clement Wannl , Yuan Taur’, Isaac Lagnado2, and Kenneth K. 0 Department of Electrical and Computer Engineering

539 Engineering Bldg., University of Florida, Gainesville, FL 3261 1

‘IBM T.J. Watson Research Center, Yorktown Heights, NY, 10598 2SPAWAR Systems Center, San Diego, D 805,53475 Strothe Rd. , San Diego, CA, 92152-6341

Absfract-4-GHz 1.5-V tuned amplifiers are implemented using a partially-scaled double-level-metal O . l - p n CMOS process on bulk and SO1 substrates. The bulk and SO1 amplifiers have for- ward transducer gains of 14 and 11 dB at vDD=1.5 v. The bulk amplifier has F,i,’s of 3.6 and 4.5 dB at 3 and 4 GHz, respectively, with a power consumption of about 28 mW. When the supply voltage is reduced to 1.0 V, Fmin i s increased to 4.4 and 5.0 dB at 3.0 and 4.0 GHz, while the peak gain and power con- sumption are lowered to 9 dB and 12.7 mW, respectively, which are not significantly worse than those of 5.8-GHz silicon bipolar LNA’s.

I. INTRODUCTION

Driven by needs for low-cost and low-power wireless com- munication devices, CMOS RF integrated circuits have drawn a great deal of attention. Several CMOS low noise amplifiers (LNA’s) have been reported for operation in the frequency range between 0.9 and 1.5 GHz [1],[2],[3],[4]. More recently, 13-GHz tuned amplifiers fabricated using CMOS transistors on SO1 and SOS substrates have also been demonstrated [5] . This paper examines possible uses of a 0.1 -pm bulk CMOS technology for 1 .O-V and 1.5-V operations at frequencies higher than 2.4 GHz.

Tuned Amplifiers with a tuned frequency of 4 GHz are implemented using a partially-scaled double-level-metal 0.1- pm CMOS process on bulk and SO1 substrates. The process utilizes a 0.35-pm design rule set for all the dimensions except for the 0. l-pm gate length and has a 2.9-nm thick gate oxide layer. Measured threshold voltages for bulk and par- tially-depleted SO1 NMOS transistors are 0.4 V. These tran- sistors have a measured peak fT’s of approximately 100 GHz. The tuned amplifiers are simulated using SOISPICE [6]. The bulk amplifier has the highest resonant frequency among bulk CMOS amplifiers reported to date. The bulk and SO1 amplifi- ers have forward transducer gains (SZ1) of 14 and 11 dB. At a VDD of 1.5 V, the bulk amplifier has Fmin’s of 3.6 and 4.5 dB at 3 and 4 GHz, respectively, which are promising. In order to

* This work is supported by IBM Cont. 53290093, and SPAWARSYSCEN, San Diego, Cont. N66001-93-C-6005.

evaluate the low-supply and low-power capabilities, the cir- cuits are also characterized for 1 .O-V operation.

11. Tuned Amplifier DESIGN

A schematic of the amplifier is shown in Fig. 1. The circuit is similar to that of a previously reported 900-MHz low noise amplifier implemented in a 0.8-pm CMOS process [2]. A photo-micrograph of the circuit is shown in Fig. 2. Transistors MI and M2 form a cascode amplifier which provides all of the power gain. MI is biased using an off-chip bias tee. For sim- plicity, gate of M2 is tied to VDD, which decreased the l-dB compression point (PldB). A current mirror formed by Mbl and Mb2 biases the second stage common-source amplifier formed by M3. C1 is a 10-pF bypass capacitor for grounding the source of M3 to improve the stability of the second stage. C2 is a de-coupling capacitor for dc isolation at the output. The supply node is bypassed to the on-chip ground with an on-chip 10-pF capacitor (C3).

An input matching network is not integrated. In particular, on-chip inductive degeneration for input matching is not used

vDDg g v b 2

f - -

Fig. 1. Amplifier schematic

0-7803-5288-2/98/$10.00 0 1998 IEEE 85

Fig. 2. Amplifier microphotograph

due to detrimental effects of the series resistance of the inte- grated spiral inductor to the gain and noise figure in the dou- ble level metal CMOS process. To obtain G,, and Fmin, an external matching network is needed. A partial output match- ing is provided by 20042 resistor (RL). Resonant frequencies of the amplifiers are determined by a 2-nH on-chip inductor, L1, and parasitic capacitances seen by the inductor at the drain node of M,. The spiral inductor has 4.5 turns with a metal width of 5 pm and a metal pitch of 6.5 pm. Measured induc- tance on the bulk and SO1 substrates is -2.2 nH. Quality-fac- tors of the inductor are 3 and 4 near 4 GHz for the bulk and SO1 inductors, respectively. The capacitors are implemented using a high-capacitance-density MOS structure with the gate oxide layer as the dielectric [7].

UI. RESULTS AND DISCUSSION

Figs. 3 and 4 show the transducer gain and noise figure data 12

3 2 3 4 5 6 7

Frequency (GHz)

15

l2 z

5

2. 6

, v 9 &'

h a W

6'

3 2 3 4 5 6 7

Frequency (GHz) Fig. 4. Transducer Gain and Noise Figure at VDD=~ .O V

obtained using on-chip measurements for the amplifiers at VDD'S of 1.5 V and 1.0 V. Peak power gains of 14 dB at 4.1 GHz, and 11 dB at 4.3 GHz are measured at a VD, of 1.5 V for the bulk and SO1 amplifiers, respectively. At a VDD of 1 .O V, peak power gains are 9 and 8 dB, respectively. The best bulk amplifier exhibits a peak gain about 3 dB greater than that of the best SO1 amplifier, which is a pleasant surprise and needs a further investigation. Because the drain-to-substrate (CDSUB2) capacitance of M2 is larger in the bulk amplifier, the resonant frequency of the bulk amplifier is about 200-MHz lower.

Measured 50-R noise figures (without any input matching) are -5.5 dB for the bulk and SO1 amplifiers at 4 GHz and VDD =1.5 V. By using an external input matching network, mini- mum noise figure at a given frequency, F,n, and power gain associated with the F,, or at GO^, GAsso of the bulk ampli- fiers are measured at varying frequencies and plotted in Fig. 5. When VDD is 1.5 V, the minimum Ffin of 3.6 dB is measured at 3 GHz. The Ffi,, at the resonant frequency is 4.5 dB. At a VDD of 1.0-V, the minimum Ffi,, of 4.4 dB is observed once again at 3 GHz, while that at the resonant frequency is 5.0 dB.

Figs. 6 and 7 show that the reverse isolations of the amplifi- ers are --45 dB at 4 GHz for the amplifiers. Isolation charac- teristics are reasonable due to the use of a two stage design, although at high frequencies, they are limited by the substrate effects. For frequencies below 3.5 GHz, isolation of the SO1 amplifier is - 10-dB better than that of the bulk amplifier. For frequencies higher than 5 GHz, isolation characteristics for the both amplifiers are approximately the same. A way to explain this is that the capacitance associated with the buried

Fig. 3. Transducer Gain and Noise Figure at VDD=1.5 V

86

oxide is shorted and differences between the bulk and SO1 D-E]vnn=1.5v H V , , = I .OV

1 1 20 I I I

-

n E9 a, l Y

E. h

e W v

2 2 3 4 5 6 7

Frequency (GHz) Fig. 5. Fmin for the bulk amplifier with VDD=I .5 V & 1 .O V

-30 L,

Y

-60 1 i L,+&SOl

1 -701 ’ I ’ I I I I I

2 3 4 5 6 7 Frequency (GHz)

Fig. 6. Reverse Isolation at VDD=l.5 V

-30 F -40

n

8 -50 2

m

-60 U t

2 3 4 5 6 7 Frequency (GHz)

Fig. 7. Reverse Isolation at V D D = ~ .O V

substrates diminish at these frequencies. To understand the low frequency behaviors of the SO1 amplifier, S12 of the amplifier is simulated using SOISPICE. If the substrate effects are not included, the simulations show valleys around 4 GHz in SI, plots. The substrate effects are also simulated using a substrate model from [8]. A combination of these effects can qualitatively explain the results.

Fig. 8 shows plots of output power versus input power. The 1-dB compression points (PldB) are -16 and -19.6 dBm for the bulk and SO1 amplifiers, respectively at a VDD of 1.5 V. When the VDD is lowered to 1 .O V, the 1-dB compression points are decreased to - 18 and -2 1.4 dBm, respectively. The relatively low PldB points are due to sub-optimal design for the second stage. This problem can be readily corrected by using an inductive load with a capacitive transformer in the second stage and by re-optimizing biasing of the 2-nd stage. The IP3’s are expected to be -IO dB higher than PldB points [9]. Power consumption level for the bulk and SO1 amplifiers at a VDD of 1.5 V is 28 mW, while at a VDD of 1.0 V, they are 12.7 and 10.9 mW, respectively. Power consumption levels of -12 mW is the lowest for bulk CMOS amplifiers reported to date. The power gain, noise figure, and power consumption, on the other hand, are not significantly worse than those of 5.8-GHz sili- con bipolar LNA’s [lo].

Input reflection coefficients (SI 1) are measured to investi- gate the amplifier’s input matching. Because of the capacitive input impedance; S1 1’s are around -2.6 in bulk amplifier and - 2.2 dB in SO1 amplifier at 4 GHz, which are poor. However, the output reflection coefficients (S22) of about -7.2 dB in bulk amplifier and -9.0 dB in SO1 amplifier at 4 GHz (Fig. 9) are starting to be acceptable. Figs. 10 and 11 show A and K for the amplifiers at a VDD of 1.5-V. The stability characteristics of the bulk and SO1 amplifiers are comparable. For frequen- cies between 2 and 7 GHz, A’s are less than one while in the worst case, K’s are slightly less than one, demonstrating rea- sonable stability characteristics. At low frequencies, K’s are greater than one but erratic due to noise in the S12 data near the noise floor of the measurement set-up.

As stated, the amplifiers are implemented using a partially scaled process. However, these results provide data points for extrapolating potential of fully scaled 0.1-pm bulk CMOS technologies for 5.8-GHz ISM band applications. Surpris- ingly, using an SO1 substrate does not seem to provide signifi- cant performance advantages for the LNA. Lastly, 1.0-V operation of the amplifiers seems feasible, but more work is needed.

87

J -50 -45 -40 -35 -30 -25

PIN (dBm) Fig. 8. P1dB measurements for VDDzl.5 V & 1 .O V

A

!3 N N

VI

-3

-6

-9

.12

2 3 4 5 6 7 .15

-6

-9

.12

.I c 2 3 4 5 6 7

- I "

0.4

0.3 a

0.2

O * l t 1

4

M

2

I I O L ' I ' I ' I ' I ' ' 2 3 4 5 6 7

Frequency (GHz)

Fig. 1 1 . Stability K for Bulk and SO1 amplifiers at VDD=1.5 V

Table I: Summary of Measurement Results

Substrate 1 Bulk 1 Bulk 1 SO1 1 SO1

Resonant 4.1 GHz 4.1 GHz 4.3 GHz 4.3 GHz frequency

Power Supply 1.5 v 1.ov 1.5 V 1.0 v

I TransducerGain I 14dB I 9 d B I 1 1 dB I 8 d B

(@ resonant freq.)

frequency)

I PowerConsumpt. I 28mW I 12.7mW I 28mW I 10.9mW r - 1 -2.6dB I - I - 2 . 2 d B I -

ACKNOWLEDGEMENT

The authors would like to thank Kihong k m and Chi-Ming Hung at University of Florida for their help in design and characterization.

1 2 3 4 5 6 7

Frequency (GHz)

0.0 REFERENCES

[ l ] Karanicolas, A . , "A 2.7-V 900-MHz CMOS LNA and Mixer," ISSCC Digest of Technical Papers, pp. 50-51, ..

Fig. 10. Stability A for Bulk and SO1 amplifiers at V D p 1 . 5 V Feb., 1996. [2] Y.-C. Ho, M. Biyani, J. Colvin, C. Smithhisler, and K. K.

0, "3-V LNA Implemented Using a 0.8-pm CMOS Pro-

88

cess with Three Metal Layers for 900-MHz Operation,” IEE Elec. Letts., v 32, n 13, pp. 1191-1193, June, 1996.

[3] Shaeffer, D.K., and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE J. Solid-state Circuits, vol. 32, pp. 745-759, May, 1997.

[4] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1 GHz CMOS RF Front-End IC for a Direct- Conversion Wireless Receiver,” IEEE J. Solid-state Cir- cuits, vol. 31, n 7, pp. 880-889, Jul., 1996.

[5] K. Kim, Y.-C. Ho, B. Floyd, C. Wann, Y. Taur, I. Lagnado, and K. K. 0, “4 GHz and 13 GHz Tuned Amplifiers Implemented in a 0.1 pm CMOS Technology on SO1 and SOS Substrates”, ISSCC Digest of Technical papers, pp 134-139, Feb., 1998.

[6] Fossum, J.G., “SOISPICE-4 (Ver. 4.4) (FD/SOI and NFD/ SO1 MOSFET Models),” University of Florida, Gaines- ville, Jan., 1997.

[7] C-M. Hung, Y.-C. Ho, I.-C. Wu, and K. K. 0, “High-Q Capacitors Implemented in a CMOS Process for Low- Power Wireless Applications”, IEEE Trans. Microwave Theory and Techniques, Vol. 46, No. 5, May 1998.

[8] A. Viviani, J. P. Raskin, D. Flandre, J. P. Colinge, and D. Vanhoenacker, “Extended study of crosstalk in SOI- SIMOX substrates,” IEDM Tech. Dig., pp. 713-716, 1995

[9] Gonzalez, G., Microwave Transistor Amplifiers, Prentice- Hall, 1984, p. 179.

[lo] S. Voinigescu, and M. Maliepaard, “5.8 GHz and 12.6 GHz Si Bipolar MMIC’s,” ISSCC Digest of Technical Papers, pp. 372-373, Feb., 1997.

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