Fig. 2. Measured [2] and (2D) simulated ID-VGS characteristics of the same device biased as (a) p- and (b) n-mode TFET for VDS = ±0.1 V and ±0.5 V. Measured ID is normalized to the length of the curved perimeter of the real device cross section.

−1.5 −1 −0.5 0

10−7

10−5

10−3

10−1

101 V

DS =–0.5VVDS =–0.1V

VGS

[V]

I D [μ

A/μ

m]

(a) p−mode

simmeas

0 0.5 1 1.5

10−7

10−5

10−3

10−1

101

V DS=0.5V

V DS=0.1V

VGS

[V]

(b) n−mode

simmeas

Fig. 1. (a) Simulated structure of a 3D-TFET that reproduces the sSi NW reported in [2] and its (b) 2D approximation (figures not in scale). The region names (Drain and Source) are related to n-operation mode.

(a)

(b)

Gate

Channel regionDrain Source

Gate oxide

Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires

Sebastiano Strangio1,2, Pierpaolo Palestri1,*, David Esseni1, Luca Selmi1, Felice Crupi2 *Email: palestri@uniud.it , phone: +39 0432 558249

1DIEGM, University of Udine, Via delle Scienze 206, I–33100, Udine (UD), Italy 2DIMES, University of Calabria, Via P. Bucci, 41C, I–87036 Arcavacata di Rende (CS), Italy

Abstract—Tunnel-FETs are studied in a mixed device/circuit simulation environment. Model parameters calibrated on experimental DC as well as pulsed characterizations are then used for 6T SRAM cells investigation. Issues concerning fabricated devices, as the ambipolarity and the uni-directionality, are addressed at both device and circuit levels. Our results suggest that ambipolarity needs to be solved through device engineering and/or fabrication process improvements, while issues related to uni-directionality may be mitigated with a proper circuit design.

Keywords—TCAD; Tunnel-FET; Ambipolarity; SRAM.

I. INTRODUCTION Tunnel-FET (TFET) is one of the most promising

candidates to replace CMOS in ultra-low-power (ULP) applications [1-3], thanks to sub-threshold swing (SS) below the 60mV/dec limit of MOSFET. Several papers investigated the performance of simple TFET-based circuit topologies, such as SRAM cells [4-8], by means of TCAD-based mixed-mode device/circuit simulations and/or look-up-table models in the Verilog-A environment [4-10]. However, the simulated device templates are often oversimplified and neglect parasitic effects and material defects arising from immature fabrication processes.

In this paper, first we accurately calibrate the structure and the physical model parameters to reproduce one of the best strained Si (sSi) nanowire (NW) TFET reported to date [2,3]. Then, a mixed device/circuit study of 6T SRAM cells is performed. Our purpose is to investigate the feasibility of TFET circuits beyond the complexity level of the simple inverters fabricated so far [2].

II. CALIBRATION ON DC MEASUREMENTS The transistor considered for model calibration is the

TFET reported in [2]. The materials are: strained Si for the channel region, NiSi2 for the self aligned source(S)/drain(D) contacts, HfO2 for the gate oxide (tox = 3 nm), TiN for the metal gate. Despite the use of HfO2, the equivalent oxide thickness (EOT = 2.2 nm) is somewhat degraded by the thin interlayer of SiO2 between the channel and the HfO2. The channel length is 200 nm, the width is 45 nm, and the height is 7 nm. Other details of the fabrication process are reported in [2]. A 3D template (Fig. 1a), as close as possible to the experimental device, was used only for few single-device simulations, since performing mixed device-circuit simulations with 3D structures would be computationally prohibitive. For the device/circuit analysis, instead, we resorted to an equivalent 2D structure (Fig. 1b), by tuning the

EOT2D (1.5 nm) to match the electrostatics of the 3D structure. The N/PTFETs of the inverter in [2] were physically identical, thus the n- or p-operation mode was exclusively determined by the biasing. It is worth noting that the S region in the n-mode (i.e. the p+ doped pocket) becomes the D region in the p-mode convention. At the same time, the n+ pocket is the D/S for the N/PTFET, respectively. The direction of the channel current is the same in both operation modes (i.e. from n+ to p+ pockets), but the tunneling junction should be only the p+/channel one when biased as n-type, and only the channel/n+ one when biased as p-type transistor. Unfortunately, since both junctions are designed to be used as tunneling junction (but in different operation modes), when the gate voltage is near to 0 V, the band diagram is sufficiently steep at both interfaces, leading to ambipolar effects. Furthermore, trap-assisted-tunneling (TAT) due to defects represents a parasitic conduction mechanism that deteriorates

978-1-4799-4376-0/14/$31.00 ©2014 IEEE 282

Fig. 4. Sketch of 6T TFET SRAM cells with either (a) inward facing access transistors (I-AT) or (b) outward facing AT (O-AT). The marker indicates the source/channel tunneling junction of the related operating mode.

QBL

WL

BLBQB

M1

M2

M3

M4M6M5

QBL

WL

BLBQB

M1

M2

M3

M4M6M5

(a) (b)

Fig. 3. Mixed mode simulations of the inverter implemented with the devices whose curves are reported in Fig.2. Each TFET of the inverter in [2] was implemented with 100 parallel NWs (WNW = 50 nm): WPTFET/WNTFET = 1. (a) Comparison with measured [2] VOUT-VIN voltage transfer characteristics (VTC). (b) ID-VIN curves, simulated for various VDDs.

0 0.2 0.4 0.6 0.8 1 1.20

0.20.40.60.8

11.2 V

DD=1.2V

VDD

=1.0VV

DD=0.8V

VDD

=0.6V

(a)

VO

UT [V

]

simmeas

0 0.2 0.4 0.6 0.8 1 1.2

10−5

10−4

10−3

10−2

10−1

100 V

DD :

(b)

Only simulations

VIN

[V]

I D [μ

A/μ

m]

1.2 V1.0 V0.8 V0.6 V

TABLE I. SRAM SIGNAL VOLTAGE LEVELS FOR VARIOUS TEST CONDITIONS.

Condition \ Signal WL BL BLBHold (Write '1') 0 VDD 0

Hold (Read) 0 VDD VDDWrite '1' VDD VDD 0

Read [BLs pre-charge (ФBLs) at VDD] VDD VDD VDDRead [ ФBLs = VDD / 2] VDD VDD/2 VDD/2

the SS and, consequently, leads to an increase of the ambipolarity [11]. Even the injection at the schottky barriers between the metal contacts and the p+/n+ pockets may be significant, since the doped pockets sandwiched between the NiSi2 and the intrinsic sSi channel region are only few nm deep according to SIMS measurements in [3]. However, our preliminary simulations including both injection at the schottky barrier and band to band tunneling (BTBT) proved that the latter contribution is predominant, thus the calibration was carried out considering only the BTBT conduction mechanism.

The (static) non-local tunneling model was employed activating the BTBT option [12]. The adjustable calibration parameters are the tunneling masses mc and mv with respect to the electron mass m0 and the scaling factors gc and gv for the generation/recombination terms that are added to the carrier continuity equations to account for tunneling [12]. Even if a more physically accurate dynamic non-local band to band tunneling model is available, we chose the static one since it is computationally more robust in the mixed device/circuit scheme. The calibration procedure was carried out by fitting the model parameters and other variables, such as the S/D doping levels and their decay lengths. A good match between simulations and DC experiments was obtained only with non-realistic parameters. Heavy and constant doping (NA,D > 1021 cm–3) is assumed for the S/D pockets, resulting in a staggered band diagram at the tunnel junctions because of the large band-gap-narrowing caused by the extremely NA,D. In the experiments, this reduction of the band gap is most likely due to strain (see fig.16 in [3]) but the simple BTBT model employed here forced us to use the high (non-realistic) doping as the only possible work-around to reproduce the I-V. Regarding the tunneling model, the effective masses were set to 0.2m0 for both electrons and holes, while the pre-factors were kept to their default values. The use of these effective calibration parameters allows us to fit the experiments by including the results of different conduction mechanisms into one model. Of course, this prevents any use of this TCAD template to derive insights of the device physics and its engineering. However, despite not having a physical substantiation, the tuned framework accurately captures the I–V characteristics, including the ambipolarity effect (Fig. 2), and it is therefore useful in order to investigate basic circuits as inverters and SRAM cells by means of mixed device-circuit simulations. The agreement between the Voltage Transfer Characteristics (VTC) of the inverter, measured for different supply voltages VDD, and the mixed device-circuit simulations is more than satisfactory (Fig. 3a). The main effects of device ambipolarity on the inverter operation are: 1) the nominal output high/low value is significantly lower/higher than VDD/0 V; 2) the ID at VIN = 0 V and at VIN = VDD (fig.3b) is more than two orders of magnitude larger than the ID at the logic threshold (for any VDD), as opposite of the ID-VIN of a typical CMOS inverter.

III. SRAM SIMULATIONS WITH THE CALIBRATED MODEL Fig. 3a demonstrates a reasonable degree of predictive

ability of the template calibrated on DC measurements in mixed device-circuit simulation. As next step we investigated the feasibility of symmetric TFET-based 6T SRAM cells using the devices discussed so far. Being the device asymmetric (i.e. S and D have opposite doping), there are two

ways to implement a symmetric TFET 6T SRAM cell depending on the position of the tunneling junction of the access-transistors (AT): inward-facing (I-AT, Fig. 4a) or outward-facing (O-AT, Fig. 4b). The test conditions reported in Table I were simulated for different cell sizing; in particular we tuned the drivability of the ATs w.r.t. the pull-up (PU) and the pull-down (PD) TFETs of the inverter, by modifying both the shape factor ratio and their gate work-functions [9].

Since the TFET can operate both as n- and p-type (according to biasing), the off-state is not strictly controlled by the gate to source voltage when it is employed as AT. In fact for a positive VDS (terminal names related to n-mode convention) it can switch to the on-state both if VGS increases (for VGS > 0) and if VGD decreases (for VGD < 0)1. In Fig. 5 the data retention of a minimum-sized (WAT = WPD = WPU) SRAM cell implemented with the devices of Fig. 2 is evaluated through the butterfly curves of the I-ATs configuration. The BL and BLB were either set to logic '1' and '0' (a) or both to logic '1' (b), to measure the hold ability (WL = '0') of the cell under test during read and write operations of a cell in the same column. The figure reports also the butterfly

1 The VGD of the device biased in the n-mode corresponds to the VGS of the p-

mode operation

283

Fig. 7. Simulated ID-VGS characteristics of the (a) P- and (b) N-TFET devices implemented with the same parameters of the device calibrated in Fig. 6. The WF is 3.94 eV and 4.97 eV for N- and P-TFET, respectively.

−1 −0.5 0

10−11

10−9

10−7

10−5

10−3

10−1

101

– 60 mV

/dec

VGS

[V]

I D [μ

A/μ

m]

(a) p−TFET

VDS

= –0.5 V

VDS

= –0.1 V

0 0.5 1

10−11

10−9

10−7

10−5

10−3

10−1

101

60 m

V/d

ec

VGS

[V]

(b) n−TFET

VDS

= 0.5 V

VDS

= 0.1 V

Fig. 6. Measured [3] and simulated pulsed ID-VGS (a) and ID-VDS (b).

−2 −1 0 1 210

−3

10−2

10−1

100

101

102

(a)

VDS

=–0.6V

VGS

[V]

I D [μ

A/μ

m]

simmeas

−2 −1.5 −1 −0.5 00

10

20

30V

GS = –1.5 V

–1.0 V–0.5 V

(b)

VDS

[V]

I D [μ

A/μ

m]

simmeas

Fig. 5. DC calibration: butterfly curves in hold condition (WL = '0') for the I-AT configuration at various BL(B) voltage levels, compared with the pure inverter VTCs (VDD = 0.5 V).

0 0.25 0.50

0.25

0.5BL=1

BLB=0

(a) I−AT: Hold (Write)

VQB

[V]

VQ

[V]

INV.SRAM

0 0.25 0.50

0.25

0.5 BL=1 BLB

=1

(b) I−AT: Hold (Read)

VQB

[V]

INV.SRAM

Fig. 8. Simulated butterfly curves in hold condition after calibration on pulsed measurements (WL = '0') for the I-AT configuration at various BL(B) voltage levels, compared with the inverter VTCs (VDD = 0.5 V).

0 0.25 0.50

0.25

0.5 BL=1

BLB=0

(a) I−AT: Hold (Write)

VQB

[V]

VQ

[V]

INV.SRAM

0 0.25 0.50

0.25

0.5 BL=1

BLB=1

(b) I−AT: Hold (Read)

VQB

[V]

INV.SRAM

curves obtained from the pure inverter VTCs without considering the ATs (dotted grey lines). When the I-AT is added, even if it is biased with VG

AT = VWL = 0 V, the VTC is considerably deformed, so that the cell is no more bi-stable. This is due to the fact that, when the WL is at the low level and the BL(B) is at VDD, the I-AT turns on as a PTFET since the VGD (i.e. VGS if the name of terminals refer to the p-type convention) is –VDD. A similar situation occurs for the O-AT configuration when the BL(B) is set to logic '0' and for different VDD values. Changing the work-function of the metal gate (as suggested in [9] to reduce the N/P imbalance) does not improve the situation.

We can conclude that the ambipolarity of such TFETs affects the operation of the SRAM cells so severely that it prevents the storage operation. Although we have simulated 6T cells, the same results apply to other proposed SRAM topologies [4-8] that employ TFETs as ATs.

IV. CALIBRATION ON PULSED MEASUREMENTS The ambipolarity may be mitigated by device engineering,

e.g. fabricating a steep tunneling junction at S side and a softer and less doped junction at the D side. Furthermore, pulsed measurements reported in [3] show that the ambipolar behavior can be limited by suppressing TAT. Thus, since transient measurements show lower SS because of the negligible TAT contribution to the current, we performed a new calibration taking as reference the pulsed I-V characteristics (Fig. 6) [3]. In this case, the calibrated parameters are more realistic. The doping levels were ND,A = 4⋅1020 cm-3, the decay lengths were 0.8 nm and 1.8 nm for the n+ pocket and for the p+ pocket, respectively. Regarding the adjustable model parameters, the effective masses mc and mv were set to 0.42m0. The pre-factors gc and gv were still kept to their default values. In addition, the EG0 (i.e. energy gap at 0 K) of sSi was modified to 0.92 eV. These more physically meaningful parameters suggest that the non-local tunneling model can adequately predict the pure BTBT current, and the agreement between simulations and DC measurements fails (if realistic parameters are used) because TAT cannot be neglected. The calibration on pulsed I-V curves can be used to project the performance that may be achieved with today devices, assuming one could eliminate the trap states responsible for TAT. Note that in Fig. 7 the gate metal work-functions (WF) of NTFET and PTFET were individually set to obtain complementary devices optimized for either n- or p-mode operation. Since such devices suffer from asymmetric current flow [1], a further analysis is necessary to investigate their limitations when employed as AT in a SRAM cell.

V. SRAM SIMULATIONS AFTER CALIBRATION ON PULSED EXPERIMENTS

The simulated I-AT and O-AT SRAM configurations, implemented with the complementary devices calibrated on pulsed experiments, are discussed in this section. The storage operation is ensured by the good VG control of the AT off-state, as demonstrated by the overlap between the SRAM butterfly curves simulated in hold operation (WL='0', Fig. 8) and the inverter VTCs, (as opposed to the results in Fig. 5). Fig. 8 refers to the I-AT configuration, but similar results have been obtained for the O-AT configuration.

Using the nominal devices/cells (i.e. without including variability), we then computed the static noise margins in Hold (HSNM), Write (WSNM) and Read (RSNM) operations as well as the write and read delays (VDD ranging from 0.5 V to 0.2 V), as defined in Fig. 10. Since the write is performed by forcing the BL pair to differential levels of '1' and '0', only one of the two ATs can propagate the data, that is only the logic '1' with I-AT and only the logic '0' with O-AT. Being an n-type transistor better in propagating logic '0' than '1', the cell with the O-AT has a better write-ability. In the case of the I-AT, the write is successful only by sizing the AT more than 5

284

Fig. 10: Dynamic performances of the O-AT configuration for VDD = 0.5 V. The capacitance of the bit-lines has been set to 20 fF.

0 200 400 600

0

0.2

0.4

0.6

QBQ

WL0.9xVDD

write delay

(a)

time [ns]

Nod

e V

olta

ges

[V]

0 20 40 60

0

0.2

0.4

0.6 BLB

BL

WL

0.1xVDD

read delay

(b)

time [μs]

Fig. 9. Hold, Write and Read Static Noise Margins, for (a) I-AT configuration and for (b) O-AT configuration versus the ratio between AT and PD sizes for minimum size PU and PD, respectively (the WMIN is equal to 50 nm, that is the effective width of the NW in [3]). VDD = 0.5V.

0 5 10

0

0.05

0.1

0.15

0.2

(a)

Hold

Read(φ=VDD ) Write

WI−AT

/ WPD

H−

, R−

, W−

SN

Ms

[V]

0 5 10

0

0.05

0.1

0.15

0.2

(b)

Read (φ=VDD

)Read (φ=V

DD /2)

Write

Hold

WO−AT

/ WPU

Fig. 11: Dynamic performances of minimum sized (WPU = WPD = WAT = 50nm) O-AT configuration for various VDD.

200 300 400 500

10−6

10−4

10−2

100

VDD

[mV]

Writ

e &

Rea

d D

elay

s [s

]

6T SRAM CELL( Outward−AT )

Read (φ=VDD

)

Read (φ=VDD

/2)

Write

times larger than the PD transistor (Fig. 9a), but for the same condition the read operation fails. In contrast, with the O-AT the read operation cannot be performed correctly if the BL pair is precharged at VDD, because the O-ATs are biased with a negative VDS. Consequently, even if the RSNM is essentially equal to the HSNM (Fig. 9b), the read delay is about two orders of magnitude larger than write delay at VDD = 0.5 V and this gap becomes unacceptable with the VDD scaling (Fig. 11). However, the O-AT configuration with a BL pre-charge to half VDD for the read can be functional. As shown in Fig. 9b, for 1 < WO-AT/WPU < 2 both read and write operations have acceptable SNMs and the same is valid for the read delay (stars in Fig. 11). In fact, the O-AT connected to the storage node at '0' has VDS < 0 and the CBL remains stuck at VDD/2 after the rise of WL voltage. However, the opposite O-AT can conduct current, allowing the corresponding CBL to be pulled-up from VDD/2 toward VDD, thus enabling the differential sense amplifier to detect the data within a reasonable delay. The pre-charge at VDD/2 appears as an effective way to mitigate the effects of TFET uni-directionality in 6T cells and a viable alternative to more complex topologies [4-8].

VI. CONCLUSIONS This paper presented a simulation study on symmetric 6T

SRAM cells featuring TFETs with models calibrated on realistic devices [2,3]. Even if a good match between simulation and DC experiments was obtained with non-realistic parameters, this calibration set reproduced the ambipolarity and allowed us to investigate the effects of such behavior on 6T SRAM cells. Our results show that ambipolarity affects the gate control of TFET in off-state, thus preventing the SRAM cell data retention. On the contrary, devices calibrated on pulsed measurements featured much less ambipolarity and the calibration parameters were more physically sound, possibly due to suppression of TAT using pulse widths shorter than the trap time constants. Two complementary n- and p-type TFETs, obtained by metal gate work-functions engineering, were used to address the unidirectional current limit of TFETs when employed in 6T SRAM cells. Only the configuration with outward ATs could achieve both acceptable read and write SNMs (> 20% of VDD), but the read delay was unacceptably larger than the write delay. However, a BL pre-charge to VDD/2 allowed a reasonable time-to-read and limited degradation at scaled supply voltage. In this study we have not included variability since reliable data for TFETs are not available. Variability may further reduce the SNMs of the investigated topologies.

ACKNOWLEDGMENT The research leading to these results has received funding

from the European Community’s Seventh Framework Programme under grant agreement No. 619509 (project E2SWITCH). The work has been supported even by the Italian MIUR through the Futuro in Ricerca project RBFR10XQZ8. We thank S. Mantl and Q.-T. Zhao for many helpful discussions.

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