[IEEE Bipolar/Bicmos Circuits and Technology Meeting - Minneapolis, MN, USA (2-3 Oct. 1995)]...

download [IEEE Bipolar/Bicmos Circuits and Technology Meeting - Minneapolis, MN, USA (2-3 Oct. 1995)] Proceedings of Bipolar/Bicmos Circuits and Technology Meeting - A high performance 0.35 μm 3.3 V BiCMOS technology optimized for product porting from a 0.6 μm 3.3 V BiCMOS technology

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Transcript of [IEEE Bipolar/Bicmos Circuits and Technology Meeting - Minneapolis, MN, USA (2-3 Oct. 1995)]...



    Portland Technology Development, Intel Corporation, Aloha, Oregon


    A 0.35 pm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect.[l] A 2.5V version offers lower power and higher performance. A 3.fW BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6 pm 3.3V BiCMOS process. The design process for converting an existing production worthy 0.6 pm 3.3V BiChAOS design is described. The silicon results are described.


    Logic products have become mainstream technology driveirs with special process technology requirements. The performance of both the transistors and the interconnect system is highly olptimired to achieve the desired clock rate. Logic products typically have transistor counts between l o6 to lo7 transistors and lo4 to IO5 global interconnect signals. There are a large number of specialized circuits with analog simulation requirements; examples of which are memory structures, clock generators and special types of logic. The operating margin of these specialized circuit needs to be optimized for the process. Interconnect current density and transistor reliability limits require validation. Design teams have grown significantly in response to the size of the task. The 3.3V BiCMOS version of the 0.35 pm process was optimized to dramatically reduce the effort requireld to re-characterize performance and reliability limits. The relative strengths of transistors were matched to the previous process generation to maintain operating margins and reduce the need for redesign. The metal interconnect system was optimized with both speed and the currently density limits in mind. This resulted in minimal need to redesign for currently density limits, and moderate redesign for global RC limitations. This optimized 0.35 pm 3.3V BiCMOS process has permitted rapid and efficient porting of a microprocessor designed on a 0.61 pm 3.3V BiCMOS process.


    Transistors are built using shallow trench isolation which offers less lateral encroachment than LOCOS isolation. See Figures 1 & 2. Planarity is also enhanced for subsequent poly patterning. Both 2.5V and 3.3V transistors use complementary doped poly silicon ,with Ti

    capping on gate and soiirce-drains. The TiSi, sheet rho is less than 2 ohm/sq. The 2.5V and 3.3V versions of the process use 6 nm and 7' nm respectively. The N and P channel lengths ,for the i2.W version are 0.18 and 0.19 ym, while for the 3.3V version they are 0.25 and 0.21 pm respectively. Performance of the 2.5 and 3.3V transistors are shown in 'Table 1.

    P o l y s i l i c o n T i S i , I

    P - W e l l T r e n c h l s o l a t i o n

    Figure 1 Schematiic View of Transistor

    Figure 2 Photomicrograph of Transistor

    0-7803-2778-0/95/$4.00 0 1995 IEEE 43

  • Figure 4 Comparison of Performance Trends P- N- Channel Channel

    2.5 V 3.3 V

    TOX 7.00 6.00 7.00 6.00 nm Lg 0.37 0.33 0.41 0.33 pm Le 0.21 0.17 0.25 0.18 pm Id 0.35 0.32 0.68 0.66 mNym Gm 150 180 230 350 mS/mm S 80 80 80 80 mV/dec

    Table 1 Summary of Transistor Characteristics

    A CV/I performance metric has been used to provide a basis of comparison between the transistors in this work and other published results. Prior transistor results are included in this comparison regardless of their loff characteristics. Gate capacitance is computed from gate size and oxide thickness, while I and V come from ldsat at measured voltage. See Figure 3. By this metric the transistors reported in this paper are faster than any previously reported for 0.35 pm technology. See Figures 4 & 5. An exception is on P-channel device with a sub-threshold slope greater than 100 mV per decade and an unspecified Vt roll off.121

    1 * G a t e D e l a y oc C g * V / I ,

    Figure 3 Schematic of Speed Benchmark Circuit

    G l 8 G 1 I n t e l , 7 n m / 3 , 3 V a 5 I n t e l , 6 n m 1 2 . 5 ~ a/

    ,6 12 /


    D e I a \I

    e/-* * .i e// A /*

    Q / 9

    6 -- /

    -- ~ ,/ M / .//

    3 -- a/* -;? 0 F0 I I I I I

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    0 0.1 0.2 0.3 0.4 0.5 0.6 I

    N - C h a n n e l L g a t e ( p m )

    G a t e

    D e


    P u b l i s h e d D e v i c e s ~ s

    I n t e l , 6 n m / 2 . 5 V I n t e l , 7 n m 1 3 . 3 V e- @ @ /

    @ M / /cis 25 /

    0 0.1 0.2 0.3 0.4 0.5 0.6 I

    P - C h a n n e l L g a t e ( p m ) Figure 5 Comparison of Performance Trends

    The 3.3V technology includes NPN Bipolar devices used primarily for BiNMOS circuitry, using the N-Well as the collector, a separate P-base implant and a second poly layer for the N-emitter. The integration of this type of Bipolar transistor provides an f, of 18 GHz and does not materially degrade MOS device performance. [3]

    Four layer of AI-Cti metal and tungsten filled contacts and vias comprise the interconnect system. A Ti/Al-Cti/Ti/TiN metal stack is used for the first three layers. The forth layer uses a Ti/Al-Cu/TiN to be compatible with wire bonding. The interlayer dielectric between poly and M1 is BPSG. PTEOS is used between metal layers, and is formed with dep-etch. Contacts and vias are formed by tungsten deposition. Dielectrics and tungsten are planarized with chemical-mechanical polishing. See Figure 6.

    Figure 6 Process Cross Section


  • The high degree of planarization in the process permits tight pitches while maximizing metal density. RC performance and currently density limits aire optimized for logic products.


    A 3.3V 100 MHz BiCMOS 3.3M transistor microprocessor in 163 mm2 designed on a 0.6 pm four metal technology, was chosen to port to the 0.35 pm process described in this paper. The design was stable in manufacturing and provided a solid starting point. It consists of a super scalar integer unit, a floating point unit, separate 8kB instruction and data caches. A block diagram of the internal structure of the microprocessor is detailed in Figure 7. [4][5]

    6 4 1 b i t


    8 K B y t e

    C a c h e

    6 4 b i t

    6 4

    Figure 7 Block Diagram Of Processor


    Porting a design to a new process requires consideration of differential circuit & RC delays, reliability limitations, and characterization of special sensitive circuits. Additionally a comparison of design rules is necessary to determine shrink factor and techniques for database manipulation.

    The 3.3V BiCMOS version of the 0.35 nim process offered 25% delay reduction for BiNMOS gates and 33% for CMOS gates, for an average delay reduction of 29%. This would imply a clock rate increase of -40% clock rate improvement if RCs were not a limitation, and worst case speed paths were not primarily BiNMOS. [6][7]

    Extraction of new expected RC delays combined with performance data from standard cell re- characterization indicated that RCs would limit the speed up in clock rate. See Figure 8.

    C u n n u l i a t i v e S p e e d P a t h s c

    h S Clock Rate Figure 8; Expected Performance With and Without RCs

    Tables 2 8: 3 list the relative resistance and capacitance scaling differentially with respect to the 0.6 pm process. The data shows that M1 resistance should be a problem for any FIC that is in a critical path. The design methodology for the microprocessor, had limited the usage reducing the amount of rework required. M2 & M3 carry most of the global signals on the chip. Here more extensive layout intervention would be required to achieve the highiest clock rate potential. The product of the M2/M3 resistance scaling factor times the Cinter scaling factor is 0.82. PI value of 0.6 - 0.7 would have been required to not limit the clock rate.

    M1 __ Fill 2 M3 M4 Scaling 1.60 1.04 1.04 .70

    Table 2 0.6/0.35 pnn Process: Ratio of Metal Resistance

    Qate Cinter Ctot a Scaling 0.63 0.59 0.81 .63

    Table 3 10.6/0.3!5 l m Process: Ratio of Metal Resistance

    Table! 4 shovvs the ratio of lavg and lrms for the 0.35 pm processor running at 133 & 150 MHz. The current density liimitation in metal lines needs to be below the spec limit to not limit clock rate. The data indicates that the rule improvements in the 0.35 pm will provide the needed improvement. The current margin is converted to maximum operating temperature Table 5. The data in the table shows that the life time of the part will not be limited by electro-migration below 1 15 degrees C..


  • SILICON RESULTS: 13311 00 150/100

    lave ratio for metal 1.48 1.67 lave ratio for vias 1.06 1.20 lrms ratio for metal 1.53 1.63 lrms ratio for vias 1.10 1.17

    Table 4 lavg and lrms Scaling for the 0.35 pm vs the 0.6 pm processes

    M I M2 M3 M4 Contact Via 1 Via 2 Via 3

    lava Ratio 1.50 1.86 1.73 1.53 1 .oo 1 .oo 1.23 1.18

    133 MHz 150 MHz 120 117 120 120 120 120 120 118 118 115 118 115 120 120 120 119

    Table 5 Maximum Operating Temperature Per Conductor Type at 133 & 150 MHz

    Analog simulations of several of the most challenging sensitive circuits revealed that there would be adequate margin for experimentation.


    Simulations showed that there was adequate EM margin and solid performance for sensitive circuits, but the clock rate would be limited by global RCs. To achieve the highest clock rate extensive RC edits would be required. Further is was expected that some critical paths would be mostly BiCMOS and also require changes. The data showed that a simple shrink would