IEEE 2014 - 2015 CIRCUIT AND SYSTEM PROJECT TITLES

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CIRCUIT AND SYSTEM PROJECT TITLES 2014 – 2015

S.NO PROJECT TITLES DOMAIN YEAR1 A Current Regulator for Inverter-Based

Massively Column-Parallel ΔΣ ADCsCircuit and system 2014

2 Combined Three-State/PWM Signal Coding for Wideband High-Efficiency Class-S Amplifiers

Circuit and system 2014

3 A 3.6-to-1.8-V Cascode Buck Converter With a Stacked LC Filter in 65-nm CMOS


4 A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS


5 A 5-V 290-μW Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8-μmCMOS Using a Correlated-Level-Shifting Technique


6 A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS


7 A 10-Bit 40-MS/s Pipelined ADCWith aWide Range Operating Temperature for WAVE Applications


8 A 576-Mbit/s 64-QAM 4 × 4 MIMO Precoding Pocessor With Lattice Reduction


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9 Aroadband Low-Power Millimeter-Wave CMOS Downconversion Mixer With Improved Linearity


10 A Fast Algorithm Based on SRFFT forLength N = q × 2m DFTs


11 A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth


12 A Frequency Synchronization Method for aSelf-Oscillating PWM Signal Generator


13 A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers


14 A Quadratic-Interpolated LUT-Based Digital Predistortion Technique for Cellular Power Amplifiers


15 A Simple Ladder Realization of Maximally Flat Allpass Fractional Delay Filters


16 A Split-Path Sensing Circuit for Spin Torque Transfer MRAM


17 A Subthreshold Symmetric SRAM CellWith High Read Stability


18 A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator




19 A True 0.4-V Delta–Sigma Modulator Using a Mixed DDA Integrator Without Clock Boosted Switches


20 A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core


21 All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator


22 An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS


23 An All-Digital Despreading Clock Generator


24 An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme


25 An Analysis of Phase Noise in Realigned VCOs


26 An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs


27 An Integrated High-Voltage Low-Distortion Current-Feedback Linear Power Amplifier for Ultrasound Transmitters Using Digital Predistortion and Dynamic Current Biasing Techniques


28 An X-Band Slow-Wave T/R Switchin 0.25-μm SiGe BiCMOS


29 Bernoulli Low-Pass Filters Circuit and system 2014



30 Characteristics of LNA Operation inDirect Delta–Sigma Receivers


31 Combined Three-State/PWM Signal Coding for Wideband High-Efficiency Class-S Amplifiers


32 Compact CMOS Analog Counterfor SPAD Pixel Arrays


33 Conjugate Symmetric Discrete Orthogonal Transform


34 Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology


35 Dual-Basis Superserial Multipliers forSecure Applications and LightweightCryptographic Architectures


36 IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration


37 Latency Analysis and Architecture Design ofSimplified SC Polar Decoders


38 Leakage, Area, and Headroom Tradeoffs for Scattered Relative Temperature Sensor Front-End Architectures


39 Linear Analysis of the Vectorial Network Model


40 Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors




41 Modeling of a MOS Ultralow Voltage Astable Multivibrator for Energy Harvesting


42 Multi-Bound-Dependent Stability Criterion for Digital Filters With Overflow Arithmetics and Time Delay

Circuit and system

2014

43 Necessary and Sufficient Stability Criteria for a Class of Fractional-Order Delayed Systems


44 New Improved Algorithms for Compressive Sening Based on p Norm


45 Nonvolatile Multilevel Resistive Switching Memory Cell: A Transition Metal Oxide-Based Circuit


46 Novel One-Dimensional Sampling Method to Calculate Two-Dimensional Diamond-Shaped Discrete Frequency Distributions


47 Offset-Free Nonlinear MPC for Mismatched Disturbance Attenuation With Application to a Static Var Compensator


48 On Brune’s Tests Circuit and system 201449 On-Chip Measurement of Rise/Fall

Gate Delay Using Reconfigurable Ring Oscillator


50 Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial Interpolation Methods


51 Power-Reduction Technique Using a Single Edge-Tracking Clock for




Multiphase Clock and Data Recovery Circuits

52 Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector


53 Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM


54 Resilient Pipeline Under Supply NoiseWith Programmable Time Borrowingand Delayed Clock Gating


55 Spur Mitigation in High-Sensitivity GNSS Receivers


56 The Lin-Bose Problem Circuit and system 201457 Theoretical Analysis for Efficient

Design of a Piecewise Constant Spiking Neuron Model


58 Using 1-D Variable Fractional-Delay Filters to Reduce the Computational Complexity of 3-D Broadband Multibeam Beamformers


59 Variable Fractional Delay FIR Filter Design with a Bicriteria and Coefficient Relationship


60 Variable Step-Size Affine Projection Sign Algorithm


61 VL-ECC: Variable Data-Length Error CorrectionCode for Embedded Memory in DSP Applications



IEEE 2014 - 2015 CIRCUIT AND SYSTEM PROJECT TITLES

Engineering

Transcript of IEEE 2014 - 2015 CIRCUIT AND SYSTEM PROJECT TITLES