A 250MHz-to-4GHz ∆-Σ Fractional-N Frequency Synthesizer with Adjustable Duty Cycle

Chen-Wei Huang and Ping Gui Department of Electrical Engineering,

Southern Methodist University, Dallas, TX, USA chenweih@smu.edu; pgui@smu.edu

Abstract— A ∆-Σ fractional-N Phase-locked Loops (PLL)- based frequency synthesizer (FS) with a frequency range of 250 MHz to 4 GHz is presented. By employing the ∆-Σ fractional-N technique and utilizing the multi-phase clocks available in the ring-VCO of the PLL, the frequency synthesizer is capable of generating high-resolution and low-spur clocks with instant frequency switching. Moreover, the proposed FS has the ability to adjust clock duty cycle which is needed in applications such as time-interleaved ADCs, switched-capacitor circuits, and DC-DC converters.

I. INTRODUCTION Generating clocks with controllable frequency, phase, and duty cycle is essential for system synchronization. The key features of a frequency synthesizer (FS) include frequency range, switching speed, noise (jitters and spurs), and power consumption. Ring-VCO (voltage-controlled oscillator)-based FS is widely used due to its wide tuning range and low cost [1]-[2]. However, as the power supply continues to scale down, the tuning range of the VCO becomes smaller, which limits their usage in practical systems [3]. Although the VCO gain (KVCO) can be increased to achieve a wide tuning range, it has a major drawback of increased clock jitters [4]. In order to achieve a wide tuning range with a low supply voltage and a reduced KVCO, reference [5] employs a Flying-Adder (FA) architecture [6] to expand the frequency range. However, the practical highest frequency (1.1 GHz in IBM 0.13 um) is limited by the digital unit consisting of adders, DFFs, and multiplexers. Frequency multipliers (FM) have been widely used in DLL(delay-locked loop)-based FS [7]-[9]. The advantages of using an FM include lower power consumption and alleviated constraints on the VCO. Since the VCO only needs to generate a moderate frequency, KVCO can be designed to be small to achieve better noise performance. Both the FA synthesis architecture and the FM utilize the multiple-phase clocks available from either the VCO or the Voltage controlled delay lines (VCDL). This paper presents a ∆-Σ fractional-N frequency synthesizer which employs both the FA and FM techniques. The ∆-Σ fractional-N architecture

can generate clocks with low spurs and high frequency resolution [10]-[11], and is particularly effective for spread spectrum clocking (SSC) [12], whereas the FA and FM techniques are employed to increase the frequency range and provide instant frequency switching. In addition, the feature of adjustable duty cycle makes the proposed FS suitable for applications such as time-interleaved ADC, switched-capacitor circuits, and DC-DC converter, where the ability to adjust the clock duty other than 50% is required [13]-[15]. The paper is organized as follows. Section II presents the proposed synthesizer architecture and describes its operation. In Section III, the performance and the comparison of the proposed circuit are discussed and SPICE simulation is provided to verify the operation of the proposed techniques; a comparison of the proposed FS to existing methods is also presented. Finally, Section IV concludes the paper.

II. PROPOSED FREQUENCY SYNTHESIZER A. The Proposed Frequency Architecture Fig. 1 shows the proposed frequency synthesizer architecture that includes a ring-VCO-based ∆-Σ fractional-N PLL and a digital processing unit to generate the output clock CLK1, and a FM to generate CLK2 and CLK3. The ring VCO provides multiple reference signals with the same

This work was supported by Semiconductor Research Corporation Contract 1620.001.

Fig. 1. Proposed frequency synthesizer

978-1-4244-5309-2/10/$26.00 ©2010 IEEE 1839

frequency but evenly distributed phases that function as the references for the digital processing unit. In other words, the output clock period is built on this phase difference. The post processing digital unit, consisting of adders, multiplexers, and Flip-Flops, is used to synthesize the desired clock CLK1 and adjust the duty cycle. In order to explain the operation of the proposed frequency synthesizer, we first introduce the phase difference ∆ between adjacent outputs from the VCO: ∆ (1) where is the VCO period, and N is the number of VCO outputs. It is clear that by increasing the number of the VCO stages, ∆ becomes smaller, which increases the resolution. However, increasing the number of VCO stages will also increase the power consumption. Thus, there is a tradeoff between the resolution and power consumption. In our design, a four-stage differential VCO which provides eight clock outputs (N=8) was chosen. Details of the post processing unit that generates the desired frequency can be found in [6]. The frequency of output clock is given as, · · · 8

(2)

where is the reference frequency, Div is the feedback divide ratio in the PLL loop, and FREQ is the control signal for the digital unit. In theory, the frequency range synthesizable using the FA technique is from /2 to · /2 . (i.e. 250 MHz to 2 GHz based on 500 MHz VCO) However, the real circuit speed could be significantly below this number as will be discussed in Section III. B. A Simple and Fast Frequency Multiplier The detailed circuit of the FM in the proposed frequency synthesizer is shown in Fig. 2 which is used to generate a clock (CLK3) with frequencies 4 times that of the VCO frequency. A similar circuit is also used to generate the frequency that is 2 times faster than VCO. By using a PLL with tuning range of 500 MHz to 1 GHz, this frequency multiplier can produce output frequencies ranging from

250 MHz to 4 GHz. The frequency in the range of 1-2 GHz is produced using a 2x multiplier and the range 2-4 GHz using a 4x multiplier. The frequencies from 250 MHz to 500 MHz is produced using the FA. The first stage of the FM (Fig. 2) takes the VCO outputs (P0-P7) and produces pulse train signals (Q0-Q3) whose pulse width is half the desired output period. The second stage is a simple OR gate that combines the pulses together to generate the final clock (CLK). Since this is a simple digital circuit, it can run at much higher frequency than the FA architecture does. C. Adjustable Duty Cycle Clock Signals To improve the speed of the Flying-Adder, [16] adopts two-path topology to produce the final clock, CLK1. This is illustrated in Fig. 3, where CLK1 is generated by toggling the D-flip-flop whenever there is a rising edge in either path 1 or path 2. The phase difference between path 1 and path 2 is adjusted as half the period so that the output duty cycle is 50%. For the proposed circuit, this phase difference is controlled by the difference of sel1 and sel2, which are determined by signal “Dmode”. For an even- or odd-number control word FREQ, the duty cycle ratios are calculated as (3) and (4) respectively, 2 , (3)

12 , (4)

The duty cycle ratios with respect to FREQ and Dmode are given in Table I (Frequencies can be calculated by using Eq (2) regardless of the value of Dmode). The duty cycle of the PLL output clock is determined by the phase difference of the two signals from two paths. Table I shows one important characteristic of this architecture: the number of available duty cycles decreases as the frequency goes up. Since the duty cycle is the ratio of clock being high over the period, both parameters can only change by a step of ∆. This explains why a long period (low frequency) provides more flexibility for clock duty cycle adjustment.

Fig. 2. Proposed frequency multiplier (example for CLK3).

Fig. 3. Two-path topology in Flying-Adder Architecture

Path 1

Path 2

CLK1

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III. SPICE SIMULATION AND COM

The SPICE simulation was conductedproposed frequency synthesis architecture.was built in IBM CMOS 0.13 um technolosupply of 1.5 V. The controller in Fig. 1 through standard cells. The PLL has a tri-staa charge pump loop filter, a 4-stage differentgenerates 8 output signals, a multi-modulusin the PLL loop, and a ∆-Σ modulator able to3rd order outputs. Table II lists key speciproposed frequency synthesizer. This architecture holds a good featfrequency switching. Since the output clock the digital circuitry, by changing FREQ in thcan instantly change the clock frequencyvaluable feature especially for application frequency scaling for power reduction [17]-[ Figure 4 and Fig. 5 plot the frequency VCO output for the fractional-N PLL with 1∆-Σ modulator respectively. The divide ratthus the dynamic divide ratio will be modumodulator to get an average ratio as 50.5. I1st order ∆-Σ modulator fails to remove thewhile the 3rd order one effectively dithespectrum. Figure 6 plots the output clock signals oFA digital unit when VCO is at 1 GHz. changes from 10 to 8 and Dmode changes makes frequency and the duty cycle racalculated from (2) and (3), change from 80and from 30% to 50% respectively.

DUTY

Dmode FREQ 2 3 4 5

0 50.00% 33.33% 50.00% 40.00% 51 N/A N/A 25.00% 20.00% 32 N/A N/A N/A N/A3 N/A N/A N/A N/A4 N/A N/A N/A N/A5 N/A N/A N/A N/A6 N/A N/A N/A N/A7 N/A N/A N/A N/A

TABLE II SPECIFICATIONS

Process IBM CMOS 0.Supply voltage 1.5 V No. of VCO outputs N = 8 PLL reference frequency 16.6 MHz (60nVCO tuning range 500MHz ~ 1GHFA operating frequency 250 MHz ~ 1.1FM operating frequency 500MHz ~ 4GHCombined operating frequency 250MHz ~ 4GHOutput Duty Cycle See Table I

MPARISON d to verify the The test circuit

ogy with a power was synthesized

ate phase detector, tial ring VCO that feedback divider o generate a 1st or ifications for the

ture, i.e. instant is synthesized by

he digital unit, we . This will be a such as dynamic

[19]. spectrum of the

1st and a 3rd order tio is set as 50.5, ulated by the ∆-Σ It is clear that the e frequency spurs er the frequency

of VCO, FM and At 10 ns, FREQ from 2 to 0. This atio of FACLK, 00 MHz to 1 GHz

The first two plots of Fig. 6 showat 4 GHz (multiplied by 4) and 2which shows that the FM approach frequency clocks from VCO clocksFM techniques, the proposed Ffrequencies ranging from 250 MHz mode is turn on, a group of frequinstantly (by changing FREQ) but limited (1.1 GHz). On the contraryvery high frequency clock but requfrom the FN-PLL when switching tdesired. TABLE III shows the comand our attempt to include many funadjustability, spread spectrum, and in

TABLE I Y CYCLE WITH RESPECT TO AND (N=8)

6 7 8 9 10 11 12 13

50.00% 42.86% 50.00% 44.44% 50.00% 45.45% 50.00% 46.15%33.33% 28.57% 37.50% 33.33% 40.00% 36.36% 41.67% 38.46%16.67% 14.29% 25.00% 22.22% 30.00% 27.27% 33.33% 30.77%

N/A N/A 12.50% 11.11% 20.00% 18.18% 25.00% 23.08%N/A N/A N/A N/A 10.00% 9.09% 16.67% 15.38%N/A N/A N/A N/A N/A N/A 8.33% 7.69%N/A N/A N/A N/A N/A N/A N/A N/AN/A N/A N/A N/A N/A N/A N/A N/A

13 um

ns) Hz 1GHz Hz Hz

Fig. 4. Spectrum of VCO output, (1st order Σ-

Fig. 5. Spectrum of VCO output, (3rd order Σ

ws the FM output clocks, 2 GHz (multiplied by 2), can produce much higher s. By combining FA and FS can generate clock

to 4 GHz. When the FA uencies can be produced the highest frequency is

y, FM mode can produce uires certain settling time to different frequencies is mparison to other designs nctions, such as duty cycle nstant switching.

14 15 16

% 50.00% 46.67% 50.00%% 42.86% 40.00% 43.75%% 35.71% 33.33% 37.50%% 28.57% 26.67% 31.25%% 21.43% 20.00% 25.00%% 14.29% 13.33% 18.75%

7.14% 6.67% 12.50%N/A N/A 6.25%

-∆ modulation).

-∆ modulation).

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IV. CONCLUSION A digital frequency synthesizer with very wide tuning

range and adjustable duty cycle has been presented. The Flying-Adder architecture can instantly synthesize clocks that have wide frequency range whereas the frequency multiplier generate output clocks which expands the upper frequency range from that of the VCO. The ∆-Σ modulator is utilized to modify the clock frequency spectrum for either spur reduction or spread spectrum purpose. Moreover, the ability to adjust output duty cycle adds more flexibility to the proposed design.

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Fig. 6. VCO output, CLK1, CLK2, and CLK3 signals (bottom up).

(ns)FREQ: 10->8, Dmode: 2->0

TABLE III COMPARISON OF FREQUENCY SYNTHESIZERS

Our Work [2] [4] [6] [8] [9] [12] [13]

Type PLL PLL PLL PLL DLL DLL PLL DLL

Technology CMOS 0.13um

CMOS 0.18um

CMOS 45nm

CMOS 0.6um

CMOS 0.35um

CMOS 0.18um CMOS CMOS

0.35um Supply Voltage 1.5V 1.8V 1.3V 3.3V 3.3V 1.8V 3.3, 1.2V 3.3V Adjustable Duty

Cycle Table I No No No No No No 35%~70% @5%

Operating Frequency

250MHz ~ 4GHz

0.5GHz ~2.5GHz

1GHz ~15GHz

57MHz ~130MHz

120MHz ~1.1GHz

0.7GHz ~2GHz

125MHz ~1.25GHz

1GHz ~ 1.27GHz

Instant Switching Yes No No Yes Yes Yes No No

Spread Spectrum Yes, Σ-∆ No Yes, Σ-∆ No No No Yes, Σ-∆ No

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