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978-1-4244-2332-3/08/$25.00 © 2008 IEEE

3D Hall probe integrated in 0.35 µm CMOS technology for magnetic field pulses measurements

Joris Pascal, Luc Hébrard, Vincent Frick, Jean-Philippe Blondé Institut d'Électronique du Solide et des Systèmes (InESS), ULP Strasbourg – CNRS - UMR7163

BP20 – 23, rue du Loess, 67037 Strasbourg Cedex - France joris.pascal@iness.c-strasbourg.fr

Abstract—This paper presents a 3 dimensional magnetometer based on Hall effect sensors integrated without any post processing in a standard low cost 0.35 µm CMOS technology. The system is dedicated to magnetic pulses measurements under a strong static field. Two vertical Hall devices (VHD) are sensitive to the components of the magnetic field oriented in the plane of the chip, while a horizontal Hall device (HHD) is sensitive to the component of the magnetic field orthogonally oriented to the plane of the chip. 3 identical instrumental chains are integrated to perform amplification of the 3 Hall voltages. The system implements a compensation of the static magnetic field and allows to measure magnetic fields pulses with a resolution of 79 µT over a [5 Hz – 1.6 kHz] bandwidth. Pulses are in the range from hundreds of µT to tens of mT in the frequency range from 1 Hz to 10 kHz. The static field is compensated up to 1.5 T. The spatial resolution is 44 µm. The system power consumption has been optimized to 15 mW.

I. INTRODUCTION Magnetic pulses measurement with a high spatial

resolution requires tight constraints in electronics design since any wire exposed to a magnetic pulse turns out to be an inductive loop that generates non desirable currents. CMOS integrated system with dimensions in the µm scale gives the best answer to this constraint. Hall effect devices can be integrated in CMOS technology without any post processing and do not use any magnetic materials that could be driven into saturation within a strong magnetic field. Conventional Hall probes usually feature one horizontal Hall device (HHD). But measuring magnetic fields with only a single dimensional sensor can be quite tenuous, since one must guaranty an orthogonal orientation of the chip to the magnetic field to be measured. When such an orientation is difficult to achieve in the measurement environment, a 3D Hall probe has to be used. Recently, a 3D Hall probe with 3 HHDs packaged in a custom developed package that insures orthogonal alignment of the 3 Hall devices has been demonstrated [1]. Manufacturing such a system necessitates non standard packaging processes that increase complexity and cost. The first monolithic CMOS-integrated 3D Hall probe has been demonstrated in [2]. Nevertheless it has been integrated in a high voltage CMOS technology to be

compatible with conventional VHD structures [3]. The new type of VHD proposed in [4] allows to integrate VHD in standard 0.35 µm CMOS technology and exhibits similar performances as the conventional VHD of [3], especially in terms of resolution, that is 79 µT over a [5 Hz – 1.6 kHz] bandwidth. Associating two new VHDs orthogonally oriented one from each other, with a well known HHD such as described in [5], we designed a 3D Hall probe in a 0.35 µm CMOS technology. Section 2 deals with the Hall devices design, while section 3 explains the design of the instrumental chain. Finally, section 4 exposes the prototype that has been sent to fabrication and the first experimental results are discussed in section 5.

II. HALL DEVICES To measure a magnetic field along the 3 dimensions of

space with silicon Hall devices integrated on the same substrate of a planar CMOS technology, we must implement two different kinds of Hall devices. Indeed, two vertical Hall devices measure the magnetic field components oriented in the plane of the chip, while a horizontal Hall device measures the field component orthogonally oriented to the plane of the chip [6].

A. The Vertical Hall Device: VHD The conventional 5-contacts vertical Hall device is

depicted in figure 1 [7]. It is based on the structure devised more than 20 years ago in [8].

2pI

2pI

Figure 1. The conventional 5-contacts vertical Hall device

The biasing current flows from contacts C1 to contacts C2 and C3. The Hall voltage VH settles between the sensing

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contacts CS1 and CS2, and is proportional to the magnetic field component in the plane of the chip, and orthogonal to the biasing current lines. The sensitivity in V/T is given by:

)1(PIPH

VH IS=I

tqnrGG=

BV=S ⋅⋅

⋅⋅⋅

where t is the plate thickness and Ip the biasing current. G is the geometrical factor (G < 1) which models the reduction of VH due to the short circuit of Ip by the sensing contacts CS1 and CS2, as well as the short circuit effect induced by the biasing contacts C1, C2 and C3. GV ≈ 0.70 is a factor that models the intrinsic lower sensitivity of a VHD compared to a HHD of same thickness and doping level [4]. SI is the current related sensitivity. SI only depends on the plate doping level n and on the thickness t. Thus, whatever the plate geometry is, the theoretical maximum sensitivity remains the same as long as G = 1. In particular, this is the case if biasing and sensing contacts are point like, which is not possible in practice because of the finite size of the contacts.

Unfortunately, the conventional VHD of figure 1 is not efficient when it is integrated in a 0.35 µm CMOS technology, since such a technology has a very shallow N-well which is about 2 µm deep. In that configuration the biasing current partly flows through the sensing contacts where the Hall effect is negligible because of the highly doping level of the N+ contacts that induces short circuit effect. In that configuration G < 1. The sensitivity is therefore strongly reduced. In addition to this, we want to measure magnetic fields in the frequency range of 1 Hz to 10 kHz. In this low frequency bandwidth, the 1/f noise limits the resolution of such a structure. Experimental results show that the conventional VHD exhibits a resolution of only 719 µT when it is manufactured in 0.35 µm CMOS technology [4]. In order to improve the resolution by one order of magnitude, the solution proposed in [4] consists of measuring the Hall voltage outside the active area which is defined as the area where the current flows. This new device is illustrated in figure 2.

2pI

2pI

Figure 2. The new 5-contacts vertical Hall device

This new structure drastically reduces the 1/f noise at the sensing contacts leading to a much better resolution of 79 µT in spite of a low intrinsic sensitivity.

In order to measure the magnetic field in the two directions oriented in the plane of the chip, we placed two VHD orthogonally oriented one to each other (see figure 3).

Figure 3. The 2D Hall device, top view

B. The Horizontal Hall device: HHD The design of horizontal Hall devices has been well

described in [6]. Integrated in standard 0.35 µm CMOS technology, this devices can reach a resolution of 20 µT [5]. In order to measure the 3rd magnetic field direction which is orthogonal to the plane of the chip, we choose to implement the well known cross like Hall plate as depicted in figure 4.

Figure 4. The Horizontal Hall device, top view

In the layout, the 2 devices of figure 3 and figure 4 are

located closed one to each other leading to a spatial resolution nearly equal to the sum of the 2 devices lengths. The spatial resolution is then 44 µm.

III. INSTRUMENTAL CHAIN Three identical instrumental chains are integrated to

amplify the Hall voltages produced by the 3 components of the magnetic field. Figure 5 gives the architecture of the complete system.

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Figure 5. Complete 3D Hall probe system

The chip which contents the 3D Hall sensor and the instrumental chains is mounted on PCB1 which is located where the magnetic field operates. PCB2 is located outside this environment and receives the signals through an optical fibre transmission. We implemented an instrumental amplifier (IA) with a differential voltage to current converter as described in [9]. Chopper stabilization is performed to suppress the 1/f noise of the instrumental amplifier. As mentioned in the introduction, measuring magnetic pulses induces electro magnetic compatibility issues. Any piece of wire on the PCB which features the chip is a loop that can generate parasitic currents in the bandwidth of the magnetic pulses [1 Hz – 10 kHz]. The magnetic pulse is both the perturbing signal and the signal to be measured. That is the reason why we extract the modulated Hall voltage VHMOD at the chopper frequency 100 kHz. By this mean the useful signal can be transmitted out of the environment where magnetic pulses operate, without being spoiled by the parasitic currents induced on PCB1. A demodulation is performed outside the magnetic environment and the perturbations, as well as the 1/f noise of the IA, are suppressed by a low pass filter. Within the chip, we also demodulate the signal and filter it in order to suppress the 1/f noise of the instrumental amplifier. Then a compensation of the strong static magnetic field is achieved by storing the static value on an external capacitance through a 1st order low pass filter with a -3 dB cut-off frequency of 0.3 Hz. The output signal is amplified and transmitted to PCB2 in the baseband. Signal VH and VH’ (figure 6) can thus be

compared, and PCB1 immunity against the non desirable parasitic currents can be evaluated.

IV. PROTOTYPING An individual HHD has already been integrated , and the

results have been published [5]. The resolution of a 3D Hall probe is limited by the resolution of the VHDs. Individual VHDs have been manufactured and characterised with the modulation technique within the perturbing environment. These results lead us to dimension a monolithic version of the 3D Hall probe as described in figure 5. A prototype has been sent to fabrication, and the results will be available for the final paper. Next section presents the preliminary experimental results obtained on isolated VHDs integrated in 0.35 µm CMOS technology. These results allow us to evaluate the expected performances for the 3D Hall probe.

V. PRELIMINARY EXPERIMENTAL RESULTS In order to lower the power consumption of the final

system, which is intended to be supplied by a battery, we determined the lower VHD biasing current that provides the required resolution of 100 µT. Measurements of the resolution for increasing current values have been carried out. From figure 6, we see that setting the biasing current to 600 µA ensures the expected resolution of 100 µT.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

100

200

300

400

500

600

700

800

900

1000

Biasing current (mA)

Res

olut

ion

(uT

)

Figure 6. VHD resolution versus biasing current

In figure 7, we plot the response of the single VHD depicted figure 2.

These results allow us to determine the different gains to apply to the integrated amplifiers. The VHD exhibits 6.40 V/AT, and we minimized the biasing current of the device to 600 µA. Thus S = 3.84 mV/T is the sensitivity of the VHD. To measure magnetic field pulses of 20 mT within a static field up to 1.5 T, we settle the gain for the IA to GIA = 50, and the gain for the output amplifier OA to GAout = 100.

100

−8 −6 −4 −2 0 2 4 6 8−50

−40

−30

−20

−10

0

10

20

30

40

50

Magnetic Field (mT)

Hal

l Vol

tage

(uV

)

Figure 7. Response of the VHD, biasing current Ip = 1.12 mA, offset is nullified

The VHD architecture that is used in the final design has been tested experimentally with an instrumental chain implemented with discrete electronics. In the integrated version we switch the Hall voltage at the output of the Hall plates to perform modulation. This solution respects electro magnetic compatibility constraints since the small dimensions of the connections between the switches and the sensing contacts of the Hall plates do not allow parasitic currents to settle. The chain implemented with discrete electronics is similar to the integrated one described in figure 5. Nevertheless, instead of switching the Hall voltage at the output of the plates we implemented a periodic switching of the biasing current in the VHD at a 100 kHz frequency. As a result, the Hall voltage VH is also modulated since VH is proportional to the current (1). This is different than switching VH at the output of the Hall plate as implemented in the integrated version of the system. Indeed, when switching the biasing current, the parasitic voltages that settle by induction between the switches and the biasing contacts of the Hall device are negligible by comparison with the voltage across the biasing contacts of the VHD, which varies over a large dynamic (0 V to 3.3 V). On the contrary, VH varies only over a small magnitude of 6.4 µV, corresponding to a field of 1 mT and a biasing current in the VHD of 1 mA. By switching the biasing current in the Hall plate we propose a discrete version of the system which also respects electro magnetic compatibility constraints. With the discrete version of the system we carried out measurements. A magnetic pulse of 2.9 mT superimposed with a static field of 1.5 T has been measured (figure 8). The magnetic pulse has a bandwidth of 500 Hz and the pulse width is 20 ms. It is interesting to see that no perturbation appears, especially during the rising and falling times. Nevertheless, the resolution is slightly altered by the thermal noise of the discrete electronics.

16.8 16.81 16.82 16.83 16.84 16.85 16.86 16.87 16.88 16.89−0.15

−0.14

−0.13

−0.12

−0.11

−0.1

−0.09

−0.08

−0.07

time (s)

Hall

Volta

ge (

V)

Figure 8. Magnetic pulse measurement carried out over 1 dimension with a VHD

VI. CONCLUSION A first 3D Hall probe integrated in standard 0.35 µm

CMOS technology has been proposed. It is based on a conventional HHD associated with 2 new VHDs. Its resolution is limited by the resolution of the VHD and can reach 79 µT. Magnetic pulses measurement specificities have been discussed. First experimental results on isolated Hall devices describe the expected final performances of the system. A complete prototype has been sent to fabrication and experimental results will be available in the final paper.

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