A voltage driver using the rail to rail operation inCMOS 0, 25 Jlffi technology

FaY9al MEDDOUR, Zohir DIBI; Souhil KOUDAand Mohamed Amir ABDI

Laboratoire d'Electronique Avancee, Batna universityAlgeria

fayca1.meddour@yahoo.fr

OttoMANCKTechnique University of Berlin Germany

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II. RAIL TO RAIL OPERATION

The operational amplifier is a circuit building block that canbe used in many applications. However, there are only twomain configurations: the inverting and non-invertingconfigurations. Each of the configurations will be analyzednext to determine its input common mode requirements.

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Index Terms-operational amplifier; rail to rail; commonmode range.

Abstract- A rail to rail input common mode range is animportant requirement in operational amplifiers for someapplications. The most common method for implementing fullrange operation is by using a complementary differential pair. Itis simply a compound structure that consists of NMOS andPMOS differential pairs connected in parallel. The compoundstructure achieves rail to rail operation; however, it producesvariations in the transconductance over the input common moderange. The variations obstruct the design of an optimaloperational amplifier, to avoid the problem of transconductancevariations, an other structure, consists of two op-amps one n-typeand the other p-type controlled by a digital control system, isproposed to achieve the "rail to rail" operation. The layout ofthis structure is involved with CMOS O,25pm technology.

I. INTRODUCTION

Operational amplifiers are the back bone for many analogcircuit designs [1-5]. it is used in numerous applications suchas amplifiers and filters. The differential amplifier is used asthe input stage for operational amplifiers. The problem is that itwill behave as a differential amplifier only over a limited rangeof common-mode input. Therefore, to make the operationalamplifier versatile, its input stage should work for rail to railcommon-mode input range[6]. The most common method toachieve this range is to use a complementary differentialamplifier at the input stage. This method uses an n-type and ap-type differential pairs simultaneously. Although the methodachieves a rail to rail common-mode input operation, itintroduces suboptimal operational amplifiers. This is due to thenon-constant transconductance (gm) of the complementarydifferential amplifier. However, there are methods that keep gmvariations small over the entire input common mode range [7­11 ].

In this paper, we propose an other structure (VoltageDriver) to achieve the "rail to rail" and to avoid the problem oftransconductance variations, this structure "rail to rail" isconsists of two op-amps one n-type and the other p-typecontrolled by a digital control system. The layout of thisstructure is involved with CMOS O,25Jlm technology.

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Figure 1. Op Amp in: (a) inverting configuration (b) non-invertingconfiguration

A. The Input Stage

In CMOS technology the differential amplifier can berealized using a PMOS or NMOS differential pair. There areseveral tradeoffs that determine which differential pair to use[12]. One criterion that is considered in making the choice isthe common mode input range to analyze the common modeinput range of the NMOS differential input stage, a simplifieddiagram will be used as shown in Figure 2. Severalmodifications are made to the simple differential pair in actualimplementation such as active loads and cascodes, howeverthis is sufficient for the purpose of illustration. The rangeextends from the positive supply to Vgs+VDsat above thenegative supply. This minimum voltage is needed to keep theNMOS differential pair and the tail current source in saturation.

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Figure 2. NMOS differential pair common mode input range

A similar analysis can be carried out for the PMOSdifferential pair shown in Figure 3. The range extends fromVgs+VDsat below the positive supply to the negative supply.This minimum voltage is needed to keep the PMOS differentialpair and the tail current source in saturation.

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Therefore, the total effect is that the complementary differentialpair is always working and the rail to rail common mode inputrequirement is met. It should be noted that for common modeinput in the middle region both pairs are working, this will havea significant effect on the performance of the circuit.

III. DRIVER OF CONTROLED VOLTAGE

Our driver is composed of two operational amplifiers, oneis n-type and the other is p-type.

A. P-type operational amplifier

This operational amplifier consists of the polarization stage(current mirror type cascode), the differential amplifier and theoutput stage, the polarization stage is used to polarize thedifferential pair and the output stage. The pair differential is P­type, it is composed of two transistors MOS p-type.

B. N-type operational amplifier

The n-type operational amplifier consists of the same stagesof the p-type operational amplifier, with differential paircomposed of two n-type MOS transistors.

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Figure 3. PMOS differential pair common mode input range

The simple differential pair can not meet the rail to railcommon mode input requirement. A possible solution to theproblem is to use both NMOS and PMOS differential pairssimultaneously. The resulting compound differential pair iscalled the complementary differential pair and is shown inFigure 4.

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Figure 4. Complementary differential pair common mode input range

For low common mode input, the PMOS differential pair isin saturation and NMOS is off. For high common mode input,the NMOS differential pair is in saturation and PMOS is off.

The operating principle of our voltage driver is as followsUpperrange_e (input active high): we make the n-typeamplifier on and off the p-type amplifier and vise versa.Adc-pd (input active high): power down can be deactivatedtwo operational amplifiers.

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TABLE!. DRIVER PRINCIPLE When we injected at the input a voltage range of 0 to 0.6 Vthe output voltage does not follow the input voltage, but for thevoltage range 0.6 to 5V the same input voltage is found at theoutput. We can then say that the N-type amplifier allow thepassage voltage of 0.6 to 5 V.

According to the two previous simulations it appears clearlythat to allow the passages of voltage range of 0 to 5 V we usedboth n-type and p-type operational amplifiers in parallel.

IV. DC SIMULATIONREsULTATS

A. The pop-amp activated and the n op-amp disabled

When we injected at the input a voltage range of 0 to 4.4Vthe same input voltage is found at the output, but for thevoltage range 4.4 to 5V we can see that the output voltage doesnot follow the input voltage. We can then say that the P-typeamplifier allow the passage voltage toO to 4.4V.

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Figure 8. DC simulation results ofN and Pop-amp

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The figure 8 shows the DC simulation results for both typeoperational amplifiers. The p-type amplifier works well in the 0to 0.6V interval. The both amplifiers involved at the same timein the 0.6 to 4.4V interval, we can activate the n or p-typeamplifier. At the interval 4.4 to 5V the n-type amplifier workswell.

Figure 6. Simulation resalts the pop-amp activated and the n op-ampdisabled

B. The n op-amp activated and the pop-amp disabled

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Figure 7. Simulation resalts the n op-amp activated and the pop-ampdisabled

V. LAYOUT OF A SWITCH

Figure 9 represent the layout ofour Voltage Driver and adigital control system; fabricated in CMOS O,25J.1m to link themwe used four levels ofmetals METAL1, METAL2, METAL3 andMETAL4.

Part A is the n-type Operational amplifier in where weused FINGERS option to reduce the size of the space occupied.Part B represent p-type Operational amplifier. Part C and Drepresent respectly the layout of the digital control system andthe capacity.

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Figure 9. Layout of the Voltage driver and a digital control system

VI. CONCLUSIONS

In this work, we have proposed the rail to rail operation witha voltage driver, to resolve the problem of transconductancevariations. Our circuit consists of two operational amplifiers, nand p-type and a digital control system. The target circuit isverified by simulations results. The fabricated circuit in CMOS0,25 Jlm technology has been described and reduced to 363 x200 Jlm2.

REFERENCES

[1] R.Hogervorst, R.1.Wiegerink, P.A.L de jong, 1.Fonderie, R.F.Wassenaarand 1.H.Huijsing "CMOS low-voltage operational amplifiers withconstant-gm rail-to-rail input stage" Proceedings of the IEEEInternational Symposium on Circuits and Systems, pp. 2876-2879, 1992.

[2] S. Sakurai and M. Ismail, "Robust design of rail-to-rail CMOSoperational amplifiers for a low power supply voltage," IEEE Journal ofSolid-State Circuits, vol. 31, no. 2, pp. 146-156,1996

[3] C. Hwang, A. Motamed, and M. Ismail, "Universal constant-gminputstage architecture for low-voltage op amps," IEEE Trans. Circuitsand Systems-I, vol. 42. no. 11, pp. 886-895,1995

[4] S. Sakurai and M. Ismail, Low-Voltage CMOS OperationalAmplifiers:Theory, Design and Implementation, Kluwer AcademicPublishers, 1995.

[5] S. A. Mahmoud and A. M. Soliman, "The differential differenceoperational floating amplifier: a new block for analog signal processing,"IEEE Trans. Circuits Syst. II, pp.148-158, 1998.

[6] K. M. AbdelMoneim S. A. Mahmoud"3V CMOS Rail to Rail Op-Amp"IEEE Microelectronics pp 373-376- December 2007

[7] 1. H. Huijsing, R. Hogervorst, and K.-1. de Langen, "Low-power low­voltage VLSI operational amplifier cells," IEEE Trans. Circuits andSystems-I, vol. 42. no. 11, pp.841-852, November 1995.

[8] R. Hogervost, 1. P. Tero, and 1. H. Huijsing, "Compact CMOS constant­gm rail-torail input stage with gm-control by an electronic zener diode,"IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp. 1035-1040, July1996.

[9] R. Hogervorst, S. M. Safai, and 1. H. Huijsing, "A programmable 3-VCMOS railto- rail opamp with gain boosting for driving heavy loads,"IEEE Proc. ISCAS 1995, pp. 1544-1547.

[10] C. Hwang, A. Motamed, and M. Ismail, "LV opamp with programmablerail-to- rail constant-gm," IEEE Proc. ISCAS 1997, pp. 1988-1959.

[11] C. Hwang, A. Motamed, and M. Ismail, "Universal constant-gm input­stage architecture for low-voltage op amps," IEEE Trans. Circuits andSystems-I, vol. 42. no. 11, pp. 886-895, November 1995.

[12] David A. Johns and Ken Martin, "Analog Integrated Circuit Design",New York:Wiley, 1997.