A PULSE-BASED FULL-BAND UWB TRANSCEIVER SoC IN 0.18gmSiGe BiCMOS

Haolu Xie, Siqiang Fan, Xin Wang, Albert Wang, Zhihua Wang* and Hongyi Chen*Dept. of ECE, Illinois Institute of Technology

3301 S. Dearborn St., Chicago, IL, (312)-567-6912,* Institute of Microelectronics, Tsinghua University, Beijing, China

ABSTRACTIn this paper, a single-chip pulse-based, non-

carrier, full-band, low power ultra wideband (UWB)transceiver system-on-a-chip (SoC) for high datarate wireless video/audio/multimedia streamingapplications is presented. This UWB SoC featuresa single full-band (7.5GHz bandwidth from 3.1GHzto 10.6GHz), pulse-based non-carrier architectureto achieve high throughput (>100Mbps) and highsimplicity. It consists of low-noise amplifier (LNA),correlator, integrator, pulse generator, powerswitches and timing controller. This digital-readyUWB SoC features an on-chip analog-to-digitalconverter (ADC). The SoC uses BPSK modulation,Gaussian pulsing, and a global switching techniquefor power reduction. As the result, the averagepower consumption of the transceiver (no ADC) is6mW only. The SoC is designed in a commercial0.18gm SiGe BiCMOS technology.

1. INTRODUCTIONUWB radio development is gaining momentum

since the FCC opened the door for commercialdevelopment in 2002 [1]. The FCC allocatedfrequency spectrum is the unlicensed 3.1-10.6GHz.To avoid interference with existing wirelessapplications, UWB signal power mask is set to bein the noise floor level for normal wirelesstechnologies. Key advantageous features for UWBradio include ultra wide bandwidth for extremelyhigh data rate (to multiple Gbps), very low power,most-digital architecture easy for BiCMOSimplementation, hence low costs. Currently, thereare two pending IEEE UWB standard proposals,i.e., MB-OFDM and DS [2, 3], both dividing the7.5GHz UWB bandwidth into multiple sub-bandsand use carrier in radio transmission, whichcomplicate base band design and greatly reducedata throughput of UWB chips. To take fulladvantage of the original UWB radio technology [4,5, 6], we designed a fully pulse-based, non-carrier,single-band (7.5GHz) UWB transceiver SoC. Thisis a fully integrated most-digital UWB SoCfeaturing single 7.5GHz band design for high datarate, non-carrier and global switching technique for

low power, simple BPSK modulation, and fast on-chip ADC.

Correlator

Figure 1: UWB SoC System Architecture in This Paper.

II. ARCHITECTURE AND BLOCKSThe pulse-based non-carrier system

architecture was presented in this paper thatoperates in a single-band mode across the whole3.1 GHz to 10.6GHz (a 7.5GHz bandwidth) to boostthe signal data rate capable for multiple Gbps. Fig.1 shows the UWB system block diagram. Inreceiver, the first block is an ultra wideband(7.5GHz) LNA. The second block is a correlatorthat correlates the incoming signals with thetemplate pulses for signal selection. An activeintegrator block follows to improve the receivedUWB signals timing synchronization and signalnoise ratio, which will be digitized by the hi-speedADC circuit for host applications. In the transmitter,the main element is a pulse generator thatgenerates the UWB pulse signals. BPSKmodulation scheme is used in this design forsimplicity.

A. Pulse Generator & BPSK ModulationPulse generator produces the required UWB

pulse signals that are sent to antenna forbroadcast [7]. Fig. 2 shows the pulse generatorschematic containing an inverted delay stage anda NOR gate block, with the latter for impulse-likefunction generation. The critical pulse width iscontrolled by transistor Ml and M2 channel length.BPSK modulation is selected in this design to

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simplify the de/modulation circuits, whichmodulates the data symbols into a sequence ofUWB pulses. Various data rates are supported bychanging variable-length spreading codesequences, ranging from 1 to 10 pulses typically.Fig. 3 shows the BPSK circuit. The transmitter isan all digital circuit in this design.

TVddTddV T

Figure 2: Pulse Generator Circuit Schematic..a

Input

Figure 3: BPSK Modulation Circuit Schematic

B. LNA Circuit with Power SwitchAn ultra wideband LNA is critical to the single-

band UWB SoC where the challenge is to maintainthe broadband matching over the 7.5GHz band(3.1-10.6GHz) [6]. To ensure the performancewhile maintain design simplicity, a SiGe HBTbased shunt-series topology is used for this7.5GHz LNA. Fig. 4 shows the LNA schematics.Since LNA is one of the largest power consumingblocks, a global switching technique is devised toturn on/off the LNA and all other major blocks ofthe UWB SoC according to the pulse signal trains,which will be discussed later.

PowerSwitch

Vdd

L C2

RFOUT

RFIN

Figure 4: A 7.5GHz UWB LNA Circuit with Power Switch

C. Correlation-Type Demodulator Circuit withPower SwitchA correlator circuit is used to select the desired

signals from UWB receiver by multiplying theincoming pulse trains with the template pulses. Keyspecs include linearity, conversion gain, and noise,etc. In this design, we chose a SiGe BJT single-balanced multiplier using a linearized trans-conductance topology as shown in Fig. 5, whichcan suppress common-mode noise at output whileachieving high gain and good linearity. The outputsare positive and negative pulse trains accordingthe BPSK modulation scheme used. A powerswitch is added to turn on/off the correlator circuitaccordingly to reduce the power dissipation.

An active integrator block is used to improvethe selected UWB pulse signal noise ratio from thecorrelator, which is realized by an Op Amp basedR, C integrator circuit with 20dB voltage gain atleast.

Power VddSwitch_ 1

j Output

- Pulse Templae lse TemplateInput

LsVbl GND

Figure 5: Correlator Circuit with Power Switch

D. ADC with Power SwitchAn on-chip BJT based ADC block is included to

make this UWB front-end digital-ready. The ADCused in this paper is over-designed. The 10 bitsresolution and 500Msps sampling rate canaccommodate the 10OMbps throughput BPSKUWB SoC with extra headroom to cover othermore complicated modulation schemes in thefuture. Fig. 6 shows the ADC block diagram. Toensure the very high resolution and sampling rate,we selected a two-stage folding-interpolationstructure for the ADC. The pre-processed UWBpulses come to ADC into the track/hold block first,and then go through resistor reference ladder andpre-amplifier bank, before moving into the coarse &fine ADC paths. The coarse ADC has 4bitresolution and the fine ADC has 6bit resolution.The pre-amps are used to drive the comparatorsand first stage folding amplifiers. Two foldingamplifier stages are needed to generate proper

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voltage levels for comparators. Details inschematics are not discussed here due to pagelimitation.

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Figure 6: ADC Block Diagram

E. Timing Control CircuitTiming is critical to Whe full pulse-based non-

carrier UWB SoC, which is also important to ourproposed global switching technique. A DLL isused in the timing control block for better jitterperformance, hence accurate timing in our UWBreceiver using pulse template. A sliding correlationmethod is used to ensure the synchronization [4, 8].Fig. 7 shows the timing control circuit functionaldiagram, which consists of delay lines and controlcircuit. The synchronous acquisition is controlledby the input signal of the timing control circuitcoming from the ADC. When the timing controllerdetects the acquisition mode, the multiplexer staysthe same line. If the timing is not correct, it keepsadding the tap-delay until it synchronizes.

rxdata

Figure 7: Timing Control Circuit Block

F. Global Power SwitchingCompared to other existing UWB transceiver

designs using carriers [2, 3], this full pulse-basednon-carrier UWB SoC has lower powerconsumption. To further reduce the power, weproposed a global power switching technique thatcontrols all major blocks including LNA, correlator,

matched filter, DLL and ADC. The concept isbased on the fact that our non-carrier UWB SoCprocesses pulse signals that are discontinuous intime domain. Hence, all circuits need not alwaysstay in ON state as in traditional circuits where thestand-by operation consumes a large amount ofpower. Using the global power switch technique,when there are no pulses signals, the circuits stayOFF to reduce power. In circuit implementation,extra shutdown devices controlled by DLL areadded to the biasing path to realize powerswitching as illustrated in Fig. 4 & 5 for LNA andcorrelator circuits. This global switching techniquegreatly reduces the total power consumption of theUWB SoC. For example, at 100Mbps, the LNApower can be at least 10 times smaller than that ofnon-switching one.

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0 Cn.5 1.5 12. 3 35 41 ~~~~~~~~~~~~~~~ResG 5 1.5 2 2.5 3 2 5

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C C 1.5 2 3 12 4

TrE 0

(a) (b)Figure 8: Simulated System-Level Waveform at (a) Transmitterand (b) Receiver

111. MEASUREMENT AND SIMULATION RESULTFig. 8 shows the system level simulation

waveform at the receiver and transmitter. Thedesigned pulse width is 800ps for high data rate(>100Mbps). Fig. 9 shows the measurementresults of the impulse at the transmitter. Themeasured gain and noise figure for the LNA circuitare shown in Fig. 10, which shows this ultrawideband 7.5GHz LNA can achieve decentperformance of a quite flat high gain of 10dB and alow noise figure (NF) better than 4dB across thewhole 3.1 GHz to 10.6GHz band. Fig. 1 1 shows thesimulated the correlator conversion gain. Fig. 12shows preliminary simulation data for the ADCblock at output points fine ADC. The achieved keyspecs for the ADC are: 1 Gb resolution, 50OMspssampling rate, INL - 0.8LSB, DNL-0.5LSB andSINAD-57dB. Critical specs for all key buildingblocks are summarized in Tables 1 & 2.

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mmmm 7120pV 2.p

Figure 9: The Output Impulse Measurement Result

1 u01

43

Start 3.10000 GHz Stop1.00 GHz|Figure 10: LNA Gain and Noise Figure Measured Results

Conversion Gain

20 r L1.00G 3.75G 6.500 9.25Gfreq ( Hz )

Figure 1 1: Correlator Conversion Gain Simulation Result

Transient FResponse

0.00 I 10.n 30, n lSn 46nnmtme ( s

Figure 12: Simulated ADC output curves at fine ADC

Table 1: Key Block Performance Summary

DataRate Sequence Pulse PowerBPSK Data Rate Lengths Width

Transmitter lOOM- 1-10 50slGpps - -1 Os- 0m

Si 1 <-5dB, NF Bandwidth PowerLA S12<-20dB 3. 3mWLNA S21=10dB, <4dB 10.6GHz (switching

S22<-8dB ___ mode)Conversion Gain NF ] Power

Correlator 0.0dB <12dB 0.2mW (switching________________________________________________________mode)

Resolution INL/DNL//Speed SINAD Power

ADC 914mW (non-10 0.8LSB/0.5LSB/ switching mode)

bits/500MHz 57dB 132.53mWI_______________I______ (switching mode)

Table 2: UWB SoC Performance SummarySPECs Values

Total voltage gain 65-70dBTotal NF -6dB

Power (non-switching mode) 40mW (w/o ADC)Power (switching mode at 4mW (w/o ADC)

100OMbps)Data rate 1 00Mbps to 1 GbpsSupply 3.0V

Technology 0.18,um SiGe BiCMOS

IV. CONCLUSIONIn this paper, we present the design a pulse-

based, non-carrier, low-power, 7.5Ghz full-bandUWB transceiver SoC with on-chip ADC. The datathroughput is 100Mbps. The SoC features non-carrier impulse operation for low power, single7.5GHz band operation for high data rate, simpleGaussian pulsing and BPSK modulation, globalpower switching for power reduction, and 1 Ob500Msps integrated ADC for digital output. TheSoC is designed in a commercial 0.18tm SiGeBiCMOS technology.

REFERENCES

1. FCC First Report and Order, FCC 02-48, February 14, 20022. IEEE 03268r3P802-15 TG3a Multiband CFP3. IEEE 15-04-0137-03-003 a Merger2 Proposal DS-uwb-

update4. T. Terada, S. Yoshizumi, Y. Sanada, "Transceiver Circuits

for Pulse-Based Ultra-Wideband," IEEE ISCAS, 20045. Y.J. Zheng, Y. Tong, J.G. Yan, Y.P. Xu, W.G. Yeoh, F.J. Lin,

"A Low Power Noncoherent CMOS UWB Transceiver ICs"IEEE, RFIC Symposium, pp 347-350, June 2005

6. Sangyoub Lee, "Design and Analysis of Ultra-wideBandwidth Impulse Radio Receiver," Ph.D. Thesis,University of South California, CA, 2002

7. Y.R. Ko, B.G. Bae, J.H. Park, S.1. Bang "Structure Proposalof the TDMG Pulse Generator for Single Band UWBSystems" IEEE. IECON, Vol. 3, pp. 2641 - 2645, 2004

8. B. Kim, T.C. Weigandt, P.R Gray, "PLLIDLL System NoiseAnalysis for Low Jitter Clock Synthesizer Design," IEEE Int.Symp. Circuits and Systems, Vol. 4, pp 31-34, June 1994

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