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Ch.5 - Exercises Solutions Q.1 Describe the advantages of multi-bit quantization in ΣΔ- modulators. Solution: Multi-Bit Achievable SNR High Stability High Power Consumption High Chip Area High Jitter Sensitivity Low Slew Rate Required Low Linearity Requirements High Dither Tolerance High Circuit Complexity High Q.2 What is the advantage of having a well-defined gain in multi- bit quantizers relatively to ΣΔ-modulator theory? Solution: When a system containing a binary quantizer is replaced by its linear model, the estimate of the quantizer gain should be found from extensive numerical simulations, otherwise, misleading results may be obtained from the linear model. In the case of multi-bit quantizers relative to ΣΔ-modulator having a well-defined gain allows for a better estimate of the NTF during the design process than the single bit case. Q.3 Describe how Dynamic Element Matching (DEM) techniques can be employed to improve the performance of high order multi-bit sigma delta modulators.

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Page 1: How To Design Sigma-Delta AD-Convertersextras.springer.com › ... › ch5_ExercisesSolutions.docx · Web view= [1.1, 1.03, 0.97, 0.9]. A constant digital value of 3 is the input

Ch.5 - Exercises Solutions

Q.1Describe the advantages of multi-bit quantization in ΣΔ-modulators.

Solution:

Multi-Bit

Achievable SNR High

Stability High

Power Consumption High

Chip Area High

Jitter Sensitivity Low

Slew Rate Required Low

Linearity Requirements High

Dither Tolerance High

Circuit Complexity High

Q.2What is the advantage of having a well-defined gain in multi-bit quantizers relatively to ΣΔ-modulator theory?

Solution:When a system containing a binary quantizer is replaced by its linear model, the estimate of the quantizer gain should be found from extensive numerical simulations, otherwise, misleading results may be obtained from the linear model. In the case of multi-bit quantizers relative to ΣΔ-modulator having a well-defined gain allows for a better estimate of the NTF during the design process than the single bit case.

Q.3Describe how Dynamic Element Matching (DEM) techniques can be employed to improve the performance of high order multi-bit sigma delta modulators.

Solution:DEM algorithms are employed by selecting which element of the DAC to use in order to represent the digital input coming from the quantizer (i.e. typically a thermometer-coded digital input). Many DEMs not only linearize the feedback DAC in a time-average sense by swapping the DAC elements around (i.e. as simple RES does), but swap the elements in such a way that the noise spectrum resulting from the elements swapping is not white but first-order noise-shaped, so that it is suppressed in the signal pass band. Important to note is that the DAC noise being shaped is the one resulting from the mismatch error introduced by the uneven spacing of the DAC levels, rather than the quantization error.

Page 2: How To Design Sigma-Delta AD-Convertersextras.springer.com › ... › ch5_ExercisesSolutions.docx · Web view= [1.1, 1.03, 0.97, 0.9]. A constant digital value of 3 is the input

Q.4A 5-level feedback DAC is to be designed for a sigma-delta modulator. The DAC elements have component values E[0:3] = [1.1, 1.03, 0.97, 0.9]. A constant digital value of 3 is the input to the DAC. Write down the sequence of analog output values for 4 clock cycles, assuming the elements are used starting from E[0] without the use of DEM.

Solution:

Input V(n) Elements Selected DACout(n)

3 DACout(0) = 1.1+1.03+0.97 = 3.13 DACout(1) = 1.1+1.03+0.97 = 3.13 DACout(2) = 1.1+1.03+0.97 = 3.13 DACout(3) = 1.1+1.03+0.97 = 3.1

Q.5Using the DAC of Q.4, write down the sequence of analog output values for 4 clock cycles, assuming the elements are used starting from E[0] using Data Weighted Averaging (DWA).

Solution:

Input V(n) Elements Selected DACout(n)

3 DACout(0) = 1.1+1.03+0.97 = 3.13 DACout(1) = 0.9+1.1+1.03 = 3.033 DACout(2) = 0.97+0.9+1.1 = 2.973 DACout(3) = 1.03+0.97+0.9 = 2.9

Q.6Determine the mismatch error sequence found in part Q.4 and Q.5. Discuss the presence of limit cycles.

Solution:

NO DEMDACout(0) = 1.1+1.03+0.97 = 3.1 e(0) = 3.1 - 3 = 0.1DACout(1) = 1.1+1.03+0.97 = 3.1 e(1) = 3.1 - 3 = 0.1DACout(2) = 1.1+1.03+0.97 = 3.1 e(2) = 3.1 - 3 = 0.1DACout(3) = 1.1+1.03+0.97 = 3.1 e(3) = 3.1 - 3 = 0.1

Average error: 0.1+0.1+0.1+0.1

4=0.1 -> at least one tone will be present in the spectrum.

Considering that the DAC generated tone may interact with the modulator, multiple tones will probably result.

Page 3: How To Design Sigma-Delta AD-Convertersextras.springer.com › ... › ch5_ExercisesSolutions.docx · Web view= [1.1, 1.03, 0.97, 0.9]. A constant digital value of 3 is the input

DWADACout(0) = 1.1+1.03+0.97 = 3.1 e(0) = 3.1 - 3 = 0.1DACout(1) = 0.9+1.1+1.03 = 3.03 e(1) = 3.03 - 3 = 0.03DACout(2) = 0.97+0.9+1.1 = 2.97 e(2) = 2.97 - 3 = -0.03DACout(3) = 1.03+0.97+0.9 = 2.9 e(3) = 2.9 - 3 = -0.1

Average error: 0.1+0.03−0.03−0.1

4=0 -> No tones. The DWA algorithm achieves zero

average error due to the sum of input codes being 12, which corresponds to an exact multiple of the number of the DAC elements.

Q.7Using the DAC of Q.4, write down the sequence of analog output values for 4 clock cycles, assuming the elements are used starting from E[0] using Individual Level Averaging (ILA) for the digital input sequence 1,3,1,3.

Solution:

ILAInput V(n) Elements Selected DACout(n)

1 DACout(0) = 1.1 = 1.13 DACout(1) = 1.1+1.03+0.97 = 3.11 DACout(2) = 1.03 = 1.033 DACout(3) = 0.9+1.1+1.03 = 3.03

Q.8In the Toolbox, simulate Q.5 and Q.7 and verify your results are in accordance with your answers in Q,5 and Q.7.

Solution:

To verify Q.5:

In the Toolbox type - load_par - into the Matlab command window.

Open the model - testbench_DEM.

Type:>> dac.dem_dcin=3;>> dac.dem_select=2;>> dac.elecount = 4;

Page 4: How To Design Sigma-Delta AD-Convertersextras.springer.com › ... › ch5_ExercisesSolutions.docx · Web view= [1.1, 1.03, 0.97, 0.9]. A constant digital value of 3 is the input

>> dac.elements = [1.1, 1.03, 0.97, 0.9];

into the Matlab command window to set the model parameters according to Q.5.

Run the simulation and open the time scope relative to the DWA algorithm. The results are shown below:

As it can be seen the error sequence is in accordance with the results of Q.5 (i.e. and Q.6), therefore confirming the correct calculations made in Q.5.

To verify Q.7:

In the Toolbox type - load_par - into the Matlab command window.

Open the model - testbench_DEM.

Double-click on the input sequence block and enter the sequence - 1 3 1 3.

Type:>> dac.dem_select=1;>> dac.elecount = 4;>> dac.elements = [1.1, 1.03, 0.97, 0.9];

into the Matlab command window to set the model parameters according to Q.7.

Run the simulation and open the time scope relative to the ILA algorithm. The results are shown below:

Page 5: How To Design Sigma-Delta AD-Convertersextras.springer.com › ... › ch5_ExercisesSolutions.docx · Web view= [1.1, 1.03, 0.97, 0.9]. A constant digital value of 3 is the input

Analyzing the ILAOUT signal it can be seen that the first 4 cycles follows what found in Q.7, hence confirming correct calculations. Note however that the simulation starts from the value 3 instead of 1 and that the repeating sequence is actually longer than 4, so it is important to choose the starting point of the analysis wisely. Therefore, as an example, in the case shown in the figure above the reader should start the evaluation from the error 0.1 at around 8.375 of the time axe.