Homework 6

1. Problem:(a) Using the figures on pages 133 and 134 of the Lecture Notes, Part II, as a guide, sketch the band diagramof an MOS capacitor with an n-type Si substrate in i) accumulation, ii) at flat band condition, and iii) at theonset of strong inversion (that is, ψs = 2ψB). Assume an Al gate with electron affinity eφM = 3.0 eV, usefor Si the work-function eχ = 3.2 eV, and assume the n-type substrate to be doped with ND = 3 × 1017

donors/cm3.(b) What is the value of the flatband voltage VFB and of the threshold voltage VT0 (see Eq. (247) of theNotes, Part III)?(c) What is the value of the depletion capacitance CD at the onset of strong inversion?

Solution:(a) See the figures.(b): Looking at the first figure, the distance between the metal Fermi level and the vacuum level (the topmostdashed horizontal line) is given by:

|VFB| + eφM = |VFB| + 3.0 eV . (1)

Similarly, the distance between the Si Fermi level and the vacuum level will be given by:

eχ + Ei − ψB = 3.2 + 0.55 − 0.435 eV = 3.315 eV , (2)

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–150 –100 –50 0 50 100–2.0

–1.5

–1.0

–0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

eφM eχ

eψB

eVFB

EF,M EC

EV

Ei

EF,S

METAL INSULATOR SEMICONDUCTOR

FLAT BANDS

DISTANCE (nm)

ELE

CTR

ON

PO

TEN

TIA

L E

NE

RG

Y (

eV)

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eVG > 0

EF,M

EC

EV

Ei

EF,S

METAL INSULATOR SEMICONDUCTOR

ACCUMULATION

eVG < 0

EF,M

EC

EV

EiEF,S

METAL INSULATOR SEMICONDUCTOR

INVERSION

where ψB = kBT ln(ND/ni) is the distance between the Fermi level and the intrinsic level Ei. FromEqns. (1) and (2), noticing that VFB must be negative (since it raises the potential energy for electrons in thegate), we have VFB = - 0.315 V.

Finally, the threshold voltage is given by Eq. (247) of the Notes with γ = (2εSieND)1/2 (with ND replacingNA since we are dealing with an n-type substrate. Thus, using Cox = εox/tox and tox = 5 nm (fromProblem 2):

Cox =11.7 × 8.85 × 10−12F/m

5 × 10−9m= 6.9 × 10−3F/m2 . (3)

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To compute the body-factor γ let’s convert the doping density to m−3:

γ =(2 × 1.6 × 10−19 × 11.7 × 8.85 × 10−12 × 3 × 1023)1/2

6.9 × 10−4≈ 9.22 × 10−4

6.9 × 10−3= 0.134 V1/2

(4)Thus:

VT0 = VFB + 2ψB + γ (2ψB)1/2 ≈ −0.315 + 0.87 + 0.125 = 0.68 V (5)

(c) The depletion capacitance is given by:

CD =εSi

WD, (6)

where WD = [2εSiψs/(eND)]1/2 is the depletion width. The minimum capacitance is obtained when thedepletion width reaches its maximum value, for ψs = 2ψB. Using the value for ψB calculated above we have:

WD,max =

(4εSiψB

eND

)1/2

≈ 61.3 nm . (7)

So:

CD,min =11.7 × 8.85 × 10−12F/m

6.13 × 10−8m= 1.7 × 10−7 F/cm2 (8)

2. Problem:Assuming an oxide thickness tox of 5 nm and a gate area of 100 µm2, sketch the capacitance-voltage (C − V )characteristics of the MOS capacitor of problem 1, as in the figure at page 140 of the Lecture Notes. Recallthat this capacitor is on an n-type substrate!Solution:See the following figure:

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VFB

GATE VOLTAGE

GA

TE C

AP

AC

ITA

NC

Ehigh–frequency

lowfrequency

Cox Cox

Cmin

Note that we have already calculated Cox ≈ 6.9 × 10−3 F/m2 and CD ≈ 1.7 × 10−3 F/m2. Sincethe area of the capacitor is 100 µm2 = 10−6cm−2, we have Cox ≈ 0.69 pF, CD ≈ 0.17 pF, so that theminimum capacitance at high frequency in inversion will be Cmin = 1/(1/Cox + 1/CD) ≈ 0.14 pF.

3. Problem:Consider a Si nMOSFET with the following parameters:substrate doping (p-type): NA = 5 × 1016 cm−3

channel length L = 0.5 µmgate width W = 5 µmelectron mobility µn = 600 cm2/Vsoxide thickness tox = 15 nmflatband voltage VFB = 0.Using the simplified model of the Lecture Notes, pages 159-162, especially Eq. (255), plot as accurately as you

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can the ID − VD characteristics of the device assuming that the source contact is grounded (that is, VS=0).More specifically, plot ID-vs-VD for VG − VT0 = 0.0, 0.5, 1.0. 1.5, and 2.0 V for VD ranging from 0 to 5 V.Indicate as best as you can the separation between the linear and saturated region by computing VD,sat for thevarious values of VG − VT0. Also indicate the value of the threshold voltage VT0.Solution:The figure below shows the drain current as a function of drain bias in four curves (black, solid lines) parametrizedby the gate overdrive VG − VT0. Note that VT0 = 1.27 V and n = 1.32. The parabola indicated by a dashedblack line is given by the expression:

ID = µ CoxW

L

n

2V 2D , (9)

and it separates the linear (left) from the saturated region (right). When VD exceeds VD,sat – so, at the rightof the dashed parabola – Eq. (255) is not valid, as explained at page 160, immediately after Eq. (255), becausethe channel is pinched off. Many of you, especially those who have employed a computer to evaluate numericallythe current, have forgotten this fact and have used Eq. (255) also when VD > VD,sat, getting negative valuesfor the current. Not good...

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0.0 0.5 1.0 1.5 2.00

100

200

300

400

VG–VT0=2.0

1.5

1.0

0.5

VG–VT0=2.0

1.5

1.0

0.5

VT0 = 1.27 V

VD (V)

I D (

µA/m

)

4. Problem:As in problem 3 above, plot the same ID − VD characteristics, but now account for the degradation of theelectron mobility with increasing VG via Eq. (298) of the Lecture Notes. To do this, just replace µn in Eq. (255)with µeff given by Eq. (298). Use a value of K such that KCox/(2εs) = 0.5 V−1.Solution:The drain current is shown in the figure above by red dashed lines.

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5. Problem:Consider a Si nMOSFET with the following parameters:substrate doping (p-type): NA = 5 × 1016 cm−3

channel length L = 1.0 µmgate width W = 10 µmelectron mobility µn = 600 cm2/Vsoxide thickness tox = 4 nmthreshold voltage VT0 = 1 V.Using, as in the previous problem, the simplified model of the Lecture Notes, pages 159-162, especially Eq. (255),calculate the width of a similar pMOSFET giving the same saturated current for the same gate overdrive (thatis, at the same value of |VG − VT0|). Assume for the hole mobility a value of µp = 200 cm2/Vs. If you wish,you may assume also for the threshold voltage of the pMOSFET the value of -1 V. Recall that in dealing withthe pFET all polarities (VD and VG) are switched.Do you really need to know the entire set of parameters characterizing the devices in order to reach your answer?Solution:No, you don’t. Since the threshold voltage has the same magnitude (just of opposite polarity), the only reasonwhy the two currents (for the n and p FETs) differ at a given gate overdrive is due to the different mobilitiesfor the two devices. Since the hole mobility is three times smaller than the electron mobility, the p-channel FETmust be three times wider, that is W = 30 µm, in order to carry the same current.

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