High Frequency Behavioral Modeling of Second-Order ΣΔ Modulators

ByBy

George Suárez MartínezGeorge Suárez Martínez

Submitted in partial fulfillment of the requirements for the degree of

MASTERS OF SCIENCEin

Electrical Engineering

February 28, 2006

2

Presentation Outline

Motivation Objectives Second-order Multi-bit ΣΔ Modulator (ΣΔΜ) Non-idealities

Jitter Noise Thermal Noise Capacitance mismatch Individual Level Averaging (ILA) Switched-capacitor (SC) integrator

Results Conclusions

3

Motivation

ΣΔ modulators (ΣΔMs) form part of the core of many today’s mixed-signal designs as cornerstone components of oversampled ΣΔ data converters

ΣΔ converters have become a promising candidate for high-speed, high-resolution, and low-power mixed-signal interfaces

Transistor-level simulation is the most accurate approach (e.g. SPICE)

Impractical for complex systems, long simulation time… can take more than a day for a single case!

4

Motivation

Alternate modeling techniques, Finite-difference equations (z-transform) Macromodels Behavioral models

Accurate models are needed for low-power, high speed applications (e.g. GSM and WCDMA)

C,C++ and MATLAB are widely used for behavioral modeling

VHDL-Analog and Mixed Signal (VHDL-AMS) becomes practical, due mixed-signal nature of ΣΔM

5

Objectives

Develop an accurate behavioral model of a high-speed second-order multi-bit ΣΔΜ

Use VHDL-AMS as the modeling language

Develop modular and reusable models for other topologies of ΣΔΜs

Validate the model with SPICE simulations

Validate the model with experimental data for target bandwidths of GSM (200kHz) and WCDMA (2.0 MHz)

6

Quantization noise Lack of non-idealities

Jitter Noise Thermal Noise Capacitance mismatch Integrator Dynamics

Second-Order ΣΔΜ (Ideal Model)

0.5

0.5

+ +

First Integrator

1

1

+ +

Second Integrator

5-level quantizer

0.5

DAC

+

-

+

-

7

Non-uniform sampling.

For a sine wave the error can be approximated by,

Assumed to be white, Gaussian noise

Noise Sources - Jitter Noise

δ

Δv

8

Caused by the random motion of electrons due to thermal energy

For switched-capacitor ΣΔΜs thermal noise is due the integrator:

1. switches resistance

2.operational transconductance amplifier (OTA)

Based on track and hold operation of switched- capacitor (SC) systems

Noise Sources - Thermal Noise

9

Noise Sources - Thermal Noise

Sampling

Integration

10

Integrator gains are built using capacitor ratios

In multibit architectures DAC mismatch introduces harmonic distortion

Dynamic Element Matching (DEM) such as Individual Level Averaging (ILA) is employed

0.5

0.5

+ +

First Integrator

1

1

+ +

Second Integrator

quantizer

0.5

DAC

Capacitance Mismatch

11

Individual Level Averaging (ILA) Internal DAC unitary model

ILA algorithm transfer curves

“00” “01” “10”

0

0.5

1.0

din

vout

0.5

1.0

“00” “01” “10”

0

unit1

din

vout

“00” “01” “10”

0

0.5

1.0unit2

din

vout

Error duemismatch

din

unit2

unit1Thermometerdecoder

+vout

2

ideal

DAC

0

0.25

0.5

“00” “01” “00”

vout

“01” din

0

0.25

0.5

voutunit1 unit2

“00” “01” “00” “01” din

idealExample

ILA on

12

Integrator Dynamics

Fundamental block of ΣΔ Μodulators Dynamic behavior is the most limiting factor

vi

vr

va vo

vi

vr

va voOTA

Ci

Cr

Cint

CpCL

Cinxt

+

-

Φ1 Φ2

Φ1 Φ2

Φ2 Φ1

Φ2 Φ1

Φ1

Φ2

Φ1Φ2

OTA

Ci

Cr

Cint

CpCL

Cinxt

+

-

Φ1 Φ2

Φ1 Φ2

Φ2 Φ1

Φ2 Φ1

Φ1

Φ2

Φ1Φ2

vo

gm(va+-va

-) go Co

va+

va-

+Io

-Io

vo

gm(va+-va

-) go Co

va+

va-

+Io

-Io

Limited DC gainLimited bandwidthSlew rate limitationsParasitic capacitancesCapacitive Loads

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Possible cases in SC integrator transient response: Linear |va| # Io/gm

Partial Slew |va| > Io/gm and t $ to

Slew |va| > Io/gm and t < to

va , SR and to

determine the case

Integrator Dynamic Behavior

vo

gm(va+-va

-) go Co

va+

va-

+Io

-Ioto

va

time

Slew Linear

SR

OT

A in

put

volta

ge

14

eqo

iaioeqint

eq

eq

eqo

iaioeqintiaiiaf g

vIvt

C

g

g

vIvvv

,

,,

,

,,,,

sgn

γ1exp

sgn

γ1

o

moiai

t t

/gIv

&

,

Sle

w

, -1 , -1 ,1 (- ) (- ) 1p p i ri ro o n a n i r af i

int int int int

C C C CC Cv v v v v v

C C C C

SC integrator transient equations

A

vt

C

g

A

vvv eqint

eq

eqeqintiaiiaf

,,,, exp

moiai /g Iv ,

Lin

ear

A

vtt

C

g

A

v

g

Ivv eqint

oeq

eqeqint

m

oiaiiaf

,,,, expsgn

o

moiai

t t

/g I v

&

,

Par

tial

S

lew

1 i r pm

o int

C C CgA

g C

, 1 i r p

o eq m oint

C C Cg g g

C

15

end

Read

Calculate

Calculatepartial slew

Linear?

SC integrator Flowchart

start

Slew?

Calculateslew

Calculatelinear

Calculate

*Same flowchart for sampling and integration phases

No

No

Yes

Yes

16

Simulation Results - Model vs SPICE

Bandwidth SPICE SNDR Model SNDR Error (%)

135kHz 86.56 dB 85.43 dB 1.31

270kHz 74.65 dB 70.35 dB 5.76

615kHz 54.99 dB 51.42 dB 6.50

1. gm=1.16 mA/V and T=27oC.

Bandwidth SPICE SNDR New Model SNDR Error (%)

135kHz 86.10 dB 84.63 dB 1.71

270kHz 72.45 dB 70.30 dB 2.96

615kHz 53.62 dB 51.34 dB 4.25

2. gm=1.75 mA/V and T=27oC.

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Bandwidth SPICE SNDR New Model SNDR Error (%)

135kHz 89.90 dB 84.07 dB 6.48

270kHz 71.08 dB 71.04 dB 0.06

615kHz 53.53 dB 51.93 dB 2.99

3. gm=1.9 mA/V and T=-30oC.

Bandwidth SPICE SNDR New Model SNDR Error (%)

135kHz 87.57 dB 84.98 dB 2.95

270kHz 72.73 dB 70.54 dB 3.01

615kHz 53.37 dB 51.89 dB 2.78

4. gm=1. 9 mA/V and T=27oC.

Simulation Results - Model vs SPICE

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Simulation Results for GSM

VHDL-AMS 76.57 dBActual data 74.50 dB

2.78% error

19

Simulation Results for WCDMA

VHDL-AMS 76.57 dBActual data 74.50 dB

2.41% error

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Results-Capacitance Mismatch

0.0%

0.1%

1.0%

Individual Level Averaging off

DAC mismatch

73.15

57.80

38.00

SNDR (dB)

21

Results-Capacitance Mismatch

0.0%

0.1%

1.0%

Individual Level Averaging on

DAC mismatch

73.15

70.40

51.19

SNDR (dB)

22

Results-Thermal Noise

-30oC

27oC

100oC

Temperature

23

Results-Thermal Noise

4X

2X

1X

Capacitor sizes

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Results-Jitter Noise

0.4 % relative difference

Sampling deviation70.7128 dB

Derivative70.4322 dB

Jitter models

25

Results-Jitter Noise

0.0 ns

0.1ns1.0 ns

Input of 62 kHz

Jitter standard deviations

26

Results-Jitter Noise

0.0 ns

0.1ns1.0 ns

Jitter standard deviations

Input of 120 kHz

27

Comparison with Previous Models

Presented Model

Admittance Matrix

Traditional ModelLow power case

Smaller Io

Smaller DC gain Inclusion of go

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Speed*

Cycles Admittance Matrix Model VHDL-AMS Transient Model

8192 31 min 42 sec 15 sec

16384 1 hr 4 min 42 sec 30 sec

32768 2 hr 12 min 8 sec 1 min

65536 4 hr 13 min 5 sec 2 min 11 sec

A robust algorithmic-level time complexity analysis is difficult!

*Simulations were carried on a Pentium 4 PC with 2GB memory running at 3.0GHz.

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Conclusions

An accurate model of a second-order multi-bit ΣΔΜ was developed

Addresses several non-idealities such as: Jitter Noise

Thermal Noise

Capacitance Mismatch

Integrator dynamics

The integrator model an improved behavioral characterization of the degrading effects of settling errors on high-speed ΣΔΜs

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Conclusions

Results against SPICE simulations show errors less than 7%

Results for GSM (200kHz) show 2.78% of error

Results for WCDMA (2.0 MHz) show 2.41% of error in comparison with ≥ 15% for the previous model

Behavioral modeling and simulation with VHDL-AMS is a viable solution to the extensive transistor-level simulation of ΣΔΜs

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References1. J. C. Candy and G. C. Temes. “Oversampling Delta-Sigma Data Converters: Theory,

Design, and Simulation”. IEEE Press, 1992.2. Norsworthy, S. R. and Schreirer, R. and Temes, G. C. “Delta-Sigma Data Converters:

Theory Design and Simulation”. IEEE Press, 1997.3. G. Gomez and B. Haroun. “A 1.5 V 2.4/2.9 mW 79/50 dB DR SD modulator for GSM-

WCDMA in a 0.13 µm digital process”. ISSCC, pages 467–469, 2002.4. Medeiro, F. and Perez-Verdu, A. and Rodriguez-Vazquez, A. “Top-Down Design of High-

Performance Sigma-Delta Modulators”. Kluwer Academic Publishers, 1999.5. Sansen, W. Transient Analysis of Charge Transfer in SC Filters: Gain and Error

Distortion. IEEE Journal of Solid State Circuits, 22:268–276, 1987.6. F.O. Fernandez and M. Jimenez. “Behavioral Modeling of Dynamic Capacitive Loads on

Sigma-Delta Modulators”. Seminario Anual de Automatica Electronica Industrial e Instrumentacion, 1:119–122, 2002.

7. G. Suarez and M. Jimenez. “Behavioral Modeling of Sigma Delta Modulators using VHDL-AMS”. IEEE Midwest Symposium on Circuits and Systems, 2005.

8. G. Suarez, M. Jimenez and F. Fernandez. “Behavioral Modeling Methods for Switched-Capacitor ΣΔ Modulators”. Submitted to IEEE Transactions on Circuits and Systems Journal.

9. G. Suarez and M. Jimenez. “Considerations for Accurate Behavioral Modeling of High-Speed SC ΣΔ Modulators”. Submitted to IEEE International Symposium on Circuits and Systems.

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Acknowledgements

• Dr. Manuel Jiménez

• Dr. Rogelio Palomera

• Dr. Domingo Rodríguez

• Felix O. Fernández

• This work was partially supported by Texas Instruments through the TI-UPRM Program.

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Questions?