Hiroshi Iwai

Frontier Research Center

Tokyo Institute of Technology

Future of Nano-CMOS

Technology

March 20,2014,

DL Talk at Zhejiang University , Hangzhou, China

1

Back ground for nano-electronics

2

3

(1970) 10 μm 8 μm 6 μm 4 μm 3 μm 2 μm 1.2 μm

0.8 μm 0.5 μm 0.35 μm 0.25 μm 180 nm 130 nm

90 nm 65 nm 45 nm 32 nm (28 nm ) 22 nm(2012)

Feature Size / Technology Node

From 1970 to 2013 (Last year)

18 generations

Line width: 1/450

Area: 1/200,000

43 years 1 generation

2.5 years

Line width: 1/1.43 = 0.70

Area: 1/2 = 0.5

Nano-Electronics

In 1990’s, people expected completely new mechanism

or operational principle due the nano size, like quantum

mechanical effects.

However, no fancy new operational principle has not yet

been confirmed for logic application.

Thus, importance of Beyond CMOS technology is increasing

as CMOS approaches its downsizing limit now.

4

However, we have to stick to conventional Si Nano CMOS

technology until other one can replace it.

For the future conventional Si Nano CMOS, high-k, multi-

gate, Schottky SD technologies are important.

LDiffusive transport

LBallistic transport

~L

Quasi-Ballistic transport

L ：Mean free pathsource drain

Mobility

Theory

Real nanoscale

MOSFETs

Back scattering

from drain

Ballistic transport will never

happen for MOSFET because

of back scattering at drain

With decreasing channel length,

Drain current increase continue.

一次元バリスティック伝導

Also, 1D quantum conduction, or ballistic conduction will not happen.

Ballistic conduction will not happen

even decreasing channel lengh.

(1D quantum conduction: 77.8mS regardless of the length and material).5

6

Until a few years ago.

Technology developments for conventional

Si CMOS were done successfully.

People assume to reach the limit of gate

length very soon – that is 5 or 3 nm

Duration for generation shirked from 3 to 2

years.

7

Then, now!.

Noticed that the technology is difficult.

Reduction of the thickness of High-k gate

oxide becomes very difficult.

Development of EUV (Extreme Ultra Violet)

lithography delayed significantly.

Decreasing supply voltage becomes difficult

because of subtreshold leakage and

variability of thereshold voltage.

Now

8

Technology development delayed.

Number of the semiconductor companies which can develop

state of the art technology decreasing.

In the past, technologies come with the purchase of

equipment's

But now, every companies are facing threat of dropping off,

unless they concentrated on the development of

technologies.

Shrink rate of gate length will become from 07 to 0.8 or 0.85.

Thus, technology development is becoming much

important.

Importance of nano-CMOS

9

First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament

Today's pocket PCmade of semiconductor

has much higher performance with

extremely low power consumption

dreamed of replacing vacuum tube with solid-state device

10

1960: First MOSFET

by D. Kahng and M. Atalla

Top View

Al

SiO2

Si

Si/SiO2 Interface is extraordinarily good

11

1970,71: 1st generation of LSIs

DRAM Intel 1103 MPU Intel 4004

12

Most Recent SD Card

128GB (Bite)

= 128G X 8bit

= 1T(Tera)bit

1T = 1012 = １Trillion

Brain Cell：10～100 Billion

World Population：7 Billion

Stars in Galaxy：100 Billion

In 2012

13

2.4cm X 3.2cm X 0.21cm

Volume：1. 6cm³ Weight：2g

Voltage：2.7 - 3.6V

Old Vacuum Tube：5cm X 5cm X 10cm, 100g, 50W

128 GB = 1Tbit

What are volume, weight, power

consumption for 1Tbit

14

Old Vacuum Tube：5cm X 5cm X 10cm

1Tbit = 10,000 X 10,000 X 10,000 bit

Volume = (5cm X 10,000) X (5cm X 10,000)

X (10cm X 10,000)

= 0.5km X 0.5km X 1km

500 m

1,0

00 m

1Tbit

Burji Khalifa

Dubai, UAE

(Year 2010)

82

8 m

Indian Tower

Mumbai, India

(Year 2016)

70

0 m

70

0 m

Pingan Intenational

Finance Center

Shanghai, China

(Year 2016)

15

Old Vacuum Tube：50W

1Tbit = 1012bit

Power = 0.05kWX1012=50 TWNuclear Power Generator

1MkW=1BW We need 50,000 Nuclear Power Plant for

just one 128 GB memory

In Japan we have only 54

Nuclear Power Generator

Last summer Tokyo Electric

Power Company (TEPCO)

can supply only 55BW.

We need 1000 TEPCO just one

128 GB memory

Imagine how many memories

are used in the world! 16

So progress of integrated

circuits is extremely

important for power saving.

17

Brain: Integrated Circuits

Hands, Legs：Power device

Stomach：PV device

Ear, Eye：Sensor

Mouth：RF/Opto device

18

19

Near future smart-society has to treat huge

data.

Demand to high-performance and low power

CMOS become much more stronger.

20

Semiconductor Device Market will

grow 5 times in 12 years, even

though, it is very matured market!!

Gartner: By K. Kim, CSTIC 2012

300B USD

2011

1,500B USD

2025

2. Current status of Si-CMOS

device technologies

21

Downsizing

Thus, important for

Decreasing cost, power

Increasing performance22

Decreasing size

Decreasing capacitance

What is the problem problem for downsizing?

Question

23

The problem for downsizing

Ioff increase: Transistor cannot be turned-off.

Ioff (Off-leakage current) between S and D

24

1. Punch-through between S and D

2. Direct-tunneling between S and D

3. Subthreshold current between S and D

S and D distance small

Ion & Ioff increase

25

1. Punch-through between S and D

Gate oxide

Gate metal

Source Drain

1V0V0V

Substrate 0V Depletion

Region (DL)

by Drain Bias

1V

0V 0V

tox and Vdd have to be decreased for better channel

potential control IOFF Suppression

0V < Vdep＜1V

0V

0V < Vdep＜1V

Channel

0V

0V

0V0V

0.5V

Large IOFF

Region governed

By drain biasRegion governed

by gate bias

DL touch with S

Region (DL)

Large IOFF

No tox. Vdd

thinning

Vdd

Vdd

26

Problem for downsizing

(Electron current)

27

1. Punch-through between S and D

There are solutions to suppress the depletion layer

1.Decrease supply voltage Very difficult

2.Decrease tox to enhance the channel potential controllability by gate bias

as explained later

3. Gate/channel configuration change to enhance the channel potential controllability by gate bias

Fin-FET, ET-SOI, etc.

Lgate and tox(EOT) scaling trendA. Toriumi (Tokyo Univ), IEDM 2006, Short Course

t ox(

(

28

29

Configuration change for channel and gate structures for better control of channel potential.

Fin-FET, ET-SOI, etc.

1V0V

0V

S

0V

0V ＜V＜1V

1V0V

0V

0V

0VS D

G

G

G

Extremely Thin (or Fully-Depleted) SOI

Planar ET (or FD) SOI30

Si

SiO2

Extremely

thin Si

Drain bias

induced

depletion

- Make Si layer thin

- Control channel potential also from the bottom

1V0V

0V

S

0V

0V ＜V＜1V

1V0V

0V

0V

0VS D

G

G

G

Surrounding gate structure (Multiple gates)

PlanarMulti gate

31

Si fin or

nanowire

Drain bias

induced

depletion

- Make Si layer thin

- Control channel potential also by multiple gates

not only from top & bottom but maybe also

from side

Fin Tri-gate

(Variation)

W-gate All-around

G G G

G

G

Multi-gate structures

32

G

Tri-gate

Our work at TIT: W-gate Si NanowireS. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)

19 nm

12 nm

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

10-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urr

en

t (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

10-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urr

en

t (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

0 0.5 1 1.5 2ION (mA/mm)

Lg=65nm

0 0.5 1 1.5 2ION (mA/mm)

Lg=65nm

Lg=65nm

Poly-Si

SiO2

SiNSiN

SiO2

NW

・Conventional CMOS process

・High drive current

(1.32 mA/mm @ IOFF=117 nA/mm)

・DIBL of 62mV/V and SS of 70mV/dec

for nFET33

34

2. Direct-tunneling between S and D

Wave function of electron penetrates the channel potential barriers by quantum mechanical physics, when the channel length is around 3 nm.

Tunnelingdistance

3 nm

Source DrainChannel

35

Energ

y o

r P

ote

ntial

for

Ele

ctr

on

Direct-tunnelcurrent

There is no solutions!

Downsizing limit is @ Lg = 3 nm.

36

3. Subthreshold current between S and D

37

Vg

Id

Vth

(Threshold Voltage)

Vg=0V

Subthreshould

Leakage Current

Subtheshold leakage current of MOSFET

ONOFF

Ion

Subthreshold

region

38

Vg (V)1

0.3 V

0.5 V 1.0 V

Ion

Ioff

Id (A/mm)

10-7

10-5

10-11

10-9

Vd

Vth

0.15 V

0 0.5

Subthreshold leakage current

Electron Energy

Boltzmann statics

Exp (qV/kT)

Lg 1/2

Vd, Vg 1/2

Vth 1/2

Ioff 103 in this example

However

Because of

log-linear dependence

39

Vg

Id

Vth

(Threshold Voltage)

Vg=0V

Subthreshould

Leakage Current

Subtheshold leakage current of MOSFET

Subthreshold Current

Is OK at Single Tr. level

But not OK

For Billions of Trs.

ONOFF

Ion

Subthreshold

region

40

3. Subthreshold current between S and D

Solution: however very difficult

Keep Vth as high as possible

- Do not decrease supply voltage, Vd

- Suppress variability in Vth

However, punchthough enhanced

Thus, subthreshold current will limit the downsizing, especially for mobile devices

41Subthreshold Leakage (A/mm)

Op

era

tio

n F

req

ue

nc

y (

a.u

.)

e)

100

10

1

Source: 2007 ITRS Winter Public Conf.

The limit is deferent depending on application

How far can we go for production?

10mm 8mm 6mm 4mm 3mm 2mm 1.2mm 0.8mm 0.5mm

0.35mm 0.25mm 180nm 130nm 90nm 65nm 45nm 32nm

(28nm) 22nm 14nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?

Past 0.7 times per 2.5 years

Now Future

・At least 4,5 generations to 8 ~ 5 nm

42

Intermediate

node

Direct-tunnelSubthreshold

punchthrough

Limit depending

on applications

Fundamental

limit

However, careful about the name of technology!

22 nm Technology by Intel

Lg (Gate length) = 30 nm (HP), 34 nm (MP), 34 nm or larger (SP)

IEDM 2012, VLSI 2013

10 nm Technology by Leti (FD-SOI)

Lg (Gate length) = 25 nm Euro SOI 2014

Recently,

Gate length (Lg) is much larger than the Technology name

14 nm Technology by Global

Lg (Gate length) = 15 nm

The rate for the shrinkage for the gate length and

line pitch will be larger than 0.7 in near future,

because of the subthreshold leakage, and also

because of the delay in EUV lithography.

As a result, we will have more technology

generations until reaching the downsizing limit,

and the time to reach the limit will be delayed.

How far can we go for production?

45

Thus, we may go down to “2 nm”

technology by choosing whatever gate

length we want for the application.

46

Thank you very much

for your attention.