Franco Maloberti - IMSims.unipv.it/courses/download/aic/presentationno02.pdf · Analog Design for...
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2. Resistors, Capacitors, Switches
Analog Design for CMOS VLSI Systems
Franco Maloberti
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches1
Integrated resistorsA resistor is a strip of resistive layer.
n+ diff
p+ diff
n-well
p-well
pinched n-well
pinched p-well
poly 1
poly 2
Type of layer
Ω/
30-50
50-150
2K-4K
3K-6K
6K-10K
9K-13K
20-40
15-40
Sheetresistance
%
20-40
20-40
15-30
15-30
25-40
25-40
25-40
25-40
Accuracy
ppm/°C
200-1K
200-1K
5K
5K
10K
10K
500-1500
500-1500
Temperaturecoefficient
ppm/V
50-300
50-300
10K
10K
20K
20K
20-200
20-200
Voltagecoefficient
€
R = 2Rcont +L
WR
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches2
Types of resistances
a) diffused resistance
b) diffused resistance intowell
c) n-well (or p-well)resistance
d) pinched n-well(or p-well) resistance
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches3
e) first polysiliconresistance
f) first polysiliconresistance with a wellshielding
g) second polysiliconresistance
h) second polysiliconresistance with a wellshielding
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches4
In order to have large value resistors:
use of long strips (large L/W)
use of layers with high sheet resistance (badperformances)
Layout:
rectangular "serpentine".
€
R =L
WR =
LW
ρ xj
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches5
If the parameters are statistically independent, the standarddeviation of the resistance is:
€
ΔRR
2
=ΔLL
2
+ΔWW
2
+Δρ ρ
2
+Δxj
xj
2
is larger for polysilicon resistors than for diffused resistors(polysilicon is composed of a conglomerate of independentlyoriented grain of crystalline silicon)
Accuracy:
Absolute accuracy is poor because of the large parameterdrift.
Ratio (or matching) accuracy is better because it dependson the local variation of parameters.
€
ΔLL
<<
ΔWW
€
Δρ ρ
L >> W
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches6
Factors affecting accuracy
Polysilicon grainsize
Crystal defects Doping dose Stress Temperature
€
Δρ ρ
€
ΔLL
;
ΔWW
€
Δxj
xj
Implant dose
Side diffusivity
Deposition rate
Etching
Boundary
Side diffusivity
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches7
Stress:
Plastic packages cause a large pressure on the die (≈ 800atm). It determines a variation of the resistivity.
For <100> material the variation is anisotropic, so theminimum is with a 45° orientation.
Temperature:
Temperature gradient on the chip may produce thermalinduced mismatch.
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches8
Etching:
Wet etching: isotropic (undercut effect)
HF for SiO2 ; H3PO4 for Al
∆x for polysilicon may be 0.75-1 µm with standard deviation0.1 µm.
Reactive ion etching (R.I.E.)(plasma etching associated to"bombardment"): anisotropic.
∆x for polysilicon is 0.4 µm with standard deviation 0.03 µm
Boundary:
The etching depends on the boundary conditions
use of dummy strips
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches9
Side diffusion effect: Contribution of endings
Interdigitized structure
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches10
Resistor guidelines
For matching:
Use of equal structures
Not too narrow (W ≈ 10µm)
Interdigitize
Thermal effect compensation
45° orientation (if stressed)
For good TC:
Use of n+ or p+ layers
Use of poly layers
For absolute value:
Use of diffused layers
Suitable endings
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches11
Types of integrated capacitors
Electrodes: metal; polysilicon; diffusionInsulator: silicon oxide; polysilicon oxide; CVD oxide
€
C =ε0εr
tox
WL
€
ΔCC
2
=ΔLL
2
+ΔWW
2
+Δεr
εr
2
+Δtox
tox
2
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches12
Factors affecting accuracy
Oxide damage Impurities Bias condition Bias history (for
CVD) Stress Temperature
€
Δεr
εr
€
ΔLL
;
ΔWW
€
Δtox
tox
Grow rate Poly grain size
Etching Alignment
Absolute accuracy: Better than resistors. The capacitancevalue does not depend on doping and diffusion.
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches13
The layout of a capacitor depends on the layers usedto realize the two plates.
To achieve good matching: Use of unity capacitors connected in parallel. Use W = L fairly large.
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches14
Common centroid structures
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches15
Matching accuracy is better than matched resistors,because:
€
Δεr
εr
<<Δρ ρ
€
ΔWW
cap
<ΔWW
res
€
Δtox
tox
<Δxj
xj
Undercut effect:
W' = W - 2 ∆x L' = L - 2 ∆x
Effective area:
A' = W'L' = WL - 2(L + W) ∆x = A - P ∆x
The undercut effect gives the same proportional reduction ifthe perimeter-area ratio is kept constant.
(capacitors aresquare)
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches16
MOS capacitors features
Parasitic capacitances:
poly-diff
poly1-poly2
metal-poly
metal-diff
metal1-metal2
Type
nm
6-20
8-25
500-700
1200-1400
800-1200
tox
%
7-14
6-12
6-12
6-12
6-12
Accuracy
ppm/°C
20-50
20-50
50-100
50-100
50-100
Temperaturecoefficient
ppm/V
60-300
40-200
40-200
60-300
40-200
Voltagecoefficient
Cp,bCp,t
diffusion
0.1 C
0.01 C
poly-poly orpoly-metal
0.01 C
0.001 C
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches17
Analog switchesThe MOS transistor is a goodswitch if it is used to switchcharge (if used to switch currentgives an offset between inputand output).
The value of the ON-resistance depends on the overdrive voltage,Vov = VGS - VTh and on the aspect ratio, through the transconductanceparameter µCox.
Modern technologies (3.3 or 2;4 V), minimum area switch (W/L) = 1with 1V as overdrive displays: Ron,n ≈ 8.6 kΩ Ron,p ≈ 26.3 kΩ.
In the ON-state, after a transient Vout = Vin, hence VDS = 0. The MOSis in the linear region; its ON-resistance is:
€
Ron =1
gds
=1
µCox
WL
VGS −VTh( )
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches18
Example
Let us assume that the switch is driven by a 2 MHz clock, stays on for250 ns, and the load capacitor is 2 pF (rather large for integratedapplication). The resulting RC time constant is 17.2 ns for the n-typeand 52.6 ns and p-type transistor, equivalent to 14.5 and 4.75 timeconstants. Assuming an exponential response (neglecting anyoperation in the saturation region) the output voltage reaches0.9999995 and 0.991 of the final voltage respectively. The former resultis good enough for any analog applications, the latter one correspondsto an error of 1% witch is not acceptable for high precision.
Conclusion:
A minimum area n-channel switch is capable of driving 2 pF, runningat a few MHz clock.
A minimum area p-channel switch is capable of driving 2 pF with aclock control not exceeding 1 MHz.
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches19
The complementary switch transistor is the parallel of an n-channel and p-channel transistor.
Its ON-conductance is:
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches20
Clock feedthrough
In the ON-state
(VG – Vin) > VTh
The charge stored on the channel
Qch = W L Cox (VG – Vin – VTh)
at the time toff the charge Qch disappears.
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches21
The charge Qch injected partially on the source and partially on thedrain.
We can assume that a fraction a of the charge from the channelaffects the output node and is integrated on the store capacitor.Similarly, we analyze the charge injected from overlap capacitance.
When the channel is still existent, the low impedance node pulls partof the charge: we assume that a fraction β, remains in the storingcapacitor.
After toff, we have no interacting injections on the two sides.
The total charge that remains in the storing capacitor is:
€
Qinj = α WLeffCox VDD −Vin −VTh( )[ ] + βWxovCoxC1
WxovCox + C1
VDD −Vin −VTh( )
+
WxovCoxC1
WxovCox + C1
Vin +VTh( )
The charge, divided by the stored capacitor, gives the voltage errorproduced by clock feedthrough.
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches22
Clock feedthrough cancellation
Dummy switch Two complementary switch delayed driving Complementary switches Compensation scheme Fully differential structure Dummy switch:
(WL)1 = 2(WL)2
W1 = 2 W2
M2 must close after theopening of M1
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches23
Two switches:
If a switch with non-minimum area mustbe used
Complementaryswitches:
Effective only if Vin =constant (virtualground)
Analog Design for CMOS VLSI SystemsFranco Maloberti
2. Resistors, Capacitors, Switches24
Compensation scheme:
Fully differential structure:
The injected charge isequivalent to a commonmode signal (rejected by theCMRR).