Fibre Channel Transmitter and Receiver Fibre Channel Transmitter and Receiver Chipset Technical...
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Fibre Channel Transmitter andReceiver Chipset
HDMP-1512 TransmitterHDMP-1514 Receiver
Features ANSI X3.230-1994 Fibre
Channel StandardCompatible (FC-0)
Selectable 531.25 Mbaud or1062.5 Mbaud Data Rates
Selectable On Chip LaserDriver and 50 CableDriver
TTL Compatible I/Os Single +5.0 V Power Supply
Applications Mass Storage System I/O
Channel Work Station/Server I/O
Channel High Speed Peripheral
DescriptionThe HDMP-1512 transmitter andthe HDMP-1514 receiver arebipolar integrated circuits,separately packaged, in 80 pin M-Quad packages. They are used tobuild a high speed Fibre Channellink for point to point data com-munications. Shown in Figure 1 isa typical full duplex point-to-point Fibre Channel link. Thesending system provides parallel,8B/10B, encoded data and atransmit byte clock to the HDMP-1512 transmitter. Using the trans-mit byte clock, the transmitter
converts the data to a serialstream and sends it over a coppercable or fiber-optic link. Thereceiver converts the serial datastream back to parallel encodeddata and presents it, along withthe recovered transmit byteclock, to the receiving system.The sending system has theoption to electrically wrap thetransmitted data back to the localreceiver. It is possible to transmitover the cable driver, or laserdriver when data is beingwrapped back to the localreceiver.
The two-chip set (transmitterchip and receiver chip) iscompatible with the FC-0 layer ofthe American National StandardsInstitute (ANSI), Fibre Channelspecification, X3.230-1994. Thisspecification defines fourstandard rates of operation forFibre Channel links. The HDMP-1512 and HDMP-1514 chip-setwill operate at the two highestdefined serial rates of 531.25Mbaud and 1062.5 Mbaud. Theseserial baud rates correspond to8B/10B encoded byte rates of 50Mbytes/sec and 100 Mbytes/secrespectively. The proper settingof a single pin on each chipselects the desired rate ofoperation.
Several features, exclusive to thischip-set, make it ideal for use inFibre Channel links. In addition,the laser driver on the transmitterchip, the dual loss of lightdetectors on the receiver chip,and the power supervisor andpower reset features make thischip-set ideal for use with laseroptics. The serial cable driver(transmitter chip), and the cableequalizer (on the receiver chip),can be operated in conjunctionwith, or as an alternative to, thelaser driver. The laser driver canalso be driven directly with anexternal high speed serial input.
Altogether, the various features,input/output options, andflexibility of this chip-set makeseveral unique link configurationspossible. In particular, it is ideallysuited for use in applicationswhere conformance to the FCSIspecification # 301-Rev 1.0,Gbaud Link Module Specification,is desired.
Figure 2. HDMP-1512 (Tx) Block Diagram.
INPUT LATCHDATA BYTE 1Tx [10:19]
DATA BYTE 0Tx [00:09] FRAME
Transmitter OperationThe block diagram of the HDMP-1512 transmitter is shown inFigure 2. The basic functions ofthe transmitter chip are the TTLInterface and Input Latch, FrameMultiplexing, Input/Outputselection, cable drivers, LaserDriver, and monolithic PhaseLocked loop clock generator. Theactual operation of each functionchanges slightly, according to thedesired configuration and optionsettings. Figures 18 and 19 showschematically how to terminateeach pin on the HDMP-1512when used in systems incorporat-ing either copper or fiber media.
There are two main modes ofoperation for the transmitterchip, both are based on theselected baud rate. The baud rateis controlled by the appropriatesetting of the SPDSEL pin, #67.When this pin is set low, thetransmitter operates at a serialrate of 531.25 Mbaud. When pin#67 is set high the transmitteroperates at a serial rate of 1062.5Mbaud. As such, the two mainmodes of operation are the531.25 Mbaud mode and the1062.5 Mbaud mode.
The transmitter does not encodethe applied data. It assumes the
data is pre-encoded using the8B/10B encoding scheme asdefined in ANSI X3.230-1994.The TTL input interface receivesdata at the standard TTL levelsspecified in the dc ElectricalSpecification table. The internalphase locked loop (PLL) locks tothe transmit byte clock, TBC.TBC is supplied to the transmitterchip by the sending system. TBCshould be a 53.125 MHz clock( 100 ppm) as defined inX3.230-1994. Once the PLL haslocked to TBC, all the clocks usedby the transmitter are generatedby the internal clock generator.
Figure 1. Point-to-Point Data Link.
tions of 10 bit binary words, the8B/10B code reserves 256 ofthem to represent the validcombinations of 8 bit data. Someof the remaining combinationsare reserved for special functions.The character reserved fordefining the transmitted wordboundary has been defined as theK28.5 character, also known as acomma character. The receiverwill automatically reset registersand clock when it receives acomma character (this will bediscussed in more detail in thereceiver operation section). Everyvalid 8 bit data word is actuallyrepresented by one of two 10 bitcodes, indicating either positiveor negative running disparity. Theinput latch only generates theK28.5 character with positivedisparity (0011111010).
In Figure 2, the FrameMultiplexer utilizes shift registersand a multi-stage multiplexingscheme to convert the 10 or 20parallel data bits to a serial datastream. This serial data stream isthen fed directly into the Input/Output Select portion of thetransmitter.
The I/O Select function allows useof both the internally serializedFibre Channel data stream and an
externally supplied Fibre Channeldata stream denoted as SI (pins11 and 12). By using the propersettings of TS1, TS2, and EWRAP(pins 76, 75, and 71respectively), the internal datastream and the external datastream can be directed to variouscombinations of the cable driveroutput, the laser driver output,and the electrical loopbackoutput. The possible I/Ocombinations are listed in theInput Output Select Table and thefunctionality is described in moredetail in the Transmitter LaserDriver Operation section below.
The cable driver functionprovides a 50 differential cabledriver output at pins 5 and 6( SO). The simplified circuit isthe O-BLL section shown inFigure 10. A similar output isprovided to allow electricalloopback, or wrap of the localdata back to the local receiver fordiagnostics. This is denoted as LOUT on pin 8 and pin 9.
The final function on thetransmitter chip is the LaserDriver block which provides ahigh speed differential output, LZOUT, at pins 19 and 20.There are several other lasercontrol I/Os which will be
HDMP-1512 Input Output Select TableData Source For: Active Outputs
Mode TS1 TS2 EWRAP SO LZOUT LOUT SO LZOUT LOUT0 0 0 0 NA Internal NA no yes no1 0 0 1 NA NA Internal no no yes2 0 1 0 Internal Internal NA yes yes no3 0 1 1 Internal NA Internal yes no yes4 1 0 0 Internal NA NA yes no no5 1 0 1 NA Internal Internal no yes yes6 1 1 0 Internal SI NA yes yes no7 1 1 1 Internal NA SI yes no yes
When operating in the 531.25Mbaud mode, data byte 0,Tx[00:09], is active and isclocked into the input latch asingle byte (10 bits) on eachrising edge of TBC. In the 1062.5Mbaud mode both data byte 0,Tx[00:09], and data byte 1,Tx[10:19], are active. In 1062.5Mbaud mode, data byte 0 anddata byte 1 are clocked into thetransmitter on the rising edge ofevery clock cycle, (TBC). There isone minor variation possible inthe 1062.5 Mbaud mode, referredto as ping-pong mode. Ping-pong mode is selected by settingthe PPSEL pin (#34) high. In thismode the transmitter clocks datainto the input latch one byte perhalf clock cycle. Data byte 0 istransmitted on the rising edge ofTBC and data byte 1 is trans-mitted 1/2 clock cycle later. SeeFigure 16 for timing information.
The input latch will stop sendingthe data applied to the Tx[00:09]data pins when a low is applied tothe -COMGEN pin (#32) and willsend the pre-set special FibreChannel character, K28.5 instead.The 8B/10B coding scheme,adopted by Fibre Channel, con-verts 8 bit data words into 10 bitrepresentations of the actualdata. Of all the possible combina-
LZPWRON 36LASER ON
2715 28 22
0.1 F 0.1 F
0.1 F 301 2.2
P1 ( >= 100)
25 TRANSMISSION LINE
POT 1 5 K
Tx CHIP BOUNDARY
Figure 3. Laser Driver Block Diagram and External Circuitry.
described in more detail in thelaser driver operation sectionbelow.
Transmitter Laser DriverOperationThe block diagram of the H