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Page 1: FEA T UR ES - datasheet.elcodis.comdatasheet.elcodis.com/pdf2/85/80/858043/ssh10n80a.pdfMax imum Lea d T e mp . for S o ... SSH10N80A N- CHAN NEL POW ER M O SFET 2 EL ECTR IC AL CHARAC

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FEATURES

• Avalanche Rugged Technology

• Rugged Gate Oxide Technology

• Lower Input Capacitance

• Improved Gate Charge

• Extended Safe Operating Area

• Lower Leakage Current: 25µA (Max.) @ VDS = 800V

• Lower RDS(ON): 0.746Ω (Typ.)

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Symbol Characteristics Value Units

VDSS Drain-to-Source Voltage 800 V

IDContinuous Drain Current (TC = 25°C) 10

AContinuous Drain Current (TC = 100°C) 6.3

IDM Drain Current-Pulsed 40 A

VGS Gate-to-Source Voltage ±30 V

EAS Single Pulsed Avalanche Energy 533 mJ

IAR Avalanche Current 10 A

EAR Repetitive Avalanche Energy 28 mJ

dv/dt Peak Diode Recovery dv/dt 2.0 V/ns

PDTotal Power Dissipation (TC = 25°C)Linear Derating Factor

2802.22

WW/°C

TJ, TSTGOperating Junction and StorageTemperature Range

−55 to +150

°CTL

Maximum Lead Temp. for SolderingPurposes, 1/8” from case for 5-seconds

300

Symbol Characteristics Typ. Max. Units

RθJC Junction-to-Case − 0.45

°C/WRθCS Case-to-Sink 0.24 −

RθJA Junction-to-Ambient − 40

BVDSS = 800V

RDS(ON) = 0.95Ω

ID = 10A

TO-3P

1. Gate 2. Drain 3. Source

32

1

N-CHANNEL POWER MOSFET SSH10N80A

1999 Fairchild Semiconductor Corporation

REV. B

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SSH10N80A N-CHANNEL POWER MOSFET

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ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

Notes:① Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature② L=10mH, IAS=10A, VDD=50V, RG=27Ω, Starting TJ =25°C③ ISD ≤ 10A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ =25°C④ Pulse Test: Pulse Width ≤ 250µs, Duty Cycle ≤ 2%⑤ Essentially Independent of Operating Temperature

Symbol Characteristics Min. Typ. Max. Units Test Conditions

BVDSS Drain-Source Breakdown Voltage 800 − − V VGS=0V, ID=250µA

∆BV/∆TJ Breakdown Voltage Temp. Coeff. − 1.02 − V/°C ID=250µA, See Fig 7

VGS(th) Gate Threshold Voltage 2.0 − 3.5 V VDS=5V, ID=250µA

IGSSGate-Source Leakage, Forward − − 100

nAVGS=30V

Gate-Source Leakage, Reverse − − −100 VGS= −30V

IDSS Drain-to-Source Leakage Current− − 25

µAVDS=800V

− − 250 VDS=640V, TC=125°C

RDS(on)Static Drain-SourceOn-State Resistance

− − 0.95 Ω VGS=10V, ID=5A ④

gfs Forward Transconductance − 8.43 − S VDS=50V, ID=5A ④

Ciss Input Capacitance − 2700 3500

pFVGS=0V, VDS=25Vf=1MHzSee Fig 5

Coss Output Capacitance − 260 300

Crss Reverse Transfer Capacitance − 110 130

td(on) Turn-On Delay Time − 29 70

nsVDD=400V, ID=10ARG=9.6ΩSee Fig 13 ④ ⑤

tr Rise Time − 58 315

td(off) Turn-Off Delay Time − 152 235

tf Fall Time − 48 105

Qg Total Gate Charge − 125 165

nCVDS=640V, VGS=10VID=10ASee Fig 6 & Fig 12 ④ ⑤

Qgs Gate-Source Charge − 19.2 −

Qgd Gate-Drain (Miller) Charge − 45.4 −

Symbol Characteristics Min. Typ. Max. Units Test Conditions

IS Continuous Source Current − − 10A

Integral reverse pn-diodein the MOSFETISM Pulsed-Source Current ① − − 40

VSD Diode Forward Voltage ④ − − 1.4 V TJ=25°C, IS=10A, VGS=0V

trr Reverse Recovery Time − 620 − ns TJ=25°C, IF=10AdiF/dt=100A/µs ④Qrr Reverse Recovery Charge − 10.17 − µC

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10-1 100 10110-1

100

101

@ Notes : 1. 250 µs Pulse Test 2. TC = 25

oC

VGS

Top : 1 5 V 1 0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 VBottom : 4.5 V

I D , Drain Current [A]

VDS , Drain-Source Voltage [V]

2 4 6 8 1010-1

100

101

25 oC

150 oC

- 55 oC

@ Notes : 1. VGS = 0 V

2. VDS = 50 V

3. 250 µs Pulse Test

I D , Drain Current [A]

VGS , Gate-Source Voltage [V]

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.610-1

100

101

150 oC

25 oC

@ Notes : 1. VGS = 0 V

2. 250 µs Pulse TestI DR , Reverse Drain Current [A]

VSD , Source-Drain Voltage [V]0 10 20 30 40 50

0.0

0.5

1.0

1.5

2.0

@ Note : TJ = 25 oC

VGS = 20 V

VGS = 10 V

R DS(on) , [

Ω]

Drain-Source On-Resistance

ID , Drain Current [A]

100 1010

1000

2000

3000

4000Ciss= Cgs+ Cgd ( Cds= shorted )

Coss= Cds+ CgdCrss= Cgd

@ Notes : 1. VGS = 0 V

2. f = 1 MHzC rss

C oss

C iss

Capacitance [pF]

VDS , Drain-Source Voltage [V]0 20 40 60 80 100 120 1400

5

10

VDS = 640 V

VDS = 400 V

VDS = 160 V

@ Notes : ID = 10.0 AV GS , Gate-Source Voltage [V]

QG , Total Gate Charge [nC]

Fig 1. Output Characteristics Fig 2. Transfer Characteristics

Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage

Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current

N-CHANNEL POWER MOSFET SSH10N80A

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SSH10N80A N-CHANNEL POWER MOSFET

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-75 -50 -25 0 25 50 75 100 125 150 1750.8

0.9

1.0

1.1

1.2

@ Notes : 1. VGS = 0 V

2. ID = 250 µA

BVDSS , (Normalized)

Drain-Source Breakdown Voltage

TJ , Junction Temperature [oC]

-75 -50 -25 0 25 50 75 100 125 150 1750.0

0.5

1.0

1.5

2.0

2.5

3.0

@ Notes : 1. VGS = 10 V

2. ID = 5.0 A

R DS(on) , (Normalized)

Drain-Source On-Resistance

TJ , Junction Temperature [oC]

25 50 75 100 125 1500

3

6

9

12

I D , Drain Current [A]

Tc , Case Temperature [oC]

101 102 10310-1

100

101

102

100 µs

DC

10 µs

1 ms

10 ms

@ Notes : 1. TC = 25

oC

2. TJ = 150 oC

3. Single Pulse

Operation in This Area is Limited by R DS(on)

I D , Drain Current [A]

VDS , Drain-Source Voltage [V]

10-5 10-4 10-3 10-2 10-1 100 101

10-2

10-1

100

single pulse

0.2

0.1

0.01

0.02

0.05

D=0.5

@ Notes : 1. ZθJC(t)=0.45

oC/W Max.

2. Duty Factor, D=t1/t2 3. TJM-TC=PDM*ZθJC(t)

Z θJC(t) , Thermal Response

t1 , Square Wave Pulse Duration [sec]

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

Fig 11. Thermal Response

Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area

PDM

t1

t2

PDM

t1

t2

t1

t2

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Fig 12. Gate Charge Test Circuit & Waveform

Fig 13. Resistive Switching Test Circuit & Waveforms

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

EAS = LL IAS2----

21 --------------------

BVDSS -- VDD

BVDSSEAS = LL IAS

2----21

EAS = LL IAS2----

21----21 --------------------

BVDSS -- VDD

BVDSS

V in

Vout

10%

90%

td(on) tr

t on t off

td(off) tf

V in

Vout

10%

90%

td(on) tr

t on t off

td(off) tf

Charge

VGS

10V

Qg

Qgs Qgd

Charge

VGS

10V

Qg

Qgs Qgd

Vary tp to obtainrequired peak ID

10V

VDDC

LL

VDS

ID

RG

t p

DUT

Vary tp to obtainrequired peak ID

10V

VDDC

LL

VDS

ID

RG

t p

DUT

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

VDD

( 0.5 rated VDS )

10V

Vout

Vin

RL

DUT

RG

VDD

( 0.5 rated VDS )

10V

Vout

Vin

RL

DUT

RG

3mA

VGS

Current Sampling (IG)Resistor

Current Sampling (ID)Resistor

DUT

VDS

300nF

50K

200nF12V

Same Typeas DUT

Current Regulator

R1 R2

3mA

VGS

Current Sampling (IG)Resistor

Current Sampling (ID)Resistor

DUT

VDS

300nF

50K

200nF12V

Same Typeas DUT

Current Regulator

R1 R2

N-CHANNEL POWER MOSFET SSH10N80A

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SSH10N80A N-CHANNEL POWER MOSFET

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Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

VDS

+

--

LI S

DriverVGS

RGSame Type

as DUT

VGS • dv/dt controlled by G

• IS controlled by Duty Factor ?

VDD

DUT

VDS

+

--

LI S

DriverVGS

RGSame Type

as DUT

VGS • dv/dt controlled by G

• IS controlled by Duty Factor ?

VDD

10VVGS

( Driver )

I S

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

V f

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D =Gate Pulse Width

Gate Pulse Period--------------------------

10VVGS

( Driver )

I S

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

V f

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D =Gate Pulse Width

Gate Pulse Period--------------------------D =Gate Pulse Width

Gate Pulse Period--------------------------

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Dimensions in Millimeters

August 1999, Rev B

TO-3P Package Dimensions

15.60 ±0.20

4.80 ±0.2013.60 ±0.20

9.60 ±0.20

2.00 ±0.20

3.00 ±0.20

1.00 ±0.20 1.40 ±0.20

ø3.20 ±0.10

3.80

±0.

20

13.9

0 ±0

.20

3.50

±0.

20

16.5

0 ±0

.30

12.7

6 ±0

.20

19.9

0 ±0

.20

23.4

0 ±0

.20

18.7

0 ±0

.20

1.50+0.15–0.05

0.60+0.15–0.05

5.45TYP[5.45 ±0.30]

5.45TYP[5.45 ±0.30]

TO-3P (FS PKG CODE AF)

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TRADEMARKS

ACEx™CoolFET™CROSSVOLT™E2CMOSTM

FACT™FACT Quiet Series™FAST®

FASTr™GTO™HiSeC™

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to theuser.

2. A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.

This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.

This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.

This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.

Formative orIn Design

First Production

Full Production

Not In Production

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHERNOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILDDOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.

TinyLogic™UHC™VCX™

ISOPLANAR™MICROWIRE™POP™PowerTrench™QFET™QS™Quiet Series™SuperSOT™-3SuperSOT™-6SuperSOT™-8

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