EVALUATION KIT Low RF Susceptibility, Mono Audio … · 2010-06-10 · ♦ Low RF Susceptibility...

General DescriptionThe MAX9875 combines a high-efficiency Class Daudio power amplifier with a stereo Class AB capacitor-less DirectDrive® headphone amplifier. Maxim’s 3rdgeneration, filterless Class D amplifier with active emis-sions limiting technology provides Class AB perfor-mance with Class D efficiency.

The MAX9875 delivers up to 725mW from a 3.7V supplyinto an 8Ω load with 87% efficiency to extend battery life.The filterless modulation scheme combined with activeemissions limiting circuitry and spread-spectrum modu-lation greatly reduces EMI while eliminating the need foroutput filtering used in traditional Class D devices.

The stereo Class AB headphone amplifier in theMAX9875 uses Maxim’s DirectDrive architecture, thatproduces a ground-referenced output from a single sup-ply, eliminating the need for large DC-blocking capaci-tors, saving cost, space, and component height.

The device utilizes a user-defined input architecture,three preamplifier gain settings, an input mixer, volumecontrol, comprehensive click-and-pop suppression, andI2C control.

The MAX9875 is available in a thermally efficient,space-saving 20-bump WLP package.

ApplicationsCell Phones

Portable Multimedia Players

Features♦ Low Emissions, Filterless Class D Amplifier

Achieves Better than 10dB Margin Under EN55022Class B Limits

♦ Low RF Susceptibility Design Rejects TDMANoise from GSM Radios

♦ Input Mixer with User-Defined Input Mode♦ 725mW Speaker Output (RSPK = 8Ω, PVDD = 3.7V)♦ 53mW Headphone Output (RHP = 16Ω, VDD = 3.7V)♦ Low 0.05% THD+N at 1kHz (Class D Power

Amplifier)♦ Low 0.016% THD+N at 1kHz (Headphone

Amplifier)♦ 87% Efficiency (RSPK = 8Ω, POUT = 750mW)♦ High Speaker Amplifier PSRR (72dB at 217Hz)♦ High Headphone Amplifier PSRR (84dB at 217Hz)♦ I2C Control♦ Hardware and Software Shutdown Mode♦ Click-and-Pop Suppression♦ Current-Limit and Thermal Protection♦ Available in a Space-Saving, 2.5mm x 2.0mm WLP

Package

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Low RF Susceptibility, Mono AudioSubsystem with DirectDrive Headphone Amplifier

________________________________________________________________ Maxim Integrated Products 1

MIXER/MUX

PREAMPLIFIER

SINGLE SUPPLY2.7V TO 5.25V

I2CINTERFACE

VOLUMECONTROL

VOLUMECONTROL

MAX9875

Simplified Block Diagram

WLP

HPL VSS C1NHPR

1

A

B

C

D

2 3 4

C1P

BIAS SDA N.C.VDD OUT+

INB1 SCL PGNDINB2 PVDD

INA1 GND N.C.INA2 OUT-

5

TOP VIEW(BUMP SIDE DOWN)

Pin Configuration

19-4536; Rev 0; 3/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering InformationPART TEMP RANGE PIN - PA C K A G E

MAX9875ERP+TG45 -40°C to +85°C 20 WLP (5x4)

+Denotes a lead(Pb)-free/RoHS-compliant package.T = Tape and reel.G45 indicates protective die coating.DirectDrive is a registered trademark of Maxim Integrated

Products, Inc.

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ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(VDD = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, SHDN = 1.Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA andSCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values areat TA = +25°C.) (Note 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

Note 1: HPR and HPL should be limited to no more than 9V above VSS, or above PVDD + 0.3V, whichever limits first.Note 2: HPR and HPL should be limited to no more than 9V below PVDD, or below VSS - 0.3V, whichever limits first.

VDD, PVDD to PGND .............................................-0.3V to +5.5VVDD to PVDD .........................................................-0.3V to +0.3VVSS to PGND .........................................................-5.5V to +0.3VC1N to PGND..............................................(VSS - 0.3V) to +0.3VC1P to PGND...........................................-0.3V to (PVDD + 0.3V)HPL, HPR to VSS

(Note 1)......-0.3V to the lower of (PVDD - (VSS + 0.3V)) or +9VHPL, HPR to PVDD

(Note 2) .....+0.3V to the higher of (VSS - (PVDD - 0.3V)) or -9VGND to PGND.....................................................................±0.3VINA1, INA2, INB1, INB2, BIAS..................................-0.3V to +4VSDA, SCL...............................................................-0.3V to +5.5VAll Other Pins to GND..............................-0.3V to (PVDD + 0.3V)Continuous Current In/Out of PVDD, PGND, OUT_........±800mA

Continuous Current In/Out of HPR and HPL.....................140mAContinuous Input Current VSS...........................................100mAContinuous Input Current (all other pins) .........................±20mADuration of OUT_ Short Circuit to GND or PVDD.......ContinuousDuration of Short Circuit Between OUT+ and OUT- ..ContinuousDuration of HP_ Short Circuit to GND or PVDD..........ContinuousContinuous Power Dissipation (TA = +70°C)

20-Bump WLP, 5 x 4, Multilayer Board (derate 13.0mW/°C above +70°C)..................................1.04W

Junction Temperature ......................................................+150°COperating Temperature Range ...........................-40°C to +85°CStorage Temperature Range .............................-65°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage Range VDD, PVDD Guaranteed by PSRR test 2.7 5.25 V

OSC = 00 5.6 9.0HP mode,OUTMODE = 2 OSC = 10 5.5

OSC = 00 6.6 11.0SPK mode,OUTMODE = 7 OSC = 10 5.7

OSC = 00 10.4 16.0

Quiescent Current IDD

SPK + HP mode,OUTMODE = 9 OSC = 10 9.3

mA

Shutdown Current ISHDNISHDN = IVDD + IPVDD; SHDN = 0; VSDA =VSCL = logic-high; TA = +25°C

10 22 µA

OSC = 00 10

OSC = 01 10Turn-On Time tONTime from shutdown tofull operation

OSC = 10 17.5

ms

BIAS Release Time tBRAfter forcing BIAS low, time from BIASreleased to I2C reset

25 80 ms

TA = +25°C, preamp gain = 0dB or +9dB 11 21 31Input Resistance RIN

TA = +25°C, preamp gain = +20dB 3 5.5 8kΩ

Preamp = 0dB 2.30

Preamp = +9dB 0.820Maximum Input Signal Swing

Preamp = +20dB 0.230

VP-P

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Preamp = 0dB 47

Preamp = +9dB 49Common-Mode Rejection Ratio CMRRfIN = 1kHz (differentialinput mode)

Preamp = +20dB 42

dB

Input DC Voltage IN__ inputs 1.22 1.3 1.38 V

Bias Voltage VBIAS 1.13 1.2 1.27 V

SPEAKER AMPLIFIER (OUTMODE = 1)

TA = +25°C (volume at mute) ±0.5 ±4

Output Offset Voltage VOS TA = +25°C (volume at 0dB,OUTMODE = 1, ∆IN_ = 0)

±1.5mV

Into shutdown -70Click-and-Pop Level KCP

Peak voltage, TA =+25°C, A-weighted, 32samples per second,volume at mute (Note 4) Out of shutdown -70

dBV

PVDD = VDD =2.7V to 5.5V

50 76

f = 217Hz,100mVP-P ripple

72

f = 1kHz,100mVP-P ripple

68

Power-Supply Rejection Ratio(Note 4)

PSRRTA = +25°C, PVDD =VDD

f = 20kHz,100mVP-P ripple

55

dB

ZSPK = 8Ω +68µH, VDD = 3.7V

725


560


465


825

Output Power (Note 5) POUT THD+N ≤ 1%


770

mW

Total Harmonic Distortion PlusNoise

THD+Nf = 1kHz, POUT = 350mW, TA = +25°C,ZSPK = 8Ω + 68µH

0.05 %

∆IN_ = 0(single-ended)

92A-weighted,OUTMODE = 1, 3,4, 6 ∆IN_ = 1 (differential) 94


88

Signal-to-Noise Ratio SNR

A-weighted,OUTMODE = 7, 9

∆IN_ = 1 (differential) 92

dB

ELECTRICAL CHARACTERISTICS (continued)(VDD = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, SHDN = 1.Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA andSCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values areat TA = +25°C.) (Note 3)

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Spread-spectrum modulation mode,OSC = 00

1176±60

Fixed-frequency mode, OSC = 01 1100Output Frequency

Fixed-frequency mode, OSC = 10 700

kHz

Current Limit 1.5 A

Efficiency η POUT = 600mW, f = 1kHz 87 %

Speaker Gain AV 11.5 12.0 12.5 dB

Output NoiseA-weighted, OUTMODE = 1, ∆IN_ = 0(Note 4)

63 µVRMS

HEADPHONE AMPLIFIERS (OUTMODE = 2)

TA = +25°C (volume at mute) ±0.15 ±0.6Output Offset Voltage VOS

TA = +25°C (volume at 0dB) ±1.6mV

Into shutdown -80

Click-and-Pop Level KCP

Peak voltage, TA =+25°C, A-weighted,32 samples persecond. volume atmute (Note 4)

Out of shutdown -80

dBV

PVDD = VDD = 2.7Vto 5.25V

70 85

f = 217Hz,VRIPPLE = 100mVP-P

84

f = 1kHz,VRIPPLE = 100mVP-P

80

Power-Supply Rejection Ratio(Note 4)

PSRRTA = +25°C, PVDD =VDD

f = 20kHz,VRIPPLE = 100mVP-P

62

dB

RHP = 16Ω 53Output Power POUT THD+N ≤ 1%

RHP = 32Ω 27mW

Headphone Gain AV -0.4 0 +0.4 dB

Channel-to-Channel GainTracking

TA = +25°C, HPL to HPR, volume at 0dB,OUTMODE = 2, 5; ∆IN_ = 0

±0.3 ±2.5 %

RHP = 32Ω (POUT = 10mW, f = 1kHz) 0.016Total Harmonic Distortion PlusNoise

THD+N RHP = 16Ω (POUT = 10mW, f = 1kHz),TA = +25°C

0.03%


98A-weighted,OUTMODE = 2, 3,5, 6; RHP = 16Ω ∆IN_ = 1 (differential) 98


96

Signal-to-Noise Ratio SNRA-weighted, RHP =16Ω, OUTMODE =8, 9 ∆IN_ = 1 (differential) 96

dB

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Slew Rate SR 0.35 V/µs

Capacitive Drive CL 100 pF

Crosstalk HPL to HPR, HPR to HPL, f = 20Hz to 20kHz 65 dB

Spread-spectrum modulation mode,OSC = 00

588±30

Fixed-frequency mode, OSC = 01 430 550 670Charge-Pump Frequency

Fixed-frequency mode, OSC = 10 220 350 500

kHz

VOLUME CONTROL

Minimum Setting _VOL = 1 -75 dB

Maximum Setting _VOL = 31 0 dB

PGAIN_ = 00 0

PGAIN_ = 01 9Preamp Gain Input A or B

PGAIN_ = 10 20

dB

Speaker 100Mute Attenuation f = 1kHz, _VOL = 0

Headphone 110dB

Zero-Crossing Detection Timeout ZCD = 1 60 ms

DIGITAL INPUTS

Input-Voltage High (SDA, SCL) VH 1.4 V

Input-Voltage Low (SDA, SCL) VL 0.4 V

Input-Voltage Low (BIAS) VBL 0.15 V

Input Hysteresis (SDA, SCL) VHYS 80 mV

SDA, SCL Input Capacitance CIN 4 pF

Input Leakage Current IIN SDA, SCL; TA = +25°C ±1.0 µA

BIAS Pullup Current IBIAS 94 µA

DIGITAL OUTPUTS (SDA Open Drain)

Output Low Voltage SDA VOL ISINK = 3mA 0.4 V

Output Fall Time SDA tOFVH(MIN) to VL(MAX) bus capacitance = 10pFto 400pF, ISINK = 3mA

250 ns

2-WIRE INTERFACE TIMING

External Pullup Voltage Range:SDA and SCL

1.7 3.6 V

Serial Clock Frequency fSCL DC 400 kHz

Bus Free Time Between STOPand START Conditions

tBUF 1.3 µs

START Condition Hold tHD:STA 0.6 µs

START Condition Setup Time tSU:STA 0.6 µs

Clock Low Period tLOW 1.3 µs

Clock High Period tHIGH 0.6 µs

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Data Setup Time tSU:DAT 100 ns

Data Hold Time tHD:DAT 0 900 ns

Maximum Receive SCL/SDA RiseTime

tR 300 ns

Maximum Receive SCL/SDA FallTime

tF 300 ns

Setup Time for STOP Condition tSU:STO 0.6 µs

Capacitive Load for Each BusLine

Cb 400 pF

Note 3: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design.Note 4: Amplifier inputs are AC-coupled to GND.Note 5: Output levels higher than 825mW are not recommended for extended durations. Production tested with ZSPK = 8Ω + 68µH only.

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SUPPLY CURRENT vs. SUPPLY VOLTAGE

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1

SUPPLY VOLTAGE (V)

SUPP

LY C

URRE

NT (m

A)

5.04.54.03.53.0

5

6

7

8

9

42.5 5.5

HEADPHONE ONLYINPUTS AC-COUPLED TO GNDOUTMODE = 8VSDA = VSCL = 3.3V

fOSC = 1176kHz SREAD-SPECTRUM MODE

fOSC = 1100kHz

fOSC = 700kHz


MAX

9875

toc0

2SUPPLY VOLTAGE (V)

SUPP

LY C

URRE

NT (m

A)

5.04.54.03.53.0

6

5

7

8

9

10

42.5 5.5

SPEAKER ONLYINPUTS AC-COUPLED TO GNDOUTMODE = 7VSDA = VSCL = 3.3V

fOSC = 1176kHz SPREAD-SPECTRUM MODE

fOSC = 1100kHzfOSC = 700kHz


MAX

9875

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3

SUPPLY VOLTAGE (V)

SUPP

LY C

URRE

NT (m

A)

5.04.54.03.53.0

10

9

8

11

12

13

72.5 5.5

fOSC = 1176kHz SPREAD-SPECTRUM MODE

fOSC = 1100kHz

fOSC = 700kHz

HEADPHONE AND SPEAKERINPUTS AC-COUPLED TO GNDOUTMODE = 9VSDA = VSCL = 3.3V

SHUTDOWN CURRENT vs. SUPPLY VOLTAGE

MAX

9875

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4

SUPPLY VOLTAGE (V)

SHUT

DOW

N CU

RREN

T (µ

A)

5.04.54.03.53.0

10

9

8

11

12

13

14

72.5 5.5

INPUTS AC-COUPLED TO GNDVSDA = VSCL = 3.3V

VOLUME ATTENUATION vs. _VOL CONTROL CODE

MAX

9875

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5

_VOL CONTROL CODE

VOLU

ME

ATTE

NUAT

ION

(dB)

515 10202530

-60

-80

-100

-40

-20

0

20

-12035 0

fIN = 1kHzMEASURED AT HPLAND HPR

Typical Operating Characteristics(VDD = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, SHDN = 1.Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK =∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.)

GENERAL

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TOTAL HARMONIC DISTORTION PLUSNOISE vs. FREQUENCY

MAX

9875

toc1

0

FREQUENCY (Hz)

THD+

N (%

)

10k1k100

1

0.1

0.0110 100k

VDD = VPVDD = 3.7VPOUT = 200mWZSPK = 8Ω + 68µH

fOSC = 700kHz

fOSC = 1176kHz

fOSC = 1100kHz

TOTAL HARMONIC DISTORTION PLUSNOISE vs. OUTPUT POWER

MAX

9875

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1

OUTPUT POWER (W)

THD+

N (%

)

1.51.00.5

0.1

1

10

0.010 2.0

fIN = 20Hz

fIN = 1kHz

fIN = 6kHz

VDD = VPVDD = 5VZSPK = 8Ω + 68µH


MAX

9875

toc1

2

OUTPUT POWER (W)

THD+

N (%

)

1.5

0.1

1

10

0.010 2.51.0 3.00.5 2.0

VDD = VPVDD = 5VZSPK = 4Ω + 33µHDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS

fIN = 6kHzfIN = 20Hz

fIN = 1kHz


MAX

9875

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3

OUTPUT POWER (mW)

THD+

N (%

)

0.1

1

10

0.010 1000600400 800200

fIN = 6kHz

fIN = 20Hz

fIN = 1kHz

VDD = VPVDD = 3.7VZSPK = 8Ω + 68µH

Typical Operating Characteristics (continued)(VDD = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, SHDN = 1.Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK =∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.)

SPEAKER AMPLIFIER


MAX

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6

FREQUENCY (Hz)

THD+

N (%

)

10k1k100

0.1

1

10

0.0110 100k

VDD = VPVDD = 3.7VZSPK = 8Ω + 68µH

POUT = 200mW

POUT = 675mW


MAX

9875

toc0

7

FREQUENCY (Hz)

THD+

N (%

)

10k1k100

0.1

1

10

0.0110 100k

VDD = VPVDD = 3.7VZSPK = 4Ω + 33µHDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS

POUT = 1100mW

POUT = 650mW


MAX

9875

toc0

8

FREQUENCY (Hz)

THD+

N (%

)

10k1k100

0.1

1

10

0.0110 100k

POUT = 425mW

POUT = 200mW



MAX

9875

toc0

9

FREQUENCY (Hz)

THD+

N (%

)

10k1k100

0.1

1

10

0.0110 100k

POUT = 700mW

POUT = 250mW


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EFFICIENCY vs. OUTPUT POWER

MAX

9875

toc1

9

OUTPUT POWER (W)

EFFI

CIEN

CY (%

)

1.5

100

0

50

60

10

80

30

70

20

90

40

0 3.00.5 2.01.0 2.5

VDD = VPVDD = 5VfIN = 1kHzDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS

ZSPK = 8Ω + 68µHZSPK = 4Ω + 33µH


MAX

9875

toc2

0

OUTPUT POWER (W)

EFFI

CIEN

CY (%

)

100

0

50

60

10

80

30

70

20

90

40

0 2.01.51.00.5

VDD = VPVDD = 3.7VfIN = 1kHzDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS

ZSPK = 8Ω + 68µH ZSPK = 4Ω + 33µH


MAX

9875

toc2

1

OUTPUT POWER (mW)

EFFI

CIEN

CY (%

)

100

0

50

60

10

80

30

70

20

90

40

0 1000600200 800400

VDD = VPVDD = 3.7VfIN = 1kHzZSPK = 8Ω + 68µH

fOSC = 700kHz

fOSC = 1176kHz AND 1100kHz



_______________________________________________________________________________________ 9


MAX

9875

toc1

4

OUTPUT POWER (W)

THD+

N (%

)

0.1

1

10

0.010 1.51.00.5

VDD = VPVDD = 3.7VZSPK = 4Ω + 33µHDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS


fIN = 1kHz


MAX

9875

toc1

5

OUTPUT POWER (mW)

THD+

N (%

)

0.1

1

10

0.010 600400200

fIN = 6kHz

fIN = 20Hz

fIN = 1kHz



MAX

9875

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6

OUTPUT POWER (W)

THD+

N (%

)

0.1

1

10

0.010 1.20.80.4 1.00.60.2

VDD = VPVDD = 3VZSPK = 4Ω + 33µHDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS


fIN = 1kHz


MAX

9875

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7

OUTPUT POWER (mW)

THD+

N (%

)

600400200

1

0.01

0.1

0 800


fOSC = 1176kHz SSM

fOSC = 700kHz

fOSC = 1100kHz


MAX

9875

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8

OUTPUT POWER (mW)

THD+

N (%

)

600400200

1

0.01

0.1

0 800


fOSC = 1176kHz SSM

fOSC = 700kHz

fOSC = 1100kHz

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IN-BAND OUTPUT SPECTRUM

MAX

9875

toc2

8

FREQUENCY (kHz)

AMPL

ITUD

E (d

BV)

15105

0

-140

-80

-40

-120

-20

-60

-100

0 20

fOSC = 1100kHzfIN = 1kHz


MAX

9875

toc2

9

FREQUENCY (kHz)

AMPL

ITUD

E (d

BV)

15105

0

-140

-80

-40

-120

-20

-60

-100

0 20



MAX

9875

toc2

2

OUTPUT POWER (mW)

EFFI

CIEN

CY (%

)

100

0

50

60

10

80

30

70

20

90

40

0 1000600400 800200

VDD = VPVDD = 3VfIN = 1kHzDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS

ZSPK = 8Ω + 68µH ZSPK = 4Ω + 33µH

OUTPUT POWER vs. SUPPLY VOLTAGE

MAX

9875

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3

SUPPLY VOLTAGE (V)

OUTP

UT P

OWER

(W)

5.04.54.03.53.0

2.0

2.5

0.5

1.0

1.5

3.0

3.5

02.5 5.5

10% THD+N

1% THD+N

VDD = VPVDDZSPK = 4Ω + 33µHDASHED LINES ARE LIMITEDBY THE ABS. MAX RATINGS


MAX

9875

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4

SUPPLY VOLTAGE (V)

OUTP

UT P

OWER

(W)

5.04.54.03.53.0

2.0

0.2

0.8

0.6

1.2

1.0

1.6

0.4

1.8

1.4

02.5 5.5

VDD = VPVDDZSPK = 8Ω + 68µH

10% THD+N

1% THD+N

OUTPUT POWER vs. LOAD RESISTANCE

MAX

9875

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5

LOAD RESISTANCE (Ω)

OUTP

UT P

OWER

(W)

1.8

0.2

0.8

0.6

1.2

1.0

1.6

0.4

1.4

00 100704010 805020 906030

VDD = VPVDD = 3.7VfIN = 1kHzZSPK = LOAD + 68µH

10% THD+N

1% THD+N


MAX

9875

toc2

6


OUTP

UT P

OWER

(W)

1.2

0.2

0.8

0.6

1.0

0.4

00 100704010 805020 906030

VDD = VPVDD = 3VfIN = 1kHzZSPK = LOAD + 68µH

10% THD+N

1% THD+N

POWER-SUPPLY REJECTION RATIOvs. FREQUENCY

MAX

9875

toc2

7

FREQUENCY (Hz)

PSRR

(dB)

10k1k100

-90

-70

-60

-40

-30

-10

-80

-50

-20

0

-10010 100k

VDD = VPVDD = 3.7VVRIPPLE = 100mVP-PINPUTS AC-COUPLED TO GND

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______________________________________________________________________________________ 11


MAX

9875

toc3

0

FREQUENCY (kHz)

AMPL

ITUD

E (d

BV)

15105

0

-140

-80

-40

-120

-20

-60

-100

0 20


WIDEBAND OUTPUT SPECTRUM

MAX

9875

toc3

1

FREQUENCY (MHz)

AMPL

ITUD

E (d

BV)

0

-70

-40

-50

-20

-80

-60

-90

-30

-10

-1000.1 10 1001

fOSC = 1100kHzINPUTS AC-COUPLED TO GND


MAX

9875

toc3

2

FREQUENCY (MHz)

AMPL

ITUD

E (d

BV)

0

-70

-40

-50

-20

-80

-60

-90

-30

-10

-1000.1 10 1001



MAX

9875

toc3

3

FREQUENCY (MHz)

AMPL

ITUD

E (d

BV)

0

-70

-40

-50

-20

-80

-60

-90

-30

-10

-1000.1 10 1001


HARDWARE SHUTDOWN RESPONSE

MAX

9875

toc3

4

VBIAS500mV/div

20ms/div

OUT+ - OUT-1V/div

SOFTWARE SHUTDOWNON- AND OFF-RESPONSE

MAX

9875

toc3

5

VSDA2V/div

20ms/div

OUT+ - OUT-1V/div

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12 ______________________________________________________________________________________


HEADPHONE AMPLIFIER

TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY

MAX

9875

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6

FREQUENCY (Hz)

THD+

N (%

)

0

0.001

0.01

0.1

10 100 1k 10k 100k

VDD = VPVDD = 3.7VRHP = 32Ω

POUT = 10mW

POUT = 20mW


MAX

9875

toc3

7

FREQUENCY (Hz)

THD+

N (%

)1

0.001

0.01

0.1

10 100 1k 10k 100k


POUT = 20mW

POUT = 40mW


MAX

9875

toc3

8

FREQUENCY (Hz)

THD+

N (%

)

1

0.001

0.01

0.1

10 100 1k 10k 100k

VDD = VPVDD = 3VRHP = 32Ω

POUT = 10mW

POUT = 20mW


MAX

9875

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9

FREQUENCY (Hz)

THD+

N (%

)

1

0.001

0.01

0.1

10 100 1k 10k 100k


POUT = 15mW

POUT = 30mW


MAX

9875

toc4

0

OUTPUT POWER (mW)

THD+

N (%

)

302010

0.01

0.1

1

10

0.0010 40


fIN = 20Hz

fIN = 1kHz fIN = 6kHz


MAX

9875

toc4

1

OUTPUT POWER (mW)

THD+

N (%

)

0.01

0.1

1

10

0.0010 20 40 6010 30 50 70


fIN = 20Hz AND 1kHz

fIN = 6kHz


MAX

9875

toc4

2

OUTPUT POWER (mW)

THD+

N (%

)

302010

0.01

0.1

1

10

0.0010 40


fIN = 20Hz

fIN = 1kHz fIN = 6kHz


MAX

9875

toc4

3

OUTPUT POWER (mW)

THD+

N (%

)

0.01

0.1

1

10

0.0010 20 4010 30 50 60


fIN = 20Hz AND 1kHz

fIN = 6kHz

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______________________________________________________________________________________ 13


MAX

9875

toc4

6

SUPPLY VOLTAGE (V)

OUTP

UT P

OWER

(mW

)

5.04.54.03.53.0

50

0

10

20

30

40

45

5

15

25

35

2.5 5.5

fIN = 1kHzRHP = 32Ω

10% THD+N

1% THD+N


MAX

9875

toc4

7

SUPPLY VOLTAGE (V)

OUTP

UT P

OWER

(mW

)

5.04.54.03.53.0

100

0

20

40

60

80

90

10

30

50

70

2.5 5.5

fIN = 1kHzRHP = 16Ω

10% THD+N

1% THD+N


MAX

9875

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8


OUTP

UT P

OWER

(mW

)

100

0

20

40

60

80

90

10

30

50

70

10 40 70 10020 50 8030 60 90

VDD = VPVDD = 3.7VfIN = 1kHz

10% THD+N

1% THD+N


MAX

9875

toc4

9


OUTP

UT P

OWER

(mW

)

100

0

20

40

60

80

90

10

30

50

70

10 40 70 10020 50 8030 60 90

VDD = VPVDD = 3VfIN = 1kHz

10% THD+N

1% THD+N


MAX

9875

toc5

0


OUTP

UT P

OWER

(mW

)

100

0

20

40

60

80

90

10

30

50

70

10 40 70 10020 50 8030 60 90

VDD = VPVDD = 3VOSC = 10fIN = 1kHz1% THD+N

C1 = C2 = 2.2µF

C1 = C2 = 0.47µF

POWER-SUPPLY REJECTION RATIOvs. FREQUENCY

MAX

9875

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1

FREQUENCY (Hz)

PSRR

(dB)

0

-120

-80

-60

-40

-20-10

-90-100

-110

-70

-50

-30

10 100 1k 10k 100k

VDD = VPVDD = 3.7VVRIPPLE = 100mVP-PRHP = 32ΩINPUTS AC-COUPLED TO GND

HPR

HPL

POWER DISSIPATION vs. OUTPUT POWER

MAX

9875

toc4

4

OUTPUT POWER (mW)

POW

ER D

ISSI

PATI

ON (m

W)

350

0

250

50

150

300

100

200

0 15010050

VDD = VPVDD = 3.7VfIN = 1kHzPOUT = PHPL + PHPR

RHP = 32Ω

RHP = 16Ω

POWER DISSIPATION vs. OUTPUT POWER

MAX

9875

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5

OUTPUT POWER (mW)

POW

ER D

ISSI

PATI

ON (m

W)

250

0

50

150

100

200

0 15010050

VDD = VPVDD = 3VfIN = 1kHzPOUT = PHPL + PHPR

RHP = 32Ω

RHP = 16Ω

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14 ______________________________________________________________________________________


COMMON-MODE REJECTION RATIOvs. FREQUENCY

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9875

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5

FREQUENCY (Hz)

CMRR

(dB)

80

0

20

40

60

10

70

30

50

10 100k10k1k100

VDD = VPVDD = 3.7VCMRR = 20log(ADM/ACM)

+9dB

+20dB

0dB

HARDWARE SHUTDOWN RESPONSE

MAX

9875

toc5

6

VBIAS500mV/div

HPL500mV/div

20ms/div

HPR500mV/div

SOFTWARE SHUTDOWNON- AND OFF-REPSONSE

MAX

9875

toc5

7

VBIAS500mV/div

HPL500mV/div

20ms/div

HPR500mV/div

OUTPUT SPECTRUM

MAX

9875

toc5

2

FREQUENCY (kHz)

AMPL

ITUD

E (d

BV)

0

-140

-100

-60

-20

-120

-80

-40

0 2015105

VDD = VPVDD = 3.7VfIN = 1kHzRHP = 32Ω

OUTPUT SPECTRUM

MAX

9875

toc5

3

FREQUENCY (kHz)

AMPL

ITUD

E (d

BV)

0

-140

-100

-60

-20

-120

-80

-40

0 2015105

VDD = VPVDD = 3.7VfIN = 1kHzRHP = 16Ω

CROSSTALK vs. FREQUENCY

MAX

9875

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4

FREQUENCY (Hz)

CROS

STAL

K (d

B)

0

-120

-30

-10

-50

-90

-60

-100-110

-70

-20

-40

-80

10 100k10k1k100

VDD = VPVDD = 3.7VVINA_ = 1VP-PRHP = 16Ω

HPR TO HPL

HPL TO HPR

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______________________________________________________________________________________ 15

Pin Description

PIN NAME FUNCTION

A1 HPR Right Headphone Output

A2 HPL Left Headphone Output

A3 VSS Headphone Amplifier Negative Power Supply. Bypass with a 1µF capacitor to PGND.

A4 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor between C1P and C1N.

A5 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor between C1P and C1N.

B1 VDD Analog Supply. Connect to PVDD. Bypass with a 1µF capacitor to GND.

B2 BIASCommon-Mode Bias. Bypass to GND with a 1µF capacitor. Pulse low to reset the part and place inshutdown (see the Typical Application Circuit).

B3 SDA Serial-Data Input. Connect a pullup resistor from SDA to a 1.7V to 3.6V supply.

B4 N.C. No Connection

B5 OUT+ Positive Speaker Output

C1 INB2 Input B2. Right input or positive input (see the Differential Input Configuration (∆IN_) section).

C2 INB1 Input B1. Left input or negative input (see the Differential Input Configuration (∆IN_) section).

C3 SCL Serial-Clock Input. Connect a pullup resistor from SCL to a 1.7V to 3.6V supply.

C4 PGND Power Ground

C5 PVDD Class D and Charge-Pump Power Supply. Bypass with a 1µF capacitor to PGND.

D1 INA2 Input A2. Right input or positive input (see the Differential Input Configuration (∆IN_) section).

D2 INA1 Input A1. Left input or negative input (see the Differential Input Configuration (∆IN_) section).

D3 GND Analog Ground

D4 N.C. No Connection

D5 OUT- Negative Speaker Output

Detailed DescriptionSignal Path

The MAX9875 signal path consists of flexible inputs,signal mixing, volume control, and output amplifiers(Figure 1).

The inputs can be configured for single-ended or differ-ential signals (Figure 2). The internal preamplifiers fea-ture three programmable gain settings of 0dB, +9dB,and +20dB. Following preamplification, the input sig-nals are mixed, volume adjusted, and routed to theheadphone and speaker amplifiers based on the out-put mode configuration (see Table 7). The volume con-trol stages provide up to 75dB attenuation. Theheadphone amplifier is configured as a unity-gain

buffer while the speaker amplifier provides +12dB ofadditional gain.

When an input is configured as mono differential it canbe routed to the speaker or to both headphones. Whenan input is stereo, it is mixed to mono without attenuationfor the speaker and kept stereo for the headphones.

When the application does not require the use of bothINA_ and INB_, the SNR of the MAX9875 is improvedby deselecting the unused input through the I2C outputmode register and AC-coupling the unused inputs toground with a 330pF capacitor. The 330pF capacitorand the input resistance to the MAX9875 form a high-pass filter preventing audible noise from coupling intothe outputs.

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16 ______________________________________________________________________________________

MIXERANDMUX

INPUT A0dB/+9dB/+20dB

INA2

INA1

INPUT B0dB/+9dB/+20dB

INB2

INB1

-75dB TO 0dB

0dB HPR

-75dB TO 0dB

0dB HPL

-75dB TO 0dB

+12dBOUT+

OUT-

Figure 1. Signal Path

IN_2 (R)

R

L

IN_1 (L)

STEREO SINGLE-ENDED

TO MIXER

IN_2 (+)

IN_1 (-)

DIFFERENTIAL

TO MIXER

Figure 2. Differential and Stereo Single-Ended Input Configurations

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______________________________________________________________________________________ 17

Volume Control and MuteThe MAX9875 features three volume control registers(see Table 4) allowing independent volume control ofmono speaker and stereo headphone amplifier outputs.Each volume control register has 31 steps providing 0 to75dB (typ) of attenuation and a mute function.

Class D Speaker AmplifierThe MAX9875 integrates a filterless Class D amplifierthat offers much higher efficiency than Class AB with-out the typical disadvantages.

The high efficiency of a Class D amplifier is due to theswitching operation of the output stage transistors. In aClass D amplifier, the output transistors act as current-steering switches and consume negligible additionalpower. Any power loss associated with the Class D out-put stage is mostly due to the I2R loss of the MOSFETon-resistance, and quiescent current overhead.

The theoretical best efficiency of a linear amplifier is78%, however, that efficiency is only exhibited at peakoutput power. Under normal operating levels (typicalmusic reproduction levels), efficiency falls below 30%,whereas the MAX9875 still exhibits 70% efficiencyunder the same conditions (Figure 3).

Ultra-Low EMI Filterless Output StageIn traditional Class D amplifiers, the high dV/dt of therising and falling edge transitions results in increasedEMI emissions, which requires the use of external LCfilters or shielding to meet EN55022 electromagnetic-interference (EMI) regulation standards. Limiting the

dV/dt normally results in decreased efficiency. Maxim’sactive emissions limiting circuitry actively limits thedV/dt of the rising and falling edge transitions, provid-ing reduced EMI emissions, while maintaining up to87% efficiency.

In addition to active emission limiting, the MAX9875features a spread-spectrum modulation mode that flat-tens the wideband spectral components. Proprietarytechniques ensure that the cycle-to-cycle variation ofthe switching period does not degrade audio reproduc-tion or eff iciency (see the Typical OperatingCharacteristics). Select spread-spectrum modulationmode through the I2C interface (Table 6). In spread-spectrum modulation mode, the switching frequencyvaries randomly by ±60kHz around the center frequen-cy (1.176MHz). The effect is to reduce the peak energyat harmonics of the switching frequency. Above10MHz, the wideband spectrum looks like white noisefor EMI purposes (see Figure 4).

Speaker Current LimitMost applications will not enter current limit unless theoutput is short circuited or connected incorrectly.

When the output current of the speaker amplifierexceeds the current limit (1.5A, typ) the MAX9875 dis-ables the outputs for approximately 250µs. At the end of250µs, the outputs are re-enabled, if the fault conditionstill exists, the MAX9875 will continue to disable and re-enable the outputs until the fault condition is removed.

MAX9875 EFFICIENCY vs. IDEAL CLASS EFFICIENCY

MAX

9875

fig0

3

OUTPUT POWER (W)

EFFI

CIEN

CY (%

)

0.750.500.25

10

20

30

40

50

60

70

80

90

100

00 1.00

MAX9875

IDEAL CLASS AB

VDD = VPVDD = 3.7V (MAX9875)VSUPPLY = 3.7V (IDEAL CLASS AB)

Figure 3. MAX9875 Efficiency vs. Class AB Efficiency

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18 ______________________________________________________________________________________

DirectDrive Headphone AmplifierTraditional single-supply headphone amplifiers haveoutputs biased at a nominal DC voltage (typically halfthe supply). Large coupling capacitors are needed toblock this DC bias from the headphone. Without thesecapacitors, a significant amount of DC current flows tothe headphone, resulting in unnecessary power dissi-pation and possible damage to both the headphoneand headphone amplifier.

Maxim’s DirectDrive architecture uses a charge pump tocreate an internal negative supply voltage. This allowsthe headphone outputs of the MAX9875 to be biased atGND while operating from a single supply (Figure 5).Without a DC component, there is no need for the largeDC-blocking capacitors. Instead of two large (220µF,typ) capacitors, the MAX9875 charge pump requirestwo small ceramic capacitors, conserving board space,

reducing cost, and improving the frequency response ofthe headphone amplifier. See the Output Power vs.Load Resistance graph in the Typical OperatingCharacteristics for details of the possible capacitorsizes. There is a low DC voltage on the amplifier outputsdue to amplifier offset. However, the offset of theMAX9875 is typically ±0.15mV, which, when combinedwith a 32Ω load, results in less than 10µA of DC currentflow to the headphones.

In addition to the cost and size disadvantages of theDC-blocking capacitors required by conventional head-phone amplifiers, these capacitors limit the amplifier’slow-frequency response and can distort the audio sig-nal. Previous attempts at eliminating the output-cou-pling capacitors involved biasing the headphone return(sleeve) to the DC bias voltage of the headphoneamplifiers. This method raises some issues:

FREQUENCY (MHz)

AMPL

ITUD

E (d

B∝V/

m)

1601401201008060

10

15

20

25

30

35

40TEST LIMIT

MAX9875 OUTPUT

MAX9875 OUTPUT

TEST LIMIT

530 180 200 240 260 280 300220

FREQUENCY (MHz)

AMPL

ITUD

E (d

B∝V/

m)

600550500450400350

15

20

25

35

40

10300 650 700 800 850 900 1000950750

Figure 4. EMI with 152mm of Speaker Cable

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______________________________________________________________________________________ 19

1) The sleeve is typically grounded to the chassis.Using the midrail biasing approach, the sleeve mustbe isolated from system ground, complicating prod-uct design.

2) During an ESD strike, the amplifier’s ESD structuresare the only path to system ground. Thus, the ampli-fier must be able to withstand the full energy from anESD strike.

3) When using the headphone jack as a line out toother equipment, the bias voltage on the sleeve mayconflict with the ground potential from other equip-ment, resulting in possible damage to the amplifiers.

The MAX9875 features a low-noise charge pump. Theswitching frequency of the charge pump is 1/2 of theClass D switching frequency, regardless of the operatingmode. When the Class D amplifiers are operated inspread-spectrum mode, the charge pump also switcheswith a spread-spectrum pattern. The nominal switchingfrequency is well beyond the audio range, and thus doesnot interfere with audio signals. The switch drivers fea-ture a controlled switching speed that minimizes noisegenerated by turn-on and turn-off transients. By limitingthe switching speed of the charge pump, the di/dt noisecaused by the parasitic trace inductance is minimized.

Although not typically required, additional high-frequen-cy noise attenuation can be achieved by increasing thesize of C2 (see the Typical Application Circuit). Thecharge pump is active only in headphone modes.

Headphone Current LimitThe headphone amplifier current is limited to 140mA (typ).The current limit clamps the output current, which appearsas clipping when the maximum current is exceeded.

Shutdown ModeThe MAX9875 features two ways of entering low-powershutdown. The hardware shutdown function is controlledby pulsing BIAS low for 1ms. While BIAS is low the ampli-fiers are shut down. Following an 80ms reset period, theMAX9875 reverts to its power-on-reset condition. PullBIAS low using an open-drain output that is not pulled upwith a resistor (see the Typical Application Circuit). Theopen-drain output leakage must not exceed 100nA andmust be able to sink at least 1mA.

The device can also be placed in shutdown mode bywriting to the SHDN bit in the Output Mode ControlRegister.

Click-and-Pop SuppressionThe MAX9875 features click-and-pop suppression thateliminates audible transients from occurring at startupand shutdown.

Use the following procedure to start up the MAX9875:

1) Configure the desired output mode and preamplifier gain.

2) Set the SHDN bit to 1 to start up the amplifier.

3) Wait 10ms for the startup time to pass.

4) Increase the output volume to the desired level.

To disable the device simply set SHDN to 0.

During the startup period, the MAX9875 precharges theinput capacitors to prevent clicks and pops. If the outputamplifiers have been programmed to be active they areheld in shutdown until the precharge period is complete.

When power is initially applied to the MAX9875, thepower-on-reset state of all three volume control registersis mute. For most applications, the volume can be set tothe desired level once the device is active. If the click-and-pop is too high, step through intermediate volumesettings with zero-crossing detection disabled. Steppingthrough higher volume settings has a greater impact onclick-and-pop than lower volume settings.

For the lowest possible click-and-pop, start up the deviceat minimum volume and then step through each volumesetting until the desired setting is reached. Disable zero-crossing detection if no input signal is expected.

VDD

VDD/2

GNDCONVENTIONAL AMPLIFIER BIASING SCHEME

DirectDrive AMPLIFIER BIASING SCHEME

+VDD

GND

-VDD(VSS)

Figure 5. Traditional Amplifier Output vs. MAX9875 DirectDriveOutput

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20 ______________________________________________________________________________________

I2C Register DescriptionZero-Crossing Detection (ZCD)

Zero-crossing detection limits distortion in the outputsignal during volume transitions by delaying the transi-tion until the mixer output crosses the internal bias volt-age. A timeout period (typically 60ms) forces thevolume transition if the mixer output signal does notcross the bias voltage.

1 = Zero-crossing detection is enabled.

0 = Zero-crossing detection is disabled.

Differential Input Configuration (∆IN_)The inputs INA_ and INB_ can be configured for monodifferential or stereo single-ended operation.

1 = IN__ is configured as a mono differential input withIN_2 as the positive and IN_1 as the negative input.

0 = IN__ is configured as a stereo single-ended inputwith IN_2 as the right and IN_1 as the left input.

Preamplifier Gain (PGAIN_)The preamplifier gain of INA_ and INB_ can be pro-grammed by writing to PGAIN_.

00 = 0dB

01 = +9dB

10 = +20dB

11 = Reserved

The MAX9875 is controlled through five I2C program-mable registers. Table 1 shows the MAX9875’s com-plete register map. Tables 2, 3, and 5 show theindividual registers.

I2C AddressThe slave address of the MAX9875 is 1001101R/(W).

Table 1. Register Map

REGISTERREGISTERADDRESS

POR STATE B7 B6 B5 B4 B3 B2 B1 B0

Input ModeControl

0x00 0x40 0 ZCD ∆INA ∆INB PGAINA PGAINB

SpeakerVolumeControl

0x01 0x00 0 0 0 SVOL (Table 4)

LeftHeadphoneVolumeControl

0x02 0x00 0 0 0 HPLVOL (Table 4)

RightHeadphoneVolumeControl

0x03 0x00 0 0 0 HPRVOL (Table 4)

Output ModeControl

0x04 0x49 SHDN 0 OSC (Table 6) OUTMODE (Table 7)

Table 2. Input Mode Control

REGISTER B7 B6 B5 B4 B3 B2 B1 B0

0x00 0 ZCD ∆INA ∆INB PGAINA PGAINB

I2C Interface

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______________________________________________________________________________________ 21

Shutdown (SSHHDDNN)1 = MAX9875 operational.

0 = MAX9875 in low-power shutdown mode.

SHDN is an active-low shutdown bit that overrides allsettings and places the entire device in low-power shut-down mode. The I2C interface is fully active in this shut-down mode. All register settings are preserved while inshutdown.

Volume ControlThe device has a separate volume control for left head-phone, right headphone, and speaker amplifiers. The

total system gain is a combination of the input gain, thevolume control, and the output amplifier gain. Table 4shows the volume settings for each volume control.

Table 4. Volume Control Settings

_VOLCODE

B4 B3 B2 B1 B0GAIN (dB)

0 0 0 0 0 0 MUTE

1 0 0 0 0 1 -75

2 0 0 0 1 0 -71

3 0 0 0 1 1 -67

4 0 0 1 0 0 -63

5 0 0 1 0 1 -59

6 0 0 1 1 0 -55

7 0 0 1 1 1 -51

8 0 1 0 0 0 -47

9 0 1 0 0 1 -44

10 0 1 0 1 0 -41

11 0 1 0 1 1 -38

12 0 1 1 0 0 -35

13 0 1 1 0 1 -32

14 0 1 1 1 0 -29

15 0 1 1 1 1 -26

_VOLCODE

B4 B3 B2 B1 B0GAIN (dB)

16 1 0 0 0 0 -23

17 1 0 0 0 1 -21

18 1 0 0 1 0 -19

19 1 0 0 1 1 -17

20 1 0 1 0 0 -15

21 1 0 1 0 1 -13

22 1 0 1 1 0 -11

23 1 0 1 1 1 -9

24 1 1 0 0 0 -7

25 1 1 0 0 1 -6

26 1 1 0 1 0 -5

27 1 1 0 1 1 -4

28 1 1 1 0 0 -3

29 1 1 1 0 1 -2

30 1 1 1 1 0 -1

31 1 1 1 1 1 0

Table 5. Output Mode Control


0x04 SHDN 0 OSC (Table 6 ) OUTMODE (Table 7)

Table 3. Speaker/Left Headphone/Right Headphone Volume Control


0x01 0 0 0 SVOL (Table 4)

0x02 0 0 0 HPLVOL (Table 4)

0x03 0 0 0 HPRVOL (Table 4)

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22 ______________________________________________________________________________________

Table 6. Oscillator ModesOSC

B5 B4CLASS D OSCILLATOR MODE (kHz) CHARGE-PUMP OSCILLATOR MODE (kHz)

0 0 1176, spread spectrum 588, spread spectrum

0 1 1100, fixed frequency 550, fixed frequency

1 0 700, fixed frequency 350, fixed frequency

1 1 Reserved

Table 7. Output Modes

OUTMODE

∆IN_ = 0(THE SINGLE-ENDED INPUT SIGNALS

ARE DEFINED AS IN_1 = LEFT ANDIN_2 = RIGHT)

∆IN_ = 1(THE DIFFERENTIAL INPUT SIGNAL IS

DEFINED AS IN_∆ = IN_2 - IN_1)MODE

B3 B2 B1 B0 SPK LEFT HP RIGHT HP SPK LEFT HP RIGHT HP

0 0 0 0 0 Reserved Reserved

1 0 0 0 1 INA1+INA2 — — INA∆ — —

2 0 0 1 0 — INA1 INA2 — INA∆ INA∆

3 0 0 1 1 INA1+INA2 INA1 INA2 INA∆ INA∆ INA∆

4 0 1 0 0 INB1+INB2 — — INB∆ — —

5 0 1 0 1 — INB1 INB2 — INB∆ INB∆

6 0 1 1 0 INB1+INB2 INB1 INB2 INB∆ INB∆ INB∆

7 0 1 1 1INA1+INA2

+INB1+INB2— — INA∆+INB∆ — —

8 1 0 0 0 — INA1+INB1 INA2+INB2 —INA∆

+INB∆INA∆ +INB∆

9 1 0 0 1INA1+INA2

+INB1+INB2INA1+INB1 INA2+INB2 INA∆+INB∆

INA∆+INB∆

INA∆ +INB∆

10–15 Reserved Reserved

— = Amplifier Off

Output Configuration (OUTMODE)The MAX9875 has a stereo DirectDrive headphone ampli-fier and a mono Class D amplifier. Table 7 shows how

each of the output amplifiers can be configured and con-nected to the input signals. For simplicity, not all possiblecombinations of ∆INA and ∆INB are shown.

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______________________________________________________________________________________ 23

SCL

SDA

STARTCONDITION

STOPCONDITION

REPEATED START CONDITION

START CONDITION

tHD:STA

tSU:STAtSU:STA

tBUF

tSU:STOtLOW

tSU:DATtHD:DAT

tHIGH

tR tF

Figure 6. 2-Wire Interface Timing Diagram

SCL

SDA

S Sr P

Figure 7. START, STOP, and REPEATED START Conditions

SMBus is a trademark of Intel Corp.

I2C Interface SpecificationThe MAX9875 features an I2C/SMBus™-compatible, 2-wire serial interface consisting of a serial-data line(SDA) and a serial-clock line (SCL). SDA and SCL facil-itate communication between the MAX9875 and themaster at clock rates up to 400kHz. Figure 6 shows the2-wire interface timing diagram. The master generatesSCL and initiates data transfer on the bus. The masterdevice writes data to the MAX9875 by transmitting theproper slave address followed by the register addressand then the data word. Each transmit sequence isframed by a START (S) or REPEATED START (Sr) con-dition and a STOP (P) condition. Each word transmittedto the MAX9875 is 8 bits long and is followed by anacknowledge clock pulse. A master reading data fromthe MAX9875 transmits the proper slave address fol-lowed by a series of nine SCL pulses. The MAX9875transmits data on SDA in sync with the master-generat-ed SCL pulses. The master acknowledges receipt ofeach byte of data. Each read sequence is framed by aSTART or REPEATED START condition, a not acknowl-edge, and a STOP condition. SDA operates as both aninput and an open-drain output. A pullup resistor, typi-cally greater than 500Ω, is required on SDA. SCL oper-ates only as an input. A pullup resistor, typically greater

than 500Ω, is required on SCL if there are multiple mas-ters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA andSCL are optional. Series resistors protect the digitalinputs of the MAX9875 from high voltage spikes on thebus lines, and minimize crosstalk and undershoot of thebus signals.

Bit TransferOne data bit is transferred during each SCL cycle. Thedata on SDA must remain stable during the high periodof the SCL pulse. Changes in SDA while SCL is highare control signals (see the START and STOPConditions section).

START and STOP ConditionsSDA and SCL idle high when the bus is not in use. Amaster initiates communication by issuing a START con-dition. A START condition is a high-to-low transition onSDA with SCL high. A STOP condition is a low-to-hightransition on SDA while SCL is high (Figure 7). A STARTcondition from the master signals the beginning of atransmission to the MAX9875. The master terminatestransmission, and frees the bus, by issuing a STOP con-dition. The bus remains active if a REPEATED STARTcondition is generated instead of a STOP condition.

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24 ______________________________________________________________________________________

A0SLAVE ADDRESS REGISTER ADDRESS DATA BYTE

ACKNOWLEDGE FROM MAX9875

R/W 1 BYTE

AUTOINCREMENT INTERNALREGISTER ADDRESS POINTER



B1 B0B3 B2B5 B4B7 B6

S AA P

Figure 9. Writing One Byte of Data to the MAX9875

1SCL

STARTCONDITION

SDA

2 8 9

CLOCK PULSE FORACKNOWLEDGMENT

ACKNOWLEDGE

NOT ACKNOWLEDGE

Figure 8. Acknowledge

Early STOP ConditionsThe MAX9875 recognizes a STOP condition at anypoint during data transmission except if the STOP con-dition occurs in the same high pulse as a START condi-tion. For proper operation, do not send a STOPcondition during the same SCL high pulse as theSTART condition.

Slave AddressThe MAX9875 is preprogrammed with a slave addressof 1001101R/(W). The address is defined as the sevenmost significant bits (MSBs) followed by the Read/Writebit. Setting the Read/Write bit to 1 configures theMAX9875 for read mode. Setting the Read/Write bit to 0configures the MAX9875 for write mode. The address isthe first byte of information sent to the MAX9875 afterthe START condition.

AcknowledgeThe acknowledge bit (ACK) is a clocked 9th bit that theMAX9875 uses to handshake receipt each byte of datawhen in write mode (see Figure 8). The MAX9875 pullsdown SDA during the entire master-generated 9thclock pulse if the previous byte is successfullyreceived. Monitoring ACK allows for detection of unsuc-cessful data transfers. An unsuccessful data transfer

occurs if a receiving device is busy or if a system faulthas occurred. In the event of an unsuccessful datatransfer, the bus master may retry communication.

The master pulls down SDA during the ninth clockcycle to acknowledge receipt of data when theMAX9875 is in read mode. An acknowledge is sent bythe master after each read byte to allow data transfer tocontinue. A not acknowledge is sent when the masterreads the final byte of data from the MAX9875, followedby a STOP condition.

Write Data FormatA write to the MAX9875 includes transmission of aSTART condition, the slave address with the R/W bit setto 0, one byte of data to configure the internal registeraddress pointer, one or more bytes of data, and aSTOP condition. Figure 9 illustrates the proper frameformat for writing one byte of data to the MAX9875.Figure 10 illustrates the frame format for writing n-bytesof data to the MAX9875.

The slave address with the R/W bit set to 0 indicatesthat the master intends to write data to the MAX9875.The MAX9875 acknowledges receipt of the addressbyte during the master-generated 9th SCL pulse.

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1 BYTE


ACKNOWLEDGE FROM MAX9875NOT ACKNOWLEDGE FROM MASTER

AA PA0


R/W

S A

R/WREPEATED START

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

Figure 11. Reading One Indexed Byte of Data from the MAX9875

1 BYTE





A A0


R/W

S A

1 BYTE



PASLAVE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n

Figure 10. Writing n-Bytes of Data to the MAX9875

The second byte transmitted from the master config-ures the MAX9875’s internal register address pointer.The pointer tells the MAX9875 where to write the nextbyte of data. An acknowledge pulse is sent by theMAX9875 upon receipt of the address pointer data.

The third byte sent to the MAX9875 contains the datathat will be written to the chosen register. An acknowl-edge pulse from the MAX9875 signals receipt of thedata byte. The address pointer autoincrements to thenext register address after each received data byte.This autoincrement feature allows a master to write tosequential registers within one continuous frame. Figure10 illustrates how to write to multiple registers with oneframe. The master signals the end of transmission byissuing a STOP condition.

Register addresses greater than 0x04 are reserved. Donot write to these addresses.

Read Data FormatSend the slave address with the R/W bit set to 1 to initiatea read operation. The MAX9875 acknowledges receipt ofits slave address by pulling SDA low during the 9th SCLclock pulse. A START command followed by a readcommand resets the address pointer to register 0x00.The first byte transmitted from the MAX9875 will be the

contents of register 0x00. Transmitted data is valid on therising edge of SCL. The address pointer autoincrementsafter each read data byte. This autoincrement featureallows all registers to be read sequentially within onecontinuous frame. A STOP condition can be issued afterany number of read data bytes. If a STOP condition isissued followed by another read operation, the first databyte to be read will be from register 0x00.

The address pointer can be preset to a specific registerbefore a read command is issued. The master presetsthe address pointer by first sending the MAX9875‘sslave address with the R/W bit set to 0 followed by theregister address. A REPEATED START condition is thensent followed by the slave address with the R/W bit setto 1. The MAX9875 then transmits the contents of thespecified register. The address pointer autoincrementsafter transmitting the first byte. The master acknowl-edges receipt of each read byte during the acknowl-edge clock pulse. The master must acknowledge allcorrectly received bytes except the last byte. The finalbyte must be followed by a not acknowledge from themaster and then a STOP condition. Figure 11 illustratesthe frame format for reading one byte from theMAX9875. Figure 12 illustrates the frame format forreading multiple bytes from the MAX9875.

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26 ______________________________________________________________________________________

Applications InformationFilterless Class D Operation

Traditional Class D amplifiers require an output filter torecover the audio signal from the amplifier’s output. Thefilters add cost, increase the solution size of the amplifier,and can decrease efficiency and THD+N performance.The traditional PWM scheme uses large differential out-put swings (2 x VDD(P-P)) and causes large ripple cur-rents. Any parasitic resistance in the filter componentsresults in a loss of power, lowering the efficiency.

The MAX9875 does not require an output filter. Thedevice relies on the inherent inductance of the speakercoil and the natural filtering of both the speaker and thehuman ear to recover the audio component of thesquare-wave output. Eliminating the output filter resultsin a smaller, less costly, more efficient solution.

Because the frequency of the MAX9875 output is wellbeyond the bandwidth of most speakers, voice coilmovement due to the square-wave frequency is verysmall. Although this movement is small, a speaker notdesigned to handle the additional power can be dam-aged. For optimum results, use a speaker with a seriesinductance > 10µH. Typical 8Ω speakers exhibit seriesinductances in the 20µH to 100µH range.

Component SelectionOptional Ferrite Bead Filter

In applications where speaker leads exceed 20mm,additional EMI suppression can be achieved by using afilter constructed from a ferrite bead and a capacitor toground. A ferrite bead with low DC resistance, high-frequency (> 1.176MHz) impedance of 100Ω to 600Ω,and rated for at least 1A should be used. The capacitorvalue varies based on the ferrite bead chosen and theactual speaker lead length. Select a capacitor less than1nF based on EMI performance.

Input CapacitorAn input capacitor, CIN, in conjunction with the inputimpedance of the MAX9875 forms a highpass filter thatremoves the DC bias from an incoming signal. The AC-

coupling capacitor allows the amplifier to automaticallybias the signal to an optimum DC level. Assuming zerosource impedance, the -3dB point of the highpass filteris given by:

Choose CIN so that f-3dB is well below the lowest fre-quency of interest. Use capacitors whose dielectricshave low-voltage coefficients, such as tantalum or alu-minum electrolytic. Capacitors with high-voltage coeffi-cients, such as ceramics, may result in increaseddistortion at low frequencies.

BIAS CapacitorBIAS is the output of the internally generated DC bias volt-age. The BIAS bypass capacitor, CBIAS, reduces powersupply and other noise sources at the common-modebias node. Bypass BIAS with a 1µF capacitor to GND.

Charge-Pump Capacitor SelectionUse capacitors with an ESR less than 100mΩ for optimumperformance. Low-ESR ceramic capacitors minimize theoutput resistance of the charge pump. Most surface-mount ceramic capacitors satisfy the ESR requirement.For best performance over the extended temperaturerange, select capacitors with an X7R dielectric.

Flying Capacitor (C1)The value of the flying capacitor (C1) affects the outputresistance of the charge pump. A C1 value that is toosmall degrades the device’s ability to provide sufficientcurrent drive, which leads to a loss of output voltage.

fR CdB

IN IN− =3

12π

MAX9875

OUT+

OUT-

Figure 13. Optional Ferrite Bead Filter


1 BYTE



AA A P0


R/W

S A

R/WREPEATED START

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

Figure 12. Reading n-Bytes of Indexed Data from the MAX9875

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Increasing the value of C1 reduces the charge-pump out-put resistance to an extent. Above 1µF, the on-resistanceof the switches and the ESR of C1 and C2 dominate.

Output Holding Capacitor (C2)The output capacitor value and ESR directly affect theripple at VSS. Increasing the value of C2 reduces outputripple. Likewise, decreasing the ESR of C2 reduces bothripple and output resistance. Lower capacitance valuescan be used in systems with low maximum output powerlevels. See the Output Power vs. Load Resistance graphin the Typical Operating Characteristics.

PVDD Bulk Capacitor (C3)In addition to the recommended PVDD bypass capaci-tance, bulk capacitance equal to C3 should be used.Place the bulk capacitor as close to the device as possible.

Supply Bypassing, Layout, and Grounding

Proper layout and grounding are essential for optimumperformance. Use wide traces for the power-supplyinputs and amplifier outputs to minimize losses due toparasitic trace resistance. Wide traces also aid in mov-ing heat away from the package. Proper groundingimproves audio performance, minimizes crosstalkbetween channels, and prevents any switching noisefrom coupling into the audio signal. Connect PGND andGND together at a single point on the PCB. Route alltraces that carry switching transients away from GNDand the traces/components in the audio signal path.

Connect PVDD to a 2.7V to 5.25V source. BypassPVDD to the PGND pin with a 1µF ceramic capacitor.Additional bulk capacitance should be used to preventpower-supply pumping. Place the bypass capacitorsas close to the MAX9875 as possible.

Connect VDD to PVDD. Bypass VDD to GND with a 1µFcapacitor. Place the bypass capacitors as close to theMAX9875 as possible.

RF SusceptibilityGSM radios transmit using time-division multipleaccess (TDMA) with 217Hz intervals. The result is anRF signal with strong amplitude modulation at 217Hzthat is easily demodulated by audio amplifiers. Figure14 shows the susceptibility of the MAX9875 to a trans-mitting GSM radio placed in close proximity. Althoughthere is measurable noise at 217Hz and its harmonics,the noise is well below the threshold of hearing usingtypical headphones.

In RF applications, improvements to both layout andcomponent selection decreases the MAX9875’s sus-

ceptibility to RF noise and prevent RF signals frombeing demodulated into audible noise. Trace lengthsshould be kept below 1/4 the wavelength of the RF fre-quency of interest. Minimizing the trace lengths pre-vents them from functioning as antennas and couplingRF signals into the MAX9875. The wavelength λ inmeters is given by:

λ = c/f

where c = 3 x 108m/s, and f = the RF frequency of inter-est.

Route audio signals on middle layers of the PCB toallow ground planes above and below shield them fromRF interference. Ideally the top and bottom layers of thePCB should primarily be ground planes to create effec-tive shielding.

Additional RF immunity can also be obtained from rely-ing on the self-resonant frequency of capacitors as itexhibits the frequency response similar to a notch filter.Depending on the manufacturer, 10pF to 20pF capaci-tors typically exhibit self resonance at RF frequencies.These capacitors, when placed at the input pins, caneffectively shunt the RF noise at the inputs of theMAX9875. For these capacitors to be effective, theymust have a low-impedance, low-inductance path tothe ground plane. Do not use microvias to connect tothe ground plane as these vias do not conduct well atRF frequencies.

RF SUSCEPTIBILITY

MAX

9875

fig1

4

FREQUENCY (Hz)

EFFI

CIEN

CY (d

Bµ)

10k1k100

-130

-110

-90

-70

-50

-30

-10

-15010 100k

THRESHOLD OF HEARING

MAX9875

NOISE FLOOR

Figure 14. MAX9875 Susceptibility to a GSM Cell Phone Radio

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WLP Applications InformationFor the latest application details on WLP construction,dimensions, tape carrier information, PCB techniques,bump-pad layout, and recommended reflow tempera-ture profile, as well as the latest information on reliabilitytesting results, refer to the Application Note: UCSP—AWafer-Level Chip-Scale Package on Maxim’s websiteat www.maxim-ic.com/ucsp. See Figure 15 for therecommended PCB footprint for the MAX9875.

250µm 45±5µm

Figure 15. PCB Footprint Recommendation Diagram

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Typical Application Circuit

CHARGEPUMP

MIXERANDMUX

CLASS DMODULATOR

+12dB

INPUT A0dB/+9dB/+20dB

INA2

INA1

D1

D2

C1N

INPUT A

INPUT B

C1P

A4

A5

BIASB2

B5

D5

OUT+

A1 HPR

A2 HPL

OUT-

I2CCONTROL

SDA

SCL

B3

C3

-75dB TO 0dB

0dB

0dB

-75dB TO 0dB

-75dB TO 0dB

C11µF

1µF

1µF

INPUT B0dB/+9dB/+20dB

INB2

INB1

C1

C2

1µF

1µF

1µF

OPEN-DRAIN GPIO

D3

GND

C4

PGND

MAX9875

A3

VSS

C21µF

B1

VDD

1µF

VBATT VBATT

C5

PVDD

C31µF

Chip InformationPROCESS: BiCMOS

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

30 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Package InformationFor the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

20 WLP R202A2+2 21-0059

20L

WLP

.EP

S

http://pdfserv.maxim-ic.com/package_dwgs/21-0059.PDF

EVALUATION KIT Low RF Susceptibility, Mono Audio … · 2010-06-10 · ♦ Low RF Susceptibility...

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