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A1

A2

A3

40kΩ40kΩ

40kΩ40kΩ

VIN

2

1

8

3

6

5

VIN

RG

V+

V−

Ref

VO

G = 1 +49.4kΩ

RG

−

+

4

7

NOTE: (1) INA129: 24.7kΩ

G = 1 +50kΩ

RG

INA128, INA129Over-Voltage

Protection

Over-Voltage

Protection

25k

Ω

(1)

25kΩ(1)

INA128:

INA129:

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英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SBOS051

INA128, INA129JAJSEJ5E –OCTOBER 1995–REVISED APRIL 2019

参参考考資資料料

INA12x 高高精精度度、、低低消消費費電電力力のの計計装装アアンンププこのデバイスには新しいバージョン INA828 が存在します

1

1 特特長長1• このデバイスには新しいバージョン INA828 が存

在します• 低いオフセット電圧： 50μV (最大値)• 低いドリフト係数： 0.5μV/°C (最大値)• 低い入力バイアス電流： 5nA (最大値)• 高い CMR： 120dB (最小値)• ±40V までの入力保護• 広い電源電圧範囲: ±2.25V～±18V• 低い静止電流: 700μA• パッケージ： 8 ピンのプラスチック DIP、SO-8

2 アアププリリケケーーシショョンン• ブリッジ・アンプ• 熱電対アンプ• RTD センサ・アンプ• 医療用計測装置• データ・アクイジション

3 概概要要INA128とINA129は、低消費電力の汎用計装アンプで、

精度が非常に優れています。多用途の3オペアンプ設計

と小さなサイズから、これらのアンプは広範なアプリケー

ションに理想的です。電流フィードバック入力回路により、

高いゲインでも広い帯域幅が得られます (G = 100 で

200kHz)。

単一の外付け抵抗によって、1～10,000の範囲でゲインを

設定できます。INA128は業界標準のゲインの式を提供し

ます。INA129のゲインの式はAD620と互換性があります。

INA12xは8ピンのプラスチックDIPおよびSO-8表面実装

パッケージで供給され、-40～+85の温度範囲で動作

が規定されています。また、INA128にはデュアル構成の

INA2128も用意されています。

アップグレードされた INA828 は、同じ静止電流で入力バ

イアス電流 (最大値 0.6nA) とノイズ (7 nV/√Hz) がさらに

低減しています。テキサス・インスツルメンツ製の高精度計

装アンプのラインナップについては、「デバイスの比較」を

参照してください。

製製品品情情報報(1)

型型番番パパッッケケーージジ本本体体ササイイズズ（（公公称称））

INA128、INA129

SOIC (8) 3.91mm×4.90mmPDIP (8) 6.35mm×9.81mm

(1) 利用可能なすべてのパッケージについては、このデータシートの末尾にあるパッケージ・オプションについての付録を参照してください。

概概略略回回路路図図

http://www-s.ti.com/sc/techlit/SBOS051.pdf

http://www.tij.co.jp/product/jp/ina128?qgpn=ina128


http://www.tij.co.jp/tool/jp/TIPD191?dcmp=dsproject&hqs=rd

http://www.ti.com/product/INA828

http://www.ti.com/product/INA828

このデバイスには新しいバージョン INA828 が存在します

2

INA128, INA129JAJSEJ5E –OCTOBER 1995–REVISED APRIL 2019 www.ti.com

Copyright © 1995–2019, Texas Instruments Incorporated

目目次次1 特特長長.......................................................................... 12 アアププリリケケーーシショョンン ......................................................... 13 概概要要.......................................................................... 14 改改訂訂履履歴歴................................................................... 25 Device Comparison Table ..................................... 36 Pin Configuration and Functions ......................... 47 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 47.2 ESD Ratings.............................................................. 47.3 Recommended Operating Conditions....................... 57.4 Thermal Information .................................................. 57.5 Electrical Characteristics........................................... 57.6 Typical Characteristics .............................................. 8

8 Detailed Description ............................................ 128.1 Overview ................................................................. 128.2 Functional Block Diagram ....................................... 128.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 139 Application and Implementation ........................ 14

9.1 Application Information............................................ 149.2 Typical Application ................................................. 14

10 Power Supply Recommendations ..................... 1810.1 Low Voltage Operation ......................................... 18

11 Layout................................................................... 2011.1 Layout Guidelines ................................................. 2011.2 Layout Example .................................................... 20

12 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト ....................... 2112.1 関連リンク ............................................................... 2112.2 ドキュメントの更新通知を受け取る方法..................... 2112.3 コミュニティ・リソース ................................................ 2112.4 商標 ....................................................................... 2112.5 静電気放電に関する注意事項 ................................ 2112.6 Glossary ................................................................ 21

13 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報 ................. 21

4 改改訂訂履履歴歴資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。

Revision D (January 2018) かからら Revision E にに変変更更 Page

• 新しいアップグレードされた INA828 の情報を追加 ................................................................................................................... 1• Added Device Comparison Table .......................................................................................................................................... 3

Revision C (October 2015) かからら Revision D にに変変更更 Page

• TI リファレンス・デザインのナビゲータ・アイコンを上端に追加 .................................................................................................... 1• Changed "±0.5±0/G" to "±0.5±20/G" in MAX column of Offset voltage RTI vs temperature row of Electrical

Characteristics ........................................................................................................................................................................ 5

Revision B (February 2005) かからら Revision C にに変変更更 Page

• 「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 ....................................................................................................................................... 1

http://www.ti.com/product/ina128?qgpn=ina128


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3

INA128, INA129www.ti.com JAJSEJ5E –OCTOBER 1995–REVISED APRIL 2019


5 Device Comparison Table

DEVICE DESCRIPTION GAIN EQUATION RG PINS AT PIN

INA828 50-µV Offset, 0.5 µV/°C VOS drift, 7-nV/√Hz Noise, Low-Power,Precision Instrumentation Amplifier G = 1 + 50 kΩ / RG 1, 8


INA821 35-µV Offset, 0.4 µV/°C VOS drift, 7-nV/√Hz Noise, High-Bandwidth, Precision Instrumentation Amplifier G = 1 + 49.4 kΩ / RG 2, 3


INA333 25-µV VOS, 0.1 µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ,chopper-stabilized INA G = 1 + 100 kΩ / RG 1, 8

PGA280 20-mV to ±10-V programmable gain IA with 3-V or 5-V differentialoutput; analog supply up to ±18 V digital programmable N/A

INA159 G = 0.2 V differential amplifier for ±10-V to 3-V and 5-Vconversion G = 0.2 V/V N/A

PGA112 Precision programmable gain op amp with SPI digital programmable N/A



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http://www.ti.com/product/ina828





http://www.ti.com/product/pga280


http://www.ti.com/product/pga112

R

V

G

−

IN

V+IN

V

R

−

G

V+

VO

Ref

1

2

3

4

8

7

6

5


4



6 Pin Configuration and Functions

D and P Packages8-Pin SOIC and PDIP

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.REF 5 I Reference input. This pin must be driven by low impedance or connected to ground.RG 1,8 — Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8.V- 4 — Negative supplyV+ 7 — Positive supplyVIN- 2 I Negative inputVIN+ 3 I Positive inputVO 6 I Output

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITSupply voltage ±18 VAnalog input voltage ±40 VOutput short circuit (to ground) continuousOperating temperature –40 125 °CJunction temperature 150 °CLead temperature (soldering, 10 seconds) 300 °CStorage temperature, Tstg –55 125 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD RatingsVALUE UNIT

V(ESD)Electrostaticdischarge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000V

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±50



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5



7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITV power supply ±2.25 ±15 ±18 VInput common-mode voltage range for VO = 0 V – 2 V V + –2 VTA operating temperature INA128-HT –55 175 °CTA operating temperature INA129-HT –55 210 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

7.4 Thermal Information

THERMAL METRIC (1)INA12x

UNITD (SOIC) P (PDIP)8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 110 46.1 °C/WRθJC(top) Junction-to-case (top) thermal resistance 57 34.1 °C/WRθJB Junction-to-board thermal resistance 54 23.4 °C/WψJT Junction-to-top characterization parameter 11 11.3 °C/WψJB Junction-to-board characterization parameter 53 23.2 °C/W

(1) Input common-mode range varies with output voltage; see Typical Characteristics.

7.5 Electrical Characteristicsat TA = 25°C, VS = ±15 V, and RL = 10 kΩ (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT

Offsetvoltage, RTI

Initial TA = 25°C

INA128P, UINA129P, U ±10±100/G ±50±500/G

µVINA128PA, UAINA129PA, UA ±25±100/G ±125±1000/G

vs temperature TA = TMIN to TMAX

INA128P, UINA129P, U ±0.2±2/G ±0.5±20/G

µV/°CINA128PA, UAINA129PA, UA ±0.2±5/G ±1±20/G

vs power supply VS = ±2.25 V to±18 V

INA128P, UINA129P, U ±0.2±20/G ±1±100/G

µV/VINA128PA, UAINA129PA, UA ±2±200/G

Long-term stability ±0.1±3/g µV/mo

ImpedanceDifferential 1010 || 2

Ω || pFCommon mode 1011 || 9

Common-mode voltage range (1) VO = 0 V(V+) - 2 (V+) - 1.4

V(V…) + 2 (V–) + 1.7

Safe input voltage ±40 V



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http://www.ti.com/lit/pdf/SPRA953

http://www.ti.com/lit/pdf/SPRA953


6



Electrical Characteristics (continued)at TA = 25°C, VS = ±15 V, and RL = 10 kΩ (unless otherwise noted)


(2) Nonlinearity measurements in G = 1000 are dominated by noise. Typical non-linearity is ±0.001%.

Common-mode rejection VCM = ±13 V, ΔRS= 1 kΩ

G = 1

INA128P, UINA129P, U 80 86

dB

INA128PA, UAINA129PA, UA 73

G = 10

INA128P, UINA129P, U 100 106


G = 100

INA128P, UINA129P, U 120 125


G = 1000

INA128P, UINA129P, U 120 130


Bias current

INA128P, UINA129P, U ±2 ±5

nAINA128PA, UAINA129PA, UA ±10

Bias current vs temperature ±30 pA/°C

Offset current

INA128P, UINA129P, U ±1 ±5

nAINA128PA, UAINA129PA, UA ±10

Offset current vs temperature ±30 pA/°C

Noisevoltage, RTI

f = 10 Hz

G = 1000, RS = 0Ω

10

nV/√Hzf = 100 Hz 8

f = 1 kHz 8

fB = 0.1 Hz to 10 Hz 0.2 µVPP

Noise current

f = 10 Hz 0.9pA/√Hz

f = 1 kHz 0.3

FB = 0.1 Hz to 10 Hz 30 pAPP

GAIN (2)

Gain equationINA128 1 + (50 kΩ/RG)

V/VINA129 1 + (49.4 kΩ/RG)

Range of gain 1 10000 V/V

Gain error

G = 1

INA128P, UINA129P, U ±0.01% ±0.024%

INA128PA, UAINA129PA, UA ±0.01%

G = 10

INA128P, UINA129P, U ±0.02% ±0.4%


G = 100

INA128P, UINA129P, U ±0.05% ±0.5%


G = 1000

INA128P, UINA129P, U ±0.5% ±1%

INA128PA, UAINA129PA, UA ±2%



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7



Electrical Characteristics (continued)at TA = 25°C, VS = ±15 V, and RL = 10 kΩ (unless otherwise noted)


(3) Specified by wafer test.(4) Temperature coefficient of the 50 kΩ (or 49.4 kΩ) term in the gain equation.

Gain vs temperature (3) G = 1 ±1 ±10ppm/°C

50-kΩ (or 49.4-kΩ) Resistance (3) (4) ±25 ±100

Nonlinearity

VO = ±13.6 V, G = 1

INA128P, UINA129P, U ±0.0001 ±0.001

% of FSR

INA128PA, UAINA129PA, UA ±0.002

G = 10

INA128P, UINA129P, U ±0.0003 ±0.002


G = 100

INA128P, UINA129P, U ±0.0005 ±0.002


G = 1000 ±0.001 />

OUTPUT (2)

VoltagePositive RL = 10 kΩ (V+) – 1.4 (V+) – 0.9

VNegative RL = 10 kΩ (V–) + 1.4 (V–) + 0.8

Load capacitance stability 1000 pF

Short-circuit current 6/–15 mA

FREQUENCY RESPONSE

Bandwidth, –3 dB

G = 1 1.3 MHz

G = 10 700

kHzG = 100 200

G = 1000 20

Slew rate VO = ±10 V, G = 10 4 V/µs

Settling time, 0.01%

G = 1 7

µsG = 10 7

G = 100 9

G = 1000 80

Overload recovery 50% overdrive 4 µs

POWER SUPPLY

Voltage range ±2.25 ±15 ±18 V

Current, total VIN = 0 V ±700 ±750 µA

TEMPERATURE RANGE

Specification –40 85 °C

Operating –40 125 °C



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Output Voltage (V)

Co

mm

on

−M

ode

Vo

ltage

(V)

0 5 15

15

10

5

0

10

G = 1 G = 1

G ≥ 10 G ≥ 10

VD/2+

+

VCM

VV

OD/2 Ref

15V

+15V

+

−5−10−15

−

−

−−5

−10

−15

Output Voltage (V)

Co

mm

on

−M

ode

Voltage

(V)

5

4

3

2

1

0

0 1 2 3 4 5

G = 1 G = 1

G ≥ 10 G ≥ 10

G ≥ 10

G = 1

−1

−2

−3

−4

−5

−1−2−3−4−5

VS = ±2.5V

VS = ±5V

Frequency (Hz)

Po

wer

Su

pp

lyR

eje

ction

(dB

)

140

120

100

80

60

40

20

0

10 100 1k 10k 100k 1M

G = 100V/V

G = 1000V/V

G = 1V/V

G = 10V/V

Frequency (Hz)

Pow

er

Supp

lyR

eje

ction

(dB

)

140

120

100

80

60

40

20

0

10 100 1k 10k 100k 1M

G = 100V/V

G = 1000V/V

G = 1V/V

G = 10V/V

Frequency (Hz)

Com

mon−

Mo

de

Reje

ction

(dB

)

10 100 10k 1M1k

140

120

100

80

60

40

20

0

100k

G = 1V/V

G = 10V/V

G = 100V/VG = 1000V/V

−

60

50

40

30

20

10

0

10

20

Gain

(dB

)

Frequency (Hz)

1k 10k 100k 1M 10M

G = 100V/V

G = 10V/V

G = 1V/V

G = 1000V/V

−


8



7.6 Typical Characteristicsat TA = 25°C and VS = ±15 V (unless otherwise noted)

Figure 1. Gain vs Frequency Figure 2. Common-Mode Rejection vs Frequency

Figure 3. Positive Power Supply Rejection vs Frequency Figure 4. Negative Power Supply Rejection vs Frequency

Figure 5. Input Common-Mode Range vs Output Voltage,VS = ±15 V

Figure 6. Input Common-Mode Range vs Output Voltage,VS = ±5 V, ±2.5 V



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2

1

0

0 25 50 75 100 125

Inp

utB

ias

Curr

ent(n

A)

IOS

IB

−25−50−75

−1

−2

Temperature (°C)

Typical IB and IOSRange ±2nA at 25°C

10

8

6

4

2

0

0 100 200 300 400 500

−2

−4

−6

−8

−10

Time (µs)

OffsetV

oltage

Change

(µV

)

5

4

3

2

1

0

Inp

ut

Curr

ent(m

A)

Input Voltage (V)

10 20 30 400 50

G = 1V/V

G = 1V/V

G = 1000V/V

G = 1000V/V VINIIN

+15V

Flat region represents

normal linear operation.

−1

−2

−3

−4

−5

−10−20−30−40−50

−15V

0.85

0.8

0.75

0.7

0.65

0 6

6

5

4

3

2

1

0 25 50 75 100 125

IQ

Slew Rate

−75 −50 −25

Temperature (°C)

Quie

scent C

urr

ent (µ

A)

Sle

w R

ate

(V

/µs)

Frequency (Hz)

1 10 1k100

1k

100

10

1

10k

G = 1V/V

G = 10V/V

100

10

1

0.1

Current Noise

G = 100, 1000V/V

InputB

ias

Curr

entN

ois

e(p

A/

)

Input-

Refe

rred

Voltage

Nois

e(n

V/√

Hz)

Gain (V/V)

Se

ttling

Tim

e(m

s)

100

10

1

1 10 100 1000

0.01%

0.1%


9



Typical Characteristics (continued)at TA = 25°C and VS = ±15 V (unless otherwise noted)

Figure 7. Input-Referred Noise vs Frequency Figure 8. Settling Time vs Gain

Figure 9. Quiescent Current and Slew Rate vs Temperature Figure 10. Input Overvoltage V/I Characteristics

Figure 11. Input Offset Voltage Warm-Up Figure 12. Input Bias Current vs Temperature



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Frequency (Hz)

TH

D+

N(%

)

100 1k 10k

1

0.1

0.01

0.001

100k

VO = 1VrmsG = 1

RL = 10kΩ

G = 10V/V

RL = 100kΩ

G = 100, RL = 100kΩ

G = 1, RL = 100kΩ

500kHz MeasurementBandwidth

Dashed Portionis noise limited.

G = 1

20mV/div

G = 10

5µs/div

Frequency (Hz)

Pe

ak−

to−

Peak

Outp

ut

Voltage

(VP

P)

30

25

20

15

10

5

0

1k 10k 100k 1M

G = 1

G = 10, 100

G = 1000

18

16

14

12

10

8

6

4

2

0

0 25 50 75 100 125

Sh

ort

−C

ircu

itC

urr

ent

(mA

)

−25−50−75

Temperature (°C)

−ISC

+ISC

(V−)+1.2

(V−)

(V+)

(V+)−0.4

(V+)−0.8

(V+)−1.2

(V−)+0.8

(V−)+0.4

0 5 10 15 20

Power Supply Voltage (V)

Outp

ut

Vo

ltage

Sw

ing

(V)

RL = 10kΩ

−40°C

+85°C

+25°C−40°C

+85°C

−40°C

+25°C

+85°C

(V−)+1.2

(V−)

(V+)

0 1 2 3 4

Output Current (mA)

Ou

tputV

olta

ge

(V)

(V+)−0.4

(V+)−0.8

(V+)−1.2

(V−)+0.8

(V−)+0.4

(V−)+1.2

(V−)

(V+)

(V+)−0.4

(V+)−0.8

(V+)−1.2

(V−)+0.8

(V−)+0.4

Outp

ut

Vo

ltage

Sw

ing

(V)


10




Figure 13. Output Voltage Swing vs Output Current Figure 14. Output Voltage Swing vs Power Supply Voltage

Figure 15. Short Circuit Output Current vs Temperature Figure 16. Maximum Output Voltage vs Frequency

Figure 17. Total Harmonic Distortion + Noise vs Frequency Figure 18. Small Signal (G = 1, 10)



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G = 100

5V/div

G = 1000

20µs/div 1s/div

0.1µV/div

G = 100

20mV/div

G = 1000

20µs/div

G = 1

5V/div

G = 10

5µs/div


11




Figure 19. Small Signal (G = 100, 1000) Figure 20. Large Signal (G = 1, 10)

Figure 21. Large Signal (G = 100, 1000) Figure 22. Voltage Noise 0.1 to 10-Hz Input-Referred, G ≥100



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A1

A2

A3

40 kW40 kW

40 kW40 kW

VIN

2

1

8

3

6

5

VIN

RG

V+

V-

Ref

VO

G = 1 +49.4 kW

RG

+

4

7

INA128, INA129

Over-Voltage

Protection

Over-Voltage

Protection

-

25 kW

(1)

25 kW

(1)

NOTE: (1) INA129: 24.7 kW

G = 1 +50 kW

RG

INA128:

INA129:


12



8 Detailed Description

8.1 OverviewThe INA12x instrumentation amplifier is a type of differential amplifier that has been outfitted with input protectioncircuit and input buffer amplifiers, which eliminate the need for input impedance matching and make the amplifierparticularly suitable for use in measurement and test equipment. Additional characteristics of the INA128 includea very low DC offset, low drift, low noise, very high open-loop gain, very high common-mode rejection ratio, andvery high input impedances. The INA12x is used where great accuracy and stability of the circuit both short andlong term are required.

8.2 Functional Block Diagram

8.3 Feature DescriptionThe INA12x devices are low power, general-purpose instrumentation amplifiers offering excellent accuracy. Theversatile three-operational-amplifier design and small size make the amplifiers ideal for a wide range ofapplications. Current-feedback input circuitry provides wide bandwidth, even at high gain. A single externalresistor sets any gain from 1 to 10,000. The INA128 is laser trimmed for very low offset voltage (25 μV typical)and high common-mode rejection (93 dB at G ≥ 100). These devices operate with power supplies as low as±2.25 V, and quiescent current of 2 mA, typically. The internal input protection can withstand up to ±40 V withoutdamage.



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1s/div

0.1 V/divm


13



8.4 Device Functional Modes

8.4.1 Noise PerformanceThe INA12x provides very low noise in most applications. Low-frequency noise is approximately 0.2 µVPPmeasured from 0.1 to 10 Hz (G ≥ 100). This provides dramatically improved noise when compared to state-of-the-art chopper-stabilized amplifiers.

G ≥ 100

Figure 23. 0.1-Hz to 10-Hz Input-Referred Voltage Noise

8.4.2 Input Common-Mode RangeThe linear input voltage range of the input circuitry of the INA12x is from approximately 1.4 V below the positivesupply voltage to 1.7 V above the negative supply. As a differential input voltage causes the output voltageincrease, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2. Thus thelinear common-mode input range is related to the output voltage of the complete amplifier. This behavior alsodepends on supply voltage (see performance curve Figure 6).

Input-overload can produce an output voltage that appears normal. For example, if an input overload conditiondrives both input amplifiers to their positive output swing limit, the difference voltage measured by the outputamplifier will be near zero. The output of A3 will be near 0 V even though both inputs are overloaded.



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RGAlso drawn in simplified form: INA128

Ref

VO

VIN

VIN+

−

G 150k

RGG 1

49.4k

RG

INA128: INA129:

DESIRED R NEAREST R NEARESTG GGAIN (V/V) (Ω) 1% RG (Ω) (Ω) 1% RG (Ω

1 NC NC NC NC2 50.00k 49.9k 49.4k 49.9k5 12.50k 12.4k 12.35k 12.4k10 5.556k 5.62k 5489 5.49k20 2.632k 2.61k 2600 2.61k50 1.02k 1.02k 1008 1k100 505.1 511 499 499200 251.3 249 248 249500 100.2 100 99 1001000 50.05 49.9 49.5 49.92000 25.01 24.9 24.7 24.95000 10.00 10 9.88 9.7610000 5.001 4.99 4.94 4.87

INA128 INA129

NC: No Connection

A1

A2

A3

6

7

4

3

8

1

2VIN

VIN

RG

V+

INA128, INA129

+

5

Over−Voltage

Protection

Over−Voltage

Protection

Load

+

OV

Ref

NOTE: (1) INA129: 24.7kΩ

−

0.1µF

0.1µF

V−

−

25kΩ(1)

25kΩ(1)

40kΩ 40kΩ

40kΩ 40kΩ

VO = G (VIN− VIN

+ −• )


14



9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe INA12x measures small differential voltage with high common-mode voltage developed between thenoninverting and inverting input. The high-input voltage protection circuit in conjunction with high inputimpedance make the INA12x suitable for a wide range of applications. The ability to set the reference pin toadjust the functionality of the output signal offers additional flexibility that is practical for multiple configurations.

9.2 Typical ApplicationFigure 24 shows the basic connections required for operation of the INA12x. Applications with noisy or highimpedance power supplies may require decoupling capacitors close to the device pins as shown. The output isreferred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedanceconnection to assure good common-mode rejection. A resistance of 8 Ω in series with the Ref pin will cause atypical device to degrade to approximately 80dB CMR (G = 1).

Figure 24. Basic Connections



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10kΩOPA177100Ω

100Ω

1/2 REF200

1/2 REF200

V+

RG INA128

Ref

VO

VIN

VIN+

−

±10mV

Adjustment Range

V−

100µA

100µA


15



Typical Application (continued)9.2.1 Design RequirementsThe device can be configured to monitor the input differential voltage when the gain of the input signal is set bythe external resistor RG. The output signal references to the Ref pin. The most common application is where theoutput is referenced to ground when no input signal is present by connecting the Ref pin to ground, as Figure 24shows. When the input signal increases, the output voltage at the OUT pin increases, too.

9.2.2 Detailed Design Procedure

9.2.2.1 Setting the GainGain is set by connecting a single external resistor, RG, connected between pins 1 and 8:

INA128: g = 1 + 50 kΩ/RG (1)

Commonly used gains and resistor values are shown in Figure 24.

The 50-kΩ term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-chip metal film resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficientof these internal resistors are included in the gain accuracy and drift specifications of the INA128.

The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution ofRG to gain accuracy and drift can be directly inferred from Equation 1. Low resistor values required for high gaincan make wiring resistance important. Sockets add to the wiring resistance, which contributes additional gainerror (possibly an unstable gain error) in gains of approximately 100 or greater.

9.2.2.2 Dynamic PerformanceThe typical performance curve Figure 1 shows that, despite its low quiescent current, the INA12x achieves widebandwidth even at high gain. This is due to the current-feedback topology of the input stage circuitry. Settlingtime also remains excellent at high gain.

9.2.2.3 Offset TrimmingThe INA12x is laser-trimmed for low-offset voltage and offset voltage drift. Most applications require no externaloffset adjustment. Figure 25 shows an optional circuit for trimming the output offset voltage. The voltage appliedto the Ref terminal is summed with the output. The op amp buffer provides low impedance at the Ref terminal topreserve good common-mode rejection.

Figure 25. Optional Trimming of Output Offset Voltage

9.2.2.4 Input Bias Current Return PathThe input impedance of the INA12x is extremely high: approximately 1010 Ω. However, a path must be providedfor the input bias current of both inputs. This input bias current is approximately ±2 nA. High input impedancemeans that this input bias current changes very little with varying input voltage.



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47kΩ47kΩ

10kΩ

Microphone,

Hydrophone

etc.

Thermocouple

Center−tap provides

bias current return.

INA128

INA128

INA128


16



Typical Application (continued)Input circuitry must provide a path for this input bias current for proper operation. Figure 26 shows variousprovisions for an input bias current path. Without a bias current path, the inputs will float to a potential whichexceeds the common-mode range, and the input amplifiers will saturate.

If the differential source resistance is low, the bias current return path can be connected to one input (see thethermocouple example in Figure 26). With higher source impedance, using two equal resistors provides abalanced input, with possible advantages of lower input offset voltage due to bias current and better high-frequency common-mode rejection.

Figure 26. Providing an Input Common-Mode Current Path



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G = 1

5V/div

G = 10

5 s/divm

5V/div

G =1000

20 s/divm

G =100

G = 1

20mV/div

G = 10

5 s/divm

G = 10 0

20mV/div

G = 10 0 0

20 s/divm


17



Typical Application (continued)9.2.3 Application Curves

G = 1, 10

Figure 27. Small Signal

G = 100, 1000

Figure 28. Small Signal

G = 1, 10

Figure 29. Large Signal

G = 100, 1000

Figure 30. Large Signal



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INA128RG

VO

OPA130

Ref R1

1MΩ

=1

2πR C1 1

= 1.59Hz

VIN

+

f−3dB

C10.1µF

−

300Ω

+5V

RG INA128 V

O

Ref

2.5V − ∆V

2.5V + ∆V


18



10 Power Supply RecommendationsThe minimum power supply voltage for INA12x is ±2.25 V and the maximum power supply voltage is ±18 V. Thisminimum and maximum range covers a wide range of power supplies; but for optimum performance, ±15 V isrecommended. TI recommends adding a bypass capacitor at the input to compensate for the layout and powersupply source impedance.

10.1 Low Voltage OperationThe INA12x can be operated on power supplies as low as ±2.25 V. Performance remains excellent with powersupplies ranging from ±2.25 V to ±18 V. Most parameters vary only slightly throughout this supply voltagerange—see Typical Characteristics.

Operation at very low supply voltage requires careful attention to assure that the input voltages remain withintheir linear range. Voltage swing requirements of internal nodes limit the input common-mode range with lowpower supply voltage. Figure 6 shows the range of linear operation for ±15-V, ±5-V, and ±2.5-V supplies.

Figure 31. Bridge Amplifier

Figure 32. AC-Coupled Instrumentation Amplifier



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INA128RG

IB

R

V

1

IN

+

A1 IO

Load

Ref

IO

V IN

R1

G−

A I1 B ERROR

OPA177 ± 1.5nA

OPA131 ± 50pA

OPA602 ± 1pA

OPA128 ± 75fA

REF102

R2R1

Pt100

Cu

Cu

V+

K

610.0V

4

2

INA128VO

Ref

R

R3

G

100Ω = Pt100 at 0°C

SEEBECKISA COEFFICIENT

TYPE MATERIAL (V/µ C) R1, R2

E + Chromel 58.5 66.5kΩ− Constantan

J + Iron 50.2 76.8kΩ− Constantan

K + Chromel 39.4 97.6kΩ

− AlumelT + Copper 38.0 102kΩ

− Constantan


19



Low Voltage Operation (continued)

Figure 33. Thermocouple Amplifier With RTD Cold-Junction Compensation

Figure 34. Differential Voltage to Current Converter



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BypassCapacitor

BypassCapacitor

Gain Resistor

R6

VIH–

V +IH

V–

R6

V+

VO

REF

–

+

V+

VOUT

GND

VIN

VIN

GNDV–

INA128RG/2

RG = 5.6kΩ

VOLA

RL

RA

10kΩ

Ref

G = 10

2.8kΩ

VV

GG

2.8kΩ

1/2

OPA2131

390kΩ

390kΩ

1/2

OPA2131 NOTE: Due to the INA128’s current-feedback

topology, VG is approximately 0.7V less than

the common-mode input voltage. This DC offset

in this guard potential is satisfactory for many

guarding applications.


20

INA128, INA129JAJSEJ5E –OCTOBER 1995–REVISED APRIL 2019 www.tij.co.jp


Low Voltage Operation (continued)

Figure 35. ECG Amplifier With Right-Leg Drive

11 Layout

11.1 Layout GuidelinesPlace the power-supply bypass capacitor as closely as possible to the supply and ground pins. Therecommended value of this bypass capacitor is 0.1 μF to 1 μF. If necessary, additional decoupling capacitancecan be added to compensate for noisy or high-impedance power supplies. These decoupling capacitors must beplaced between the power supply and INA12x devices.

The gain resistor must be placed close to pin 1 and pin 8. This placement limits the layout loop and minimizesany noise coupling into the part.

11.2 Layout Example

Figure 36. Recommended Layout



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21

INA128, INA129www.tij.co.jp JAJSEJ5E –OCTOBER 1995–REVISED APRIL 2019


12 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト

12.1 関関連連リリンンクク表 1 に、クイック・アクセス・リンクの一覧を示します。カテゴリには、技術資料、サポートおよびコミュニティ・リソース、ツールとソフトウェア、およびサンプル注文またはご購入へのクイック・アクセスが含まれます。

表表 1. 関関連連リリンンクク製製品品ププロロダダククトト・・フフォォルルダダササンンププルルととごご購購入入技技術術資資料料ツツーールルととソソフフトトウウェェアアササポポーートトととココミミュュニニテティィ

INA128 ここをクリックここをクリックここをクリックここをクリックここをクリック

INA129 ここをクリックここをクリックここをクリックここをクリックここをクリック

12.2 ドドキキュュメメンントトのの更更新新通通知知をを受受けけ取取るる方方法法ドキュメントの更新についての通知を受け取るには、ti.comのデバイス製品フォルダを開いてください。右上の「アラートを受け取る」をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取れます。変更の詳細については、修正されたドキュメントに含まれている改訂履歴をご覧ください。

12.3 ココミミュュニニテティィ・・リリソソーーススThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.4 商商標標E2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.5 静静電電気気放放電電にに関関すするる注注意意事事項項これらのデバイスは、限定的なESD（静電破壊）保護機能を内蔵しています。保存時または取り扱い時は、MOSゲートに対する静電破壊を防止するために、リード線同士をショートさせておくか、デバイスを導電フォームに入れる必要があります。

12.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。この情報は、そのデバイスについて利用可能な最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もあります。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。



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重重要要ななおお知知ららせせとと免免責責事事項項

TI は、技術データと信頼性データ（データシートを含みます）、設計リソース（リファレンス・デザインを含みます）、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。

これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

INA128P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type INA128P

INA128PA ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type INA128PA

INA128PG4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type INA128P

INA128U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR INA128U

INA128U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR INA128U

INA128U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR INA128U

INA128UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA128UA

INA128UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA128UA

INA128UA/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA128UA

INA128UA/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA128UA

INA128UAE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA128UA

INA128UAG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA128UA

INA128UG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR INA128U

INA129P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type INA129P

INA129PA ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type INA129P

http://www.ti.com/product/INA128?CMP=conv-poasamples#samplebuy

















Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

A

INA129PG4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type INA129P

INA129U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR INA129U

INA129U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR INA129U

INA129UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA129UA

INA129UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA129UA

INA129UA/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA129UA

INA129UAE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 INA129UA

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.










Addendum-Page 3

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

INA128U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

INA128UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

INA129U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

INA129UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

INA128U/2K5 SOIC D 8 2500 853.0 449.0 35.0

INA128UA/2K5 SOIC D 8 2500 853.0 449.0 35.0

INA129U/2K5 SOIC D 8 2500 367.0 367.0 35.0

INA129UA/2K5 SOIC D 8 2500 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 2

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PACKAGE OUTLINE

C

.228-.244 TYP[5.80-6.19]

.069 MAX[1.75]

6X .050[1.27]

8X .012-.020 [0.31-0.51]

2X.150[3.81]

.005-.010 TYP[0.13-0.25]

0 - 8 .004-.010[0.11-0.25]

.010[0.25]

.016-.050[0.41-1.27]

4X (0 -15 )

A

.189-.197[4.81-5.00]

NOTE 3

B .150-.157[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)[1.04]

SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.

18

.010 [0.25] C A B

54

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX[0.07]ALL AROUND

.0028 MIN[0.07]ALL AROUND

(.213)[5.4]

6X (.050 )[1.27]

8X (.061 )[1.55]

8X (.024)[0.6]

(R.002 ) TYP[0.05]


4214825/C 02/2019

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

EXPOSEDMETAL

OPENINGSOLDER MASK METAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSEDMETAL

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:8X

SYMM

1

45

8

SEEDETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )[1.55]

8X (.024)[0.6]

6X (.050 )[1.27]

(.213)[5.4]

(R.002 ) TYP[0.05]


4214825/C 02/2019

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

SYMM

1

45

8

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