EE5342 – Semiconductor Device Modeling and Characterization Lecture 28 April 28, 2010
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Transcript of EE5342 – Semiconductor Device Modeling and Characterization Lecture 28 April 28, 2010
EE5342 – Semiconductor Device
Modeling and Characterization
Lecture 28April 28, 2010
Professor Ronald L. [email protected]
http://www.uta.edu/ronc/
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Introduction• Self heating of the transistor is
proportional to the power dissipated.• Temperature Rise = ΔT = Rth ∙Power• The VBIC model was developed to
simulate the BJT such that the device temperature tracked power dissipation in real time.
• Other circuit simulators which accommodate thermal resistance are– HICUM– MEXTRAM
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Rth Estimation for a Small Diode-isolated BJT Device
VBE=0.87 V and VCE=20 V, RTH = 341 C/W
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dt
tl
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VBIC Model HighlightsSelf-heating effects
includedImproved Early effect
modelingQuasi-saturation
modelingParasitic substrate
transistor modeling
Parasitic fixed (oxide) capacitance modeling
An avalanche multiplication model included
Base current is decoupled from collector current
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2-D Isotherm Plot- Lines Connecting Points of Equal Temperature
2-D Isotherm plots for a structure scaled to be the same as the P10 1X2X1 device.
• The structure of a typical SiGe HBT (Heterojunction Bipolar Transistor) [1]
• The Electrical circuit topology (Cauer network) for the thermal analogy model
Thermal Model of a SiGe HBT
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Oxide
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One Dimensional Heat Flow in Silicon
• A silicon structure can be sub-divided into several silicon slabs.
• Each section contributes to the total Rth and Cth of the structure. If each section is of equal volume, their individual Rth and Cth should be equal in value.
• To correspond to uniform heat flow, each section can be represented by a thermal resistance and half the total capacitance on each node of the resistor. Cth
2
Rth
Cth 2
AMBIENT
HEAT
SILI
CON
SILI
CON
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The Distributed Nature of the Heat Flow
• The corresponding CTh /2 capacitors are aggregated at each node.
• Note that the “ambient end” CTh /2 is short-circuited. • The distributed equivalent circuit analogy simulation
is obtained from the following network.Rth n
Cth 2n
Rth n
Cth n
Cth n
Rth n
Rth n
Cth n
Rth = Total Thermal resistance for the silicon structureCth= Total Thermal capacitance of the silicon structuren = number of sections
AtpcρCth
ApktRth
t= thicknesskp= thermal conductance
A=areacp= thermal capacitanceρ=density
Comparison of Circuit Analogy to Davinci Simulation of the Heat Flow
Considering a silicon structure of size 3.7umx2.5um x10um
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1.26uCthRthTau18.2nAtpcρCth 6989Apk
tRth
Dividing the structure into 10 sections.
nCth
iCthn
RthiRth where i=1,2,3…n,
n= number of sections
Dotted line=Davinci simulation measurementSolid line = equivalent circuit simulation
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• Converting the 10 element distributed model to a 1 pole model:RTotal=Rth at ‘dc’ΔQTotal =(cp)(ρ)Tavg
For total heat consumption. 2
CC
is limit the ,n For
CVCV
Th1pole
n
1iii1pole1pole
th1
thith RR1R
n
ipole
Heat stored corresponds to charge stored for the equivalent circuit.
Approximating the Distributed Circuit With a Single Pole Model
Rth n
Cth 2n
Rth n
Cth n
Cth n
Rth n
Rth n
Cth n
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Comparison of Circuit Analogy to Davinci Simulation for Heat Flow
1E-08 1E-07 1E-06 1E-05 1E-04 1E-031E+01
1E+02
1E+03
1E+04
1E+05
30um slab davinci
30um slab circuit simulation
20um slab davinci
20um slab simulation
10um slab davinci
10um slab simulation
Time
RTh(
W/K
)
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1E-07 1E-06 1E-05 1E-04 1E-031E+02
1E+03
1E+04
Time
Rth(
k/W
)
Results from equivalent circuit simulationsResults from Davinci Simulation
Results from device measurement Foster networkResults from device measurement Cauer network
Top of the tubTop of the oxideTop of the wafer
(cont’d)
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Circuit used for simulations
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dt for VBIC-R1.5 model• Model: VBIC-R1.5.
• “selft” flag set to 1.
• No optimization done.
• No external circuit connected.
• Rth=5.8E+0
• Cth=96E-12L28 04/28/10
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VBIC-R1.5 Y11 plot (standard data)
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VBIC-R1.5 Y11 plot (standard data)
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VBIC-R1.2 Y11 plot (optimized data)
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• For optimized data refer slide “Model Parameters”.
• Circuit used is shown in “Circuit for Y parameters (optimized data)” slide. fc Τ
fc1= 2E3 7.962E-05fc2=
9.25E4 1.721E-06fc3= 3.2E6 4.976E-08
Fc4=2E3 7.962E-05Fc5=1E5 1.592E-06Fc6=4E6 3.981E-08fc7= 2E3 7.962E-05fc8= 1E5 1.592E-06fc9=4E6 3.981E-08L28 04/28/10
Spreadsheet for Calculating the Rth and Cth• Calculations mentioned in the previous slides have
been implemented in an Excel spreadsheet.• The Cauer to Foster network transformation is done.
• The spreadsheet takes the dimensions of different layers of the devices and gives corresponding Cauer and Foster network values. This enables the calculation of time constants which can be converted into a single pole. The characteristic times for the Foster network appear on a impulse response plot.L28 04/28/10 18
Fig. 7. Electrical equivalent Cauer network of the HBT Fig. 8. Electrical equivalent Foster network of the HBT
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Effect of Rth on current feedback op-amp settling time
-
+
vIN = 1 V P-P, t = 200 m-sec
500 W
500 W
vOUT
100 W
max,IN
OUTmax,OUT
AvtvvOffset
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y = 0.0055e-0.1416x
Offset = 0.16%Tau = 7.1 u-sec
y = 0.0039e-0.0749x
Offset = .39%Tau = 13.4 u-sec
0.01%
0.10%
1.00%
0 5 10 15 20 25 30Time after switching (u-sec)
Ther
mal
sw
itchi
ng o
ffset
as
%
of V
pCurrent Feedback Op Amp Data
(LMH6704) Switching Offset3.3/t4.13/t e%16.0e%39.0model cfoa
3.34.13/%39.07.7/%55.0%16.0Tau
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LMH6550 impulse thermal characteristics
• LeCroy sampling oscilloscope (1MW input mode)
• Maximum averaging (10000)• Input nominally +/- 1V with 50 micro-
sec period and 50% duty cycle.• Fractional Gain Error = FGE
1v
v)t(v
)t(vFGE
max,INmax,OUT
INOUT
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vIN Rising Response
y = 0.0362e-111568x
R2 = 0.9707,Tau = 9 micro-sec
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-050.10%
1.00%
10.00%
vOUT
vIN
FGE
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y = 0.0373e-148345x
R2 = 0.9257Tau = 6.7 micro-sec
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-050.10%
1.00%
10.00%
vIN Falling Response
vOUT
vIN
FGE
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Current Feedback Op-Amp (CFOA) with Simple Current Mirror (CM) Bias
STICK1
VEE
VEE
VCC
VCC
Q1 Q2
Q3 Q4(stk2-pnp-cm)
Q11 Q12
Q9 Q10 Q17
Q18
Q14
Q13
Q15
Q16
VOZVN
STICK2 STICK3 STICK4 STICK5 STICK6
VEE
VCC
Q6
Q5
Q7(stk3-npn-bf)
Q8(stk3-pnp-bf)
VP
RF
200 μA
+1 V
-1 V
sup
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Large-signal Output Voltage Transient Analysis for CFOA with Simple CM Biasing
0 5 10 15 20 25 30 35 40 45-978
-976
-974
-972
-970
-968
Time (ms)
Vol
tage
(mV
)
0 5 10 15 20 25 30 35 40 45
1020
1022
1024
1026
1028
Time (ms)
Vol
tage
(mV
)
High-to-Low area x1High-to-Low area x8
Low-to-High area x1Low-to-High area x8
TT=-5311 mV
TT=5313 mV
TT=789 mV
TT=-789 mV
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Hypothesis: The Thermal Tail is a Linear Superposition of the Contribution from each Individual Circuit Stick
• The contribution of individual transistor to the total thermal tail.
• Used six stick classifications according to transistor type and functionality. i.e. Q10stk3-pnp-bf and Q11stk4-npn-cm
• Enabled the self-heating effect in the stick of interest and disabled the self-heating effect of the remaining transistors.
• Simulated the contribution of each individual stick.• The total thermal tail simulated is essentially the sum
of the individual thermal tail contributions of each circuit stick.
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The Hypothesis Supported Area x1 Area x8
Thermal Tail (uV/V) High-to-Low Low-to-High High-to-Low Low-to-High
stk2-npn-bf (Q5) -822 842 -124 128
stk2-pnp-bf (Q6) -727 712 -101 98
stk2-npn-cm (Q2) -89 91 -11 12
stk2-pnp-cm (Q4) -91 89 -10 9
stk3-npn-bf (Q7) -877 850 -111 106
stk3-pnp-bf (Q8) -783 808 -111 115
stk4-npn-cm (Q12) -1213 1217 -172 173
stk4-pnp-cm (Q10) -1075 1073 -159 158
stk5-npn-bf(Q13) 13 -13 2 -2
stk5-pnp-bf(Q14) -4 4 -1 1
stk5-npn-cm(Q18) 16 -15 2 -2
stk5-pnp-cm(Q17) -5 2 0 0
stk6-npn-bf(Q15) 0 1 0 0
stk6-pnp-bf(Q16) -1 0 0 0
added total -5658 5661 -796 796
simulated total -5311 5313 -789 789L28 04/28/10
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HeterojunctionElectrostatics
Eo
EC,p
EV,p
EF,pEF,n
EC,n
EV,n
DEC
DEV
qfp
qfn
-xn xp0
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Poisson’s EquationEx
xxp-xn
pA
ppx qN
dxdE
nD
nnx qN
dxdE
n,bix VdxE
n,bix VdxE
0xE0xE0x at eqn Continuity
xpxn
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Heterojunctionelectronics
d
2inonovn,vn,f
n,vn,fn,gnndcn,fc
n,fcnn,fonnpbi
pand
N/np , p/NlnkTEEEEEqq
N/NlnkTEEEEqEEq
VxqNxqN ,neutrality Charge
f
f
ff
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Heterojunctionelectronics (cont)
text. in 8.40 & 8.39 c.f. , N/NlnkTEE
, EEEqq. N/nn , n/NlnkTEE
, EEqEEq
avp,vp,f
p,vp,fp,gpp
a2ipopocp,fc
p,fcpp,fop
f
f
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Heterojunctionelectronics (cont)
form. eappropriat the is this thenE is barrier eappropriat the and
important, is injection hole Since. /Nnp and , Np
, NN
pp
lnkTEqV
8.39 e.g.
v
d2inoapo
n,vn,v
nopo
vbi
D
D
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Heterojunctiondepletion widths
p,apn,dnp,an,dbipn
p
p,apn,dnn,dp,abipn
n
p,apn,dnp,an,d
2p,an,dbipnpn
NNqNNV2
x
NNqNNV2
x
NNNqNNNV2
xxW
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References• Fujiang Lin, et al, “Extraction Of VBIC Model for SiGe
HBTs Made Easy by Going Through Gummel-Poon Model”, from http://eesof.tm.agilent.com/pdf/VBIC_Model_Extraction.pdf
• http://www.fht-esslingen.de/institute/iafgp/neu/VBIC/• Avanti Star-spice User Manual, 04, 2001. • Affirma Spectre Circuit Simulator Device Model
Equations• Zweidinger, D.T.; Fox, R.M., et al, “Equivalent circuit
modeling of static substrate thermal coupling using VCVS representation”, Solid-State Circuits, IEEE Journal of , Volume: 2 Issue: 9 , Sept. 2002, Page(s): 1198 -1206
Thermal Analogy References
[1] I.Z. Mitrovic , O. Buiu, S. Hall, D.M. Bagnall and P. Ashburn “Review of SiGe HBTs on SOI”, Solid State Electronics, Sept. 2005, Vol. 49, pp. 1556-1567.
[2] Masana, F. N., “A New Approach to the Dynamic Thermal Modeling of Semiconductor Packages”, Microelectron. Reliab., 41, 2001, pp. 901–912.
[3] Richard C. Joy and E. S. Schlig, “Thermal Properties of Very Fast Transistors”, IEEE Trans. ED, ED-1 7. No. 8, August 1970, pp. 586-599.
[4] Kevin Bastin, “Analysis and Modeling of self heating in SiGe HBTs” , Aug. 2009, Masters Thesis, UTA.
[5] Rinaldi, N., “On the Modeling of the Transient Thermal Behavior of Semiconductor Devices”, IEEE Trans-ED, Volume: 48 , Issue: 12 , Dec. 2001; Pages:2796 – 2802.
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Simulation … References• [1] E. Castro, S. Coco, A. Laudani, L. LO Nigro and G. Pollicino, “A New Tool For
Bipolar Transistor Characterization Based on HICUM”, Communications to SIMAI Congress, ISSN 1827-9015, Vol. 2, 2007.
• [2] K. Bastin, “Analysis And Modeling of Self Heating in Silicon Germanium Heterojunction Bipolar Transistors”, Thesis report, The University of Texas at Arlington, August 2009.
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AICR Team at University of Texas Arlington - Electrical Engineering
Current• Ronald L. Carter, Professor• W. Alan Davis, Associate
Professor• Howard T. Russell, Senior
Lecturer• Ardasheir Rahman1
• Ratan Pulugurta1
• Xuesong Xie1
• Arun Thomas-Karingada2
• Sharath Patil2• Valay Shah2
Earlier Contributors• Kevin Bastin, MS• Abhijit Chaugule, MS• Daewoo Kim, PhD• Anurag Lakhlani, MS• Zheng Li, PhD• Kamal Sinha, PhD
1PhD Student2MS Student
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