EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141...

25
EE141 Pass Transistor Logic EE141- Spring 2003 Lecture 15 EE141 Announcements Last software lab this week Project readings available online

Transcript of EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141...

Page 1: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

1

EE141

Pass Transistor Logic

EE141- Spring 2003Lecture 15

EE141

Announcements

Last software lab this weekProject readings available online

Page 2: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

2

EE141

Today’s lecture

Logical EffortPass-Transistor Logic

EE141

Logical Effort

+⋅=γ

τ gfpkDelay 0

p – parasitic delay - gate parameter ≠ f(W)g – logical effort – gate parameter ≠ f(W)f – electrical effort (effective fanout)

Normalize everything to an inverter:ginv =1, pinv = 1Everything is measured in unit delays τ0

Page 3: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

3

EE141

Delay in a Logic Gate

Gate delay:

d = h + p

effort delay intrinsic delay

Effort delay:

h = g f

logical effort effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size

EE141

Buffer Example

∑=

⋅+=

N

i

iii

fgpDelay1 γ

pi, gi are constant (and equal to 1)Variables are fiMinimum delay is when fi’s are equal(each stage bears the same effort)

CL

In Out

1 2 N

(in units of τ0)

Page 4: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

4

EE141

Logical Effort

Inverter has the smallest logical effort and intrinsic delay of all static CMOS gatesLogical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same currentLogical effort increases with the gate complexity

EE141

Calculating Logical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current

g = 1 g = 4/3 g = 5/3

B

A

A B

F

VDDVDD

A B

A

B

F

VDD

A

A

F

1

2 2 2

2

21 1

4

4

Inverter 2-input NAND 2-input NOR

Page 5: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

5

EE141

Logical Effort of Gates

Fan-out (f)

Nor

mal

ized

del

ay (d

)t

1 2 3 4 5 6 7

pINVtpNAND

F(Fan-in)

g=1p=1d=f+1

g=4/3p=2d=(4/3)f+2

EE141

Logical Effort of Gates

Intrinsic�Delay

EffortDelay

1 2 3 4 5Fanout f

1

2

3

4

5

Inverter:

g = 1; p = 1

2-inp

ut NAND: g

= 4/3;

p = 2

Nor

mal

ized

Del

ay

Page 6: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

6

EE141

Logical Effort

From Sutherland, Sproull

EE141

Add Branching Effort

Branching effort:

pathon

pathoffpathonC

CCb

−− +=

Page 7: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

7

EE141

Multistage Networks

Stage effort: hi = gifiPath electrical effort: F = Cout/Cin

Path logical effort: G = g1g2…gN

Branching effort: B = b1b2…bN

Path effort: H = GFB

Path delay D = Σdi = Σpi + Σfigi/γ

∑=

⋅+=

N

i

iii

fgpDelay1 γ

EE141

Optimum Effort per Stage

HhN =ˆWhen each stage bears the same effort:

N Hh =ˆ

PNHpfgDN

iii +=

+=∑ γγ

/1ˆ

Minimum path delay

Effective fanout of each stage:ii ghf ˆ=

Page 8: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

8

EE141

Optimal Number of Stages

For a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing

invN NpNHD += /1

( ) 0ln /1/1/1 =++−=∂∂

invNNN pHHH

ND

NHh ˆ/1=Substitute ‘best stage effort’

EE141

Example: Optimize Path

1a

b c

5

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

Effective fanout, F = 5G = 25/9H = 125/9 = 13.9f = 1.93a = 1.93b = fa/g2 = 2.23c = fb/g3 = 5g4/f = 2.59

Page 9: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

9

EE141

Multi-level logic: What is the best?

g = 10/3 g =1

G = 10/3g = 2 g =5/3

G = 10/3g =4/3 g=5/3 g=4/3 g=1

G = 80/27

EE141

Handling Wires & Fixed Loads

CL

Cw

∑=

+⋅+=

N

i

iiii

wfgpDelay1

)(γ

Page 10: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

10

EE141

Summary

D = DH + Pd = h + pDelay

pParasitic Delay

N1Number of Stages

hEffort DelayH = FGBh = fgEffort

n/aBranching Effort

f = Cout/CinElectrical Effort

gLogical EffortPathStage

∏= igG

inout CCF /=

∏= ibB

∑= iH hD

∑= ipP

EE141

Method of Logical Effort

Compute the path effort: H = GBFFind the best number of stages N ~ log4HCompute the stage effort h = H1/N

Sketch the path with this number of stagesWork either from either end, find sizes: Cin = Cout*g/h

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

Page 11: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

11

EE141

Ratioed Logic

VDD

VSS

PDNIn1In2In3

F

RLLoadResistive

(a) resistive load

VDD

VSS

PDNIn1In2In3

FVSS

PMOSLoad

(c) pseudo-NMOS

Goal: reduce the number of transistors over complementary CMOS

EE141

Ratioed Logic

VDD

VSS

PDNIn1In2In3

F

RLLoadResistive

N transistors + Load

• VOH = VDD

• VOL = RPN

RPN + RL

• Assymetrical response

• Static power consumption

• tpL= 0.69 RLCL

VDD

Page 12: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

12

EE141

Pseudo-NMOS VTC

0.0 0.5 1.0 1.5 2.0 2.50.0

0.5

1.0

1.5

2.0

2.5

3.0

Vin [V]

Vou

t[V

]

W/Lp = 4

W/Lp = 2

W/Lp = 1

W/Lp = 0.25

W/Lp = 0.5

VDD

VSS

PDNIn1In2In3

FVSS

PMOSLoad

(c) pseudo-NMOS

EE141

Pseudo-NMOS

VDD

A B C D

FCL

VOH = VDD (similar to complementary CMOS)

kn VDD VTn–( )VOLVOL

2

2-------------–

kp

2------ VDD VTp–( )

2=

VOL VDD VT–( ) 1 1kpkn------–– (assuming that VT VTn VTp )= = =

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Page 13: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

13

EE141

Improved Loads

A B C D

F

CL

M1M2 M1 >> M2Enable

VDD

Adaptive Load

EE141

Improved Loads (2)

VDD

VSS

PDN1

Out

VDD

VSS

PDN2

Out

AABB

M1 M2

Differential Cascode Voltage Switch Logic (DCVSL)

Page 14: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

14

EE141

DCVSL Example

B

A A

B B B

Out

Out

XOR-NXOR gate

EE141

DCVSL Transient Response

0 0.2 0.4 0.6 0.8 1.0-0.5

0.5

1.5

2.5

Time [ns]

Vol

tag e

[V] A B

A B

A,BA,B

B

A A

B B B

Out

Out

XOR-NXOR gate

Page 15: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

15

EE141

Pass-Transistor Logic

Inpu

ts Switch

Network

OutOut

A

B

B

B

• N transistors• No static consumption

EE141

Example: AND Gate

B

B

A

F = AB

0

Page 16: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

16

EE141

NMOS-Only Logic

VDD

In

Outx

0.5µm/0.25µm0.5µm/0.25µm

1.5µm/0.25µm

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]Vo

ltage

[V]

xOut

In

EE141

NMOS-only Switch

A = 2.5 V

B

C = 2.5V

CL

A = 2.5 V

C = 2.5 V

BM2

M1

Mn

Threshold voltage loss causesstatic power consumption

VB does not pull up to 2.5V, but 2.5V -VTN

NMOS has higher threshold than PMOS (body effect)

Page 17: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

17

EE141

NMOS Only Logic: Level Restoring Transistor

M2

M1

Mn

Mr

OutA

B

VDDVDDLevel Restorer

X

• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problem

EE141

Level Restoring Transistor

(a) Output node (b) Intermediate node X

0 2 4 6t (nsec)

-1.0

1.0

3.0

5.0

Vou

t (V

)

0 2 4t (nsec)

-1.0

1.0

3.0

5.0

VX

with

without

VB

with

without

6

Page 18: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

18

EE141

Restorer Sizing

0 100 200 300 400 5000.0

1.0

2.0

W/Lr =1.0/0.25 W/Lr =1.25/0.25

W/Lr =1.50/0.25

W/Lr =1.75/0.25

Time [ps]

3.0• Upper limit on restorer size

• Pass-transistor pull-downcan have several transistors in stack

Volta

ge [V

]

EE141

Solution 2: Single Transistor Pass Gate with VT=0

Out

VDD

VDD

2.5V

VDD

0V 2.5V

0V

WATCH OUT FOR LEAKAGE CURRENTS

Page 19: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

19

EE141

Complementary Pass Transistor Logic

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=A⊕ΒÝ

F=A⊕ΒÝ

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-TransistorNetwork

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)

EE141

Solution 3: Transmission Gate

A B

C

C

A B

C

C

BCL

C = 0 V

A = 2.5 V

C = 2.5 V

Page 20: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

20

EE141

Resistance of Transmission Gate

Vout

0 V

2.5 V

2.5 VRn

Rp

0.0 1.0 2.00

10

20

30

Vout, V

Res

ista

nce,

ohm

s

Rn

Rp

Rn || Rp

EE141

Pass-Transistor Based Multiplexer

AM2

M1

B

S

S

S F

VDD

GND

VDD

In1 In2S S

S S

Page 21: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

21

EE141

Transmission Gate XOR

A

B

F

B

A

B

BM1

M2

M3/M4

EE141

Delay in Transmission Gate Networks

V1 Vi-1

C

2.5 2.5

0 0

Vi Vi+1

CC

2.5

0

Vn-1 Vn

CC

2.5

0

In

V1 Vi Vi+1

C

Vn-1 Vn

CC

InReqReq Req Req

CC

(a)

(b)

C

Req Req

C C

Req

C C

Req Req

C C

Req

CIn

m

(c)

Page 22: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

22

EE141

Delay Optimization

EE141

Transmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

Page 23: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

23

EE141

Dynamic CMOS

In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.» fan-in of n requires 2n (n N-type + p P-type)

devices

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.» requires on n + 2 (n+1 N-type + 1 P-type)

transistors

EE141

Dynamic Gate

In1

In2 PDNIn3

Me

Mp

CLK

CLKOut

CL

Out

CLK

CLK

A

BC

Mp

Me

Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)

Page 24: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

24

EE141

Dynamic Gate

In1

In2 PDNIn3

Me

Mp

CLK

CLKOut

CL

Out

CLK

CLK

A

BC

Mp

Me

Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)

on

off

1off

on

((AB)+C)

EE141

Conditions on Output

Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.Inputs to the gate can make at most one transition during evaluation.

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

Page 25: EE141- Spring 2003bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s03/Lectures/Lectu… · EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay:

25

EE141

Properties of Dynamic Gates

Logic function is implemented by the PDN only» number of transistors is N + 2 (versus 2N for static complementary

CMOS)

Full swing outputs (VOL = GND and VOH = VDD)Nonratioed - sizing of the devices is not important for proper functioningFaster switching speeds» reduced load capacitance due to lower input capacitance (Cin)» reduced load capacitance due to smaller output loading (Cout)» no Isc, so all the current provided by PDN goes into discharging CL

EE141

Properties of Dynamic GatesOverall power dissipation usually significantly higher than static CMOS» no static current path ever exists between VDD and GND

(including Psc)» no glitching» higher transition probabilities» extra load on CLK

PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL equal to VTn» low noise margin (NML)

Needs a precharge clock