EE 221 Midterm Solutions -...
Transcript of EE 221 Midterm Solutions -...
EE 221 Midterm Solutions October 30, 2002
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1)
Figure 1
a) Determine and sketch the Thevenin’s equivalent circuit for the output terminals A and B. Solution First one should realize that R3, R5, and R7 along with I2 and V2 have no bearing on the final solution. Thus the circuit to determine RTH is:
RTH = R2 + R4//R6 = 300Ω Circuit to determine VTH is:
VA = I1 x R2 = 50 mA x 260 Ω = 13 V and VVRR
RVVB 1060120
1201564
41 =
Ω+ΩΩ=
+=
EE 221 Midterm Solutions October 30, 2002
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VAB = VTH = VA – VB = 13 V – 10 V = 3 V
Thevenin Equivalent Circuit. b) At what value of load resistance will 600 µA flow through the load? RLoad = _4.7 kΩ_
Ω=Ω−=−=∴+
= kA
VRA
VRRR
VA THTH
LoadLoadTH
TH 7.4300600
3600
600µµ
µ
c) At what value of load resistance is maximum power transferred? RLoad = __300 Ω__ Maximum Power is transferred when RLoad = RTH = 300 Ω d) What would be the minimum load resistance if this Thevenin’s equivalent circuit was to be a stiff voltage supply? RLoad(min) = ___30 kΩ__ From the definition of a stiff supply! RLoad(min) = 100 x RS. In this case RS is the Thevenin resistance (RTH). Hence RLoad(min) = 100 x 300 Ω = 30 kΩ e) What is the Norton’s equivalent circuit? (Provide a circuit sketch as well)
RN = RTH = 300 Ω and mAVRVI
TH
THN 10
3003 =
Ω==
Norton Equivalent Circuit.
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2) (Use the second approximation of the diode!)
Figure 2
NOTE: There is an error on the diagram, both D1 and D2 should be flipped so that the anode is connected to ground. With the above configuration the output would be zero as there is no ground connection for current flow. a) What is the peak or maximum voltage across the load? VLoad = __20 V_ For a primary transformer voltage of 120 Vac gives a secondary voltage of 20 Vac means that
the transformer turns ratio is, 620
120 =VacVac . Thus for a primary voltage of 90.8 Vac the secondary
voltage is PVVacVacVac 4.212133.15133.1568.90 ≅×==
Realizing that this is a bridge rectifier and the fact that we are using the second approximation of the diode gives a load voltage of 21.4 V – 1.4 V = 20 V. b) What is the peak to peak ripple voltage at the load? Vripple = __0.250 VP-P__
ARV
ILoad
LoadLoad 2.0(max) == and since this is a bridge rectifier circuit as well means that the rectified
frequency is double the input frequency of 60 Hz. Hence the time between charging for the
capacitor is sec3.8120
1 mHz
=
So to find the change in charge is as follows; mCmAQ 6.1sec3.82.0 =×=∆
PPPP VmVmF
mCCQV
VQ
−− ≅==∆=∆∴∆∆= 250.09.249
67.66.1eCapacitanc
EE 221 Midterm Solutions October 30, 2002
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-22
-20
-18
-16
-14
-12
-10-8-6-4-20246810121416182022
030
6090
120
150
180
210
240
270
300
330
360
390
420
450
480
510
540
570
600
630
660
690
720
Voltage
VAVB
With
out F
ilter C
ap.
VB W
ith F
ilter C
ap.
Vripp
le ~
0.250
Vp-
p
21.4
V
c) What rectifier configuration is this supply? Bridge Rectifier (well supposed to be ) d) Using the graph on the next page, sketch the waveform at point ‘A’. Also on the same graph sketch the resulting waveform at point ‘B’ both with and without the capacitor in circuit. (You must indicate which waveform is which along with voltage levels.) Please try to be neat! A sloppy diagram may lead to a misinterpretation and lost marks.
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3) (Use the second approximation of the diode!) Sketch the waveform at each terminal, A, B, C, and D on the supplied graphs. Please try to be neat! A sloppy diagram may lead to a misinterpretation and lost marks.
Figure 3
Circuit break down: D1 and C3 = Peak Detector 1. Sets up a bias for Clamper 1. C2 and D4 = Clamper 1. D3 and C5 = Peak Detector 2. Sets up a bias for Clamper 2. C1 and D2 = Clamper 2. D5 and C4 = Peak Detector 3.
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Question 3 Continued
-2-1.9-1.8-1.7-1.6-1.5-1.4-1.3-1.2-1.1
-1-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.1
00.10.20.30.40.50.60.70.80.9
11.11.21.31.41.51.61.71.81.9
2
0 30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Vs VA
-3-2.8-2.6-2.4-2.2
-2-1.8-1.6-1.4-1.2
-1-0.8-0.6-0.4-0.2
00.20.40.60.8
11.21.41.61.8
22.22.42.62.8
3
0 30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Vs VB
Graph 1 for VA
Graph 2 for VB
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Question 3 Continued
-3-2.8-2.6-2.4-2.2
-2-1.8-1.6-1.4-1.2
-1-0.8-0.6-0.4-0.2
00.20.40.60.8
11.21.41.61.8
22.22.42.62.8
3
0 30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Vs VB VC
-0.7 V
0.9 V
-3-2.8-2.6-2.4-2.2
-2-1.8-1.6-1.4-1.2
-1-0.8-0.6-0.4-0.2
00.20.40.60.8
11.21.41.61.8
22.22.42.62.8
3
0 30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Vs VD
1.5 V
Graph 3 for VC
Graph 4 for VD
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1 2
4 0.7 ( 2 ) 2.65V V VI mAR R
− − −= =+ 1 1 2 0.65V IR V V= − =
-5.5
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0 30 60 90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Vin Vout
1.35 V
4) (Use the second approximation of the diode!) With the given Vin sketch Vout on the same graph. Please try to be neat! A sloppy diagram may lead to a misinterpretation and lost marks.
Figure 4
Because there are supplies attached means that the diodes will have a forward biased region for an input waveform. To determine what this region is and how the output will look is as follows. First let’s determine a relationship between Vin and Vout. This can be done by choosing an intermediate point such as V1. Vout = V1 + 0.7 V and V1 = Vin – 0.7 V Vout = Vin – 0.7 V +0.7 V But this is not for all cases of Vin! The upper end will be limited by the +4 V supply. In other words for an input signal greater than 4 V D2 will be reversed biased. To determine the lower limit we have to find what V1 is when no input signal is applied. In this condition current will flow from the +4 V supply through R2, D2 and R1 to the –2 V supply.
But we are interested in Vout = V1 + 0.7 V = 1.35 V therefore the lower limit is 1.35 V.
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5) (Assume β = 100, VBE = 0.7 V and VCE(sat) = 0.3 V)
Figure 5
Find the following for the above transistor Schmitt trigger. a) Determine the: - Upper Trip Point? UTP = __10 V_ - Lower Trip Point? LTP = __4 V_ - Hysteresis Voltage? VH = __6 V_
VVk
kVRR
RUTP CC 10122001
1
54
4 =Ω+Ω
Ω=+
=
VVkk
kVRR
RLTP CC 41212
1
42
4 =Ω+Ω
Ω=+
=
VH = UTP – LTP = 10V – 4V = 6V
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Question 5 Continued b) It is determined that a capacitor can be used in order to increase the switching time.
On the circuit diagram sketch where this capacitor is to be connected. See CS on diagram (Figure 5)!
c) If this was a 621 pF capacitor, what would the maximum switching frequency be? Fmax = _700 kHz_
max
1 3.2 F
treR
tC re == R = R3//R2
max32
32
32
32
max
3.23.2
1
FRRRR
RRRR
FC +=
+
=∴
kHzkHzpFkk
kkCRR
RRF 70013.700
621223.222
3.2 32
32max ≅=
×Ω×Ω×Ω+Ω=
+=⇒
d) List two advantages the transistor Schmitt Trigger has over a Basic Transistor Switch. 1) Different trip points for turn on (UTP) and turn off (LTP). 2) The output signal tracks the input signal. i.e. When the input is low the output is low
and when the input is high the output is high.
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6) (Assume β = 100, VBE = 0.7 V, VCE(sat) = 0.3 V, and at room temperature (300 oK))
Figure 6
a) Draw the DC load line and determine the Q point. (Use the supplied transistor curve and label the X and Y axis’ values) ICQ = _1.02 mA_ VCEQ = _5.42 V_
VCE (V)
IC (mA)
2 4 6 8 10 12 14 16 18 20
1.41
1.20
1.00
0.80
0.60
0.40
0.20
1.40
Q
5.42 V
1.02
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Question 6 Continued Page for Q point calculations
mAmAkk
VRRR
VI CC
C 41.1406.105.217512
20
543(max) ≅=
Ω+Ω+Ω=
++=
Vkk
kVRR
RVV CCBQ 3317
32021
2 =Ω+Ω
Ω=+
=
VVVVVV BEBQEQ 3.27.03 =−=−=
mAk
VRR
VI EQ
EQ 034.105.2175
3.2
54
=Ω+Ω
=+
=
mAmAmAII EQCQ 02.1024.1034.11100
1001
≅=+
=+
=β
β
VkmAVRIVV CQCCCQ 72.712024.1203 =Ω×−=−=
VVVVVV EQCQCEQ 42.53.272.7 =−=−=
EE 221 Midterm Solutions October 30, 2002
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Question 6 Continued b) Determine the input impedance (Zin), output impedance (Zout) and voltage gain (Av).
Zin = __2.26 kΩ__ Zout = _12 kΩ__ Av = __- 60 _
Ω== kRZout 123 Zin = R1//R2//β( er ' + R4)
EQ
T
IVer =' V
qkTVT 02585.0== @ room temp. (300oK). Ω≅=∴ 25
034.102585.0'
mAVer
Zin = 17 kΩ//3 kΩ//100(25 Ω + 175 Ω) = 2.26 kΩ
6017525
12' 4
3 −=Ω+Ω
Ω−=+
−= k
RerR
AV
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Question 6 Continued c) Sketch the T and π transistor ac models for this circuit. (Remember to label all components)
EE 221 Midterm Solutions October 30, 2002
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Question 6 Continued d) Sketch the DC transistor model for this circuit. (Remember to label all components)
e) Is this a stiff voltage divider bias? (You must show proof to support your answer)
R1//R2 = Ω=Ω+ΩΩ×Ω k
kkkk 55.2
317317
Ω=Ω+Ω=+= kkRRRE 225.205.217554
Definition of a stiff voltage divider bias is R1//R2 < 0.01 β RE Since β = 100 then 0.01 β = 1 and 2.55 kΩ is NOT less than 2.225 kΩ Therefore this is NOT a stiff voltage divider bias.