ECEN4533 Data CommunicationsLecture #37 10 April 2013Dr. George Scheets

ECEN4533 Data CommunicationsLecture #37 10 April 2013Dr. George Scheets

Read 6.1 – 6.2Read 6.1 – 6.2 Problems: Web 27 & 28Problems: Web 27 & 28 Exam #2: Exam #2: << 15 April (DL) 15 April (DL) Corrected Quizzes dueCorrected Quizzes due

10 April (Live) 10 April (Live) & 1 week after return (DL) & 1 week after return (DL) Corrected tests due 17 April (Live) Corrected tests due 17 April (Live) Design #2 Final ResultsDesign #2 Final Results

Hi = 80, Low = 43.8, Ave = 68.60, Hi = 80, Low = 43.8, Ave = 68.60, σσ = 14.23 = 14.23

ECEN4533 Data CommunicationsLecture #38 12 April 2013Dr. George Scheets

ECEN4533 Data CommunicationsLecture #38 12 April 2013Dr. George Scheets

Read 6.3Read 6.3 Problems: 4.2, 4.8, Web 29Problems: 4.2, 4.8, Web 29 Exam #2: Exam #2: << 15 April (DL) 15 April (DL) Corrected Quizzes due 1 week after return (DL)Corrected Quizzes due 1 week after return (DL) Corrected tests due 17 April (Live) Corrected tests due 17 April (Live) Wireshark Project due by midnight 4 May (All)Wireshark Project due by midnight 4 May (All)

Late turn in NOT acceptedLate turn in NOT accepted 15 points + 20 points extra credit15 points + 20 points extra credit

2013 OSU ECE Spring Banquet2013 OSU ECE Spring Banquet Hosted by Student Branch of IEEEHosted by Student Branch of IEEE Wednesday, 17 April, at MeditationsWednesday, 17 April, at Meditations Doors open at 5:30 pm, meal at 6:00 pmDoors open at 5:30 pm, meal at 6:00 pm Cash BarCash Bar Sign up in ES202 to reserve your seat(s)Sign up in ES202 to reserve your seat(s) $5 a head (for a $16 meal!)$5 a head (for a $16 meal!)

ifif pay in advance and resume submitted pay in advance and resume submittedto OSUIEEEresume@gmail.comto OSUIEEEresume@gmail.com<< noon, 16 April. Otherwise $8. noon, 16 April. Otherwise $8.

Speaker: Dr. Matt PerrySpeaker: Dr. Matt PerryDirector, SiArchDirector, SiArch

Dress is Business CasualDress is Business Casual Many door prizes available!Many door prizes available!

+10 points extra credit +10 points extra credit All are invited!All are invited!

Sponsored in part by:

Ways to decrease P(Bit Error)Ways to decrease P(Bit Error) Crank up power outCrank up power out Reduce noise in systemReduce noise in system Slow down transmitted bit rateSlow down transmitted bit rate Use directional antennasUse directional antennas

Need some fancy DSP to steer beamsNeed some fancy DSP to steer beams Use Forward Error Correcting codesUse Forward Error Correcting codes

Add controlled redundancy to bit streamAdd controlled redundancy to bit stream Extra parity bits must be transmittedExtra parity bits must be transmitted

System at BW limit w/o FEC? System at BW limit w/o FEC? Go M-Ary or reduce Layer 2-7 bpsGo M-Ary or reduce Layer 2-7 bps

No coding: Binary SystemNo coding: Binary System

Source

Channel

Channel Coder

Symbol Detector

Source: Outputs a bit streamSource: Outputs a bit stream Channel Coder: Maps bit stream into a form suitable for Channel Coder: Maps bit stream into a form suitable for

channelchannel Channel: Attenuates, distorts, & adds noiseChannel: Attenuates, distorts, & adds noise Symbol Detector: Looks at received symbol and decides (if Symbol Detector: Looks at received symbol and decides (if

binary) "1?" or "0?"binary) "1?" or "0?"

Suppose P(Bit Error) = 0.1

2:1 FEC Binary System2:1 FEC Binary System

SourceSource Coder:Input = 1 bit.

Output = Input + Parity

bit.

Channel

Channel Coder

Symbol Detector

Source Decoder:Looks at blocks of

2 bits. Outputs1 bit.

R bpsLayer 2-7

2Rcoded

bps

2R coded bpsR bps

Suppose P(Coded BE) = 0.1Suppose P(Coded BE) = 0.1 P(Layer 2-7 BE) also = 0.1P(Layer 2-7 BE) also = 0.1

*Binary → 2x BW*4-Ary → same BW

2 bits/symbol

Example) Two bit code wordsExample) Two bit code words Suppose you now transmit each bit twice, and Suppose you now transmit each bit twice, and

P(Code Bit Error) = .1 P(Code Bit Error) = .1 Legal Transmitted code words; 00, 11Legal Transmitted code words; 00, 11 Possible received code wordsPossible received code words

00, 11 (appears legal, 0 or 2 bits decoded in error)00, 11 (appears legal, 0 or 2 bits decoded in error)01, 10 (clearly illegal, 1 bit decoded in error)01, 10 (clearly illegal, 1 bit decoded in error)P(No bits in error) = .9*.9 = .81P(No bits in error) = .9*.9 = .81P(One bit in error) = 2*.9*.1 = .18P(One bit in error) = 2*.9*.1 = .18P(Both bits in error) = .1*.1 = .01P(Both bits in error) = .1*.1 = .01

Decoder takes 2 Code bits at a time & outputs 1 bit of DataDecoder takes 2 Code bits at a time & outputs 1 bit of DataIf illegal code word received, it can guess 0 or 1.If illegal code word received, it can guess 0 or 1.81%81% + + 18%(1/2)18%(1/2) = 90% of time the correct bit is output = 90% of time the correct bit is output 1%1% + + 18%(1/2)18%(1/2) = 10% of time the incorrect bit is output = 10% of time the incorrect bit is output

Same performance as No Coding @ twice the bit rateSame performance as No Coding @ twice the bit rate

3:1 FEC Binary System3:1 FEC Binary System

SourceSource Coder:Input = 1 bit.

Output = Input +

2 Parity bits

Channel

Channel Coder

Symbol Detector

Source Decoder:Looks at blocks of

3 bits. Outputs1 bit.

R bpsLayer 2-7

3Rcoded

bps

3R coded bpsR bps

Suppose P(Code BE) = 0.1Suppose P(Code BE) = 0.1

*Binary → 3x BW*8-Ary → same BW

3 bits/symbol

Example) SSD 3 bit code wordsExample) SSD 3 bit code words Transmit each bit thrice, P(Code Bit Error) = .1Transmit each bit thrice, P(Code Bit Error) = .1

Legal Transmitted code words; 000, 111Legal Transmitted code words; 000, 111 Possible received code wordsPossible received code words

000, 111 (appears legal, 0 or 3 bits in error)000, 111 (appears legal, 0 or 3 bits in error)001, 010, 100 (clearly illegal, 1 or 2 bits in error)001, 010, 100 (clearly illegal, 1 or 2 bits in error)011, 101, 110 (clearly illegal, 1 or 2 bits in error)011, 101, 110 (clearly illegal, 1 or 2 bits in error)P(No bits in error) = .9*.9*.9 = .729P(No bits in error) = .9*.9*.9 = .729P(One bit in error) = 3*.9P(One bit in error) = 3*.922*.1 = .243*.1 = .243P(Two bits in error) = 3*.9*.1P(Two bits in error) = 3*.9*.122 = .027 = .027 P(Three bits in error) = .1*.1*.1 = .001P(Three bits in error) = .1*.1*.1 = .001

Decoder takes 3 bits at a time & outputs 1 bit. Majority Rules.Decoder takes 3 bits at a time & outputs 1 bit. Majority Rules.72.9%72.9% + 24.3% = 97.2% of time correct bit is output + 24.3% = 97.2% of time correct bit is output .1%.1% + + 2.7%2.7% = 2.8% of time incorrect bit is output = 2.8% of time incorrect bit is output

Improved performance as No Coding @ thrice the bit rateImproved performance as No Coding @ thrice the bit rate

Local Oscillator On Frequency & PhaseLocal Oscillator On Frequency & Phase

X

=

Cos(0)

Local Oscillator off frequencyLocal Oscillator off frequency

X

=

Cos(2πΔf)

Doppler Effect 60 mph (26.8 m/sec), 2 m offset

Doppler Effect 60 mph (26.8 m/sec), 2 m offset

Receiver Phase Locked LoopReceiver Phase Locked Loop

XActive

Low PassFilter

VoltageControlledOscillator

cosωct(from antenna)

sin((ωvcot +θ) -sin((ωvco -ωc)t+θ)

VCO set to free run at ≈ ωc

VCO output frequency = ωc + K * input voltage

LPF withnegative gain.

2 sinα cosβ = sin(α-β) + sin(α+β)

Phase Locked LoopPhase Locked Loop

XActive

Low PassFilter

VoltageControlledOscillator

cosωct(from antenna)

sin(ωvcot) -sin((ωvco -ωc)t)

VCO frequency and phase locked.ωvco-ωc = 0 & θ = 0

Input to VCO = 0 volts.

LPF withnegative gain.

Phase Locked LoopPhase Locked Loop

XActive

Low PassFilter

VoltageControlledOscillator

cosωct(from antenna)

-sinθ

VCO on frequency & positive θ?VCO phase is slightly ahead & needs to slow down.

Negative voltage momentarily applied.

sin((ωvcot )+θ)

LPF withnegative gain.

Phase Locked LoopPhase Locked Loop

XActive

Low PassFilter

VoltageControlledOscillator

cosωct(from antenna)

sinωvcot -sin(ωvco -ωc)t

LPF withnegative gain.

VCO off frequency?Oscillating input voltage moves VCO frequency up & down.

If close enough to input, system will lock.

M-Ary SignalingM-Ary Signaling One of M possible signals transmitted each symbol intervalOne of M possible signals transmitted each symbol interval Tends to be used where bandwidth is tight & SNR decent Tends to be used where bandwidth is tight & SNR decent

at the receiver. at the receiver. Each symbol can represent logEach symbol can represent log22(M) bits(M) bits

Example: In 16 PSK Example: In 16 PSK one of 16 possible phase angles is transmitted every symbol one of 16 possible phase angles is transmitted every symbol

intervalinterval each symbol can represent 4 bitseach symbol can represent 4 bits

QAM normally usedQAM normally used each symbol has different amplitude & phaseeach symbol has different amplitude & phase