Digital Transceiver Implementation

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Digital Transceiver Implementation. Characterization Presentation Barak Shaashua Barak Straussman Supervisor: Idan Shmuel. Project Goals. Implementation of transceiver with Labview on FPGA . Project parts: 16 QAM Tranceiver 8 PSK Tranceiver. Transmitter Block Diagram. I. - PowerPoint PPT Presentation

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Symbol DecisionConstellationMappingChannel DecoderRFParallel/ SerialReceiver Block-DiagramADC

Sin(wt)+ /2IQIQ(+ Source)Timing & Carrier RecoveryLPFLPFProject GoalsImplementation of transceiver with Labview on FPGA.

Project parts:16 QAM Tranceiver8 PSK TranceiverConstellation MappingImplementation with Lock Up Table

Symbols - according to Gray Code

One LUT for 16QAM, another for PSK

11ISISymbol interference results of dispersion in transmission mediumISI filter decreases this interferenceFilter: Root Raised Cosine

Project Environment SoftwareLabView 2010 v.10(FPGA, RF toolbox)Tabor ArbConnectionHardwareFPGA Virtex5, NI FlexRio BoardNI 5761 DigitizerTabor wx2182Scope, Spectrum Analyzer

Combiner 5M 2500MNI 5761 Digitizer 14-Bit, 250 MS/s, 500Mhz BWTabor wx2182, 2.1GS/s, 16Mb waveform memory, 1Ghz (sin) , 12 digits resolution.

5Hardware Connection

RatesFPGA 400Mb/sTabor 2.1GS/s, 16MB waveform memoryDigitizer 250MS/sGPIB 1.5MB/sLAN Fast Ethernet 100Mb/sCoaxial cable BW 4.2Ghz

Our IF frequency: 100MhzTabor Symbol Rate possible: 100Khz 500Mhz

Time Table1.2 28.28.1 31.125.12 7.14.12 24.1227.11 3.123.11 26.11Studying project material & work environment Transmitter Block DesignReceiver Block DesignFPGA Simulation & debuggingTestsChannel CoderBlock Code as Hamming Code:

Implementation with vectors and matrices representationAble to detect up to 2 errors and correct one

Timing & Carrier RecoveryRecovers 3 elements:Symbol Timing Grander AlgorithmCarrier FrequencyCarrier Phase

Makes use of Digital PLL