Development of National System-on-Chip (NSoC) Program in ... · NSoC 12 Nov. 18, 2004 National SoC...

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Development of National System-on-Chip (NSoC) Program in Taiwan Dr. Chun-Yen Chang and Dr. Wei Hwang National Chiao Tung University Hsin-chu, Taiwan http://nsoc.eic.nctu.edu.tw

Transcript of Development of National System-on-Chip (NSoC) Program in ... · NSoC 12 Nov. 18, 2004 National SoC...

  • Development of National System-on-Chip (NSoC)

    Program in Taiwan

    Dr. Chun-Yen Chang and Dr. Wei Hwang National Chiao Tung University

    Hsin-chu, Taiwanhttp://nsoc.eic.nctu.edu.tw

  • 2NSoC Nov. 18, 2004

    OutlineIntroductionThe Si-Soft InitiativeNational SoC Program Summary

  • 3NSoC Nov. 18, 2004

    Evolution of Silicon Technology

    1980 1990 2000 2010

    VLSI

    SoC era

    PCμp + Memory

    Computer Focus Comp./Comm./ Consumer/ Content/Convergence

    2020

    GSI

    HeterogeneousIP and Platform-based DesignLow PowerScaleable, reuse methodology

    Wireless Multimedia NetworkingDSP + Analog + RF

  • 4NSoC Nov. 18, 2004

    Unit: USD Billion

    95 96 97 98 99 00 01 95 - 01CAGRTaiwanFabless 0.7 0.8 1.3 1.3 2.2 3.3 3.6 31%

    WorldwideFabless 5.9 6.7 7.6 8.7 11.7 16.6 13.9 15%

    % of share 12% 12% 17% 15% 19% 20% 26%

    TaiwanFoundry 1.1 1.4 2.0 2.8 4.9 9.0 6.1 33%

    WorldwideFoundry 5.1 5.0 5.1 5.3 7.5 12.9 8.3 8%

    % of share 21% 27% 39% 52% 65% 70% 73%

    Source: Dataquest, FSA, ITRI

    Brilliant Taiwan IC Design & Foundry

    Foundry: Ranked 1st Worldwide, shares 76%IC Design: Ranked 2nd Worldwide, shares 30%

    Our Vision: more than 50% by 2008

  • 5NSoC Nov. 18, 2004

    A few Top Academic Achievements in IT Research

    1996-2002 Published Papers in 65 IEEE Journals & Magazines

    70866976607259University of Illinois at Urbana-Champaign

    83544964466052U.C. Berkely(University of California at Berkeley)

    42486665647065UCLA(University of California at Los Angeles)

    84766278755274Stanford University

    77947964709171MIT(Massachusetts Institute of Technology)

    64576169817862台灣大學(National Taiwan University)

    8887102921038974交通大學(National Chiao-Tung University)

    1996年

    1997年

    1998年

    1999年

    2000年

    2001年

    2002年學 校

  • 6NSoC Nov. 18, 2004

    2001-2005 Published Papers in ISSCC

    916224191183159159Total

    811042Finland

    942111Ireland

    1563402France

    1972424Canada

    2084530Italy

    23105404Switzerland

    2647348Belgium

    28155350Taiwan

    35481067Germany

    4910111387The Netherlands

    72171719127Korea

    1874544373031Japan

    4259382808486USA

    Total20052004200320022001Country

  • 7NSoC Nov. 18, 2004

    2002-2004 Published Papers in IEDM

    661226221214Total

    10433The Netherlands

    13553Singapore

    23887Italy

    241086Belgium

    301956France

    34111112Germany

    42151611Taiwan

    71242324Korea

    155485552Japan

    259828790USA

    Total200420032002Country

  • 8NSoC Nov. 18, 2004

    Numbers of Patent Issued in USA

    169120

    148169

    145722

    136323

    131964126297953429239085002853398280481115

    79346

    74077Total

    12761348128913021184126996292283995310071002937983Italy

    151316471669152013011084760743643566472472556565Sweden

    169416321625141813391211960978889978974107810651031Swiss

    21602286255123642391236219381750168015861738180821082046England

    21811662841834784790581555565636534550586516Holland

    25762536254222762079182513421294118811071070103811041005Canada

    34953669374534173280318225722387238523802541261125212373France

    368936813656307320961534955780612436364236168121Taiwan

    373435833375318234823167183914151091874689470337163Korea

    10394101321011190498101796761076016583158185995632664656541Germany

    355413489233258311443097330442228912278021379220072187221467204851891

    2Japan

    746167651176927733657184168480521945065845939462324383842266411533796

    3U.S.A

    20032002200120001999199819971996199519941993199219911990Country

    單位:篇

  • 9NSoC Nov. 18, 2004

    Global Competitiveness Report (2004-2005)

    24556246China

    23454334Thailand

    20382731Malaysia

    3541929Korea

    1393421HK

    871811England

    12171410Iceland

    291659Japan

    5878Swiss

    110117Singapore

    25106Norway

    4165Denmark

    92724Taiwan

    17643Sweden

    152112USA

    3331Finland

    Macroeconomic EnvironmentPublic PolicyTechnology

    Growth CompetitivenessCountry

    Source: WEF (World Economy Forum)

  • 10NSoC Nov. 18, 2004

    Si-Soft Initiative- Vision

    Electro-OpticalLCD, Optical Communication,

    Storage DevicesInformationAppliancesPDA’s , GamesHumanities/Art

    Internet Intra-netSoftware, Routers

    Protocols, Switches, Applications

    EnergyBatteries, Cells

    P-SOCS/W O/S

    System Integration

    CommunicationsWireless, Satellite

    Bio-MedicalBio-Informatics,Bio-chips, BME

    MEMs

    Nano-Technology

    Material MechanicalAutomotive, Aerospace

    Chemical

    Civil/Environmental

    Packaging Foundries

    Si-SoftSOC, EDA,

    IP, Products, Services

    Si-HardFoundry, GaAs

    ODM/OEM, Services

    Design IP Industry

    Knowledge EconomyThe engine of all industries

    The food Chain of Si-Soft Family

  • 11NSoC Nov. 18, 2004

    Si-Soft Initiative / National SoC Program

    StrategyCoordination and Promotion

    Design ServiceIP MallEDA VendorsIncubation CentersData Centers

    NSoC ProgramMission

    Human Resources Silicon Intellectual Property (SIP)Innovative Platform and EDAInnovative Product Emerging Industry Development

    Projects Review and FundingHuman Resources DevelopmentTechnology Research ProjectsIC Design Park Promotion

    VisionSi-Soft Initiative

    ExecutionDesign and

    Service Park

    ExecutionGovernment Agencies:

    NSC / MOE / MOEA

  • 12NSoC Nov. 18, 2004

    National SoC Program- VisionPromote Taiwan’s 2nd High -Tech Revolution (The Si-Soft Initiative) Strengthen Taiwan’s industry to produce high value-added product

    Manufacturing

    Design Sevice

    Design

    Innovative Product

    Value Added

    Value Chain

    Supply Chain

    Industry Developing Key-point

  • 13NSoC Nov. 18, 2004

    Establish a richresource of Silicon IP

    Integrate EDA Tool and Services

    Provide Worldwide Customerswith Easy Design

    and SoC Total Solutions

    To providean outstanding

    design environment forthe use of global systems

    design firms.

    These measures will enableTaiwan to strengthen its

    manufacturing niche

    National SoC Program- Goal

    To establish a rich resource of Silicon Intellectual Property (SIP) in Taiwan within the next 3-5 years, to integrate electronic design automation (EDA) software, and to provide an outstanding design environment for the use of global systems design firms. These measures will enable Taiwan to strengthen its manufacturingniche, to continue its crucial role in the worldwide semiconductor business.

  • 14NSoC Nov. 18, 2004

    Sub-plan 1Human Resources

    Sub-plan 3InnovativePlatforms

    Sub-plan 4Innovative

    IP

    Sub-plan 2InnovativeProducts

    Sub-plan 5Emerging Industry

    Development

    3. InnovativePlatforms

    2. Innovative Products

    4. InnovativeIP

    5. Emerging IndustryDevelopment

    Platform Verification

    IP Verification

    Pd Verification Leading Product Vehicles

    +Foresight

    Matching PlansService Verification

    National SoC Research Program

    1. Human Resources

  • 15NSoC Nov. 18, 2004

    NSoC Human Resources PlanAdditional 85 faculty members per year specifically for SoC design for four years (2002 -2005)

    The specialty areas include RF/AMS, digital, embedded software, EDA tools and testing

    Establishment of Six Consortiums from Universities (MOE)Advanced Technologies (ADV), Digital IP (DIP), Electronic Design Automation (EDA), Mixed-Signal Design (MSD),Placement and Layout (P&L) and System-on-Chip (SoC) New VLSI Circuits and Systems Curriculum Development for SoCEra

    Enhancement of SoC graduate research programs (NSC)Integrated Research ProjectsMission Oriented Research Projects

  • 16NSoC Nov. 18, 2004

    SoC Education Development - (MOE)VLSI Circuits and Systems Design Education Program(six consortiums)

    SoC : System on ChipEDA : E. Design AutomationMSD : Mixed Signal Design P&L : Prototype & LayoutESW : Embedded SoftwareS&IP : System IP Consortium

    P&L

    S&IP

    EDA

    ESW

    MSD

    SoC

  • 17NSoC Nov. 18, 2004

    • Embedded Software• Nanometer Technology Circuit Design and EDA

    Course PromotionSystem Software & Verification SoC as 2nd majorUnder graduate EDAUnder graduate analog ICSi-Soft Teacher Promotion

    Advanced CourseSOC Experiment PlatformSoC Innovation and Social Impact

    Course/HRData Base

    2002 2003 2004

    SoC Education Development – (MOE)

  • 18NSoC Nov. 18, 2004

    MOE:VLSI Circuits and Systems Design Education ProgramSet up six Consortia : System on Chip Consortium (SoC)、 Design Automation Consortium (EDA)、 Embedded Software Consortium (ESW)、Mixed Signal Design Consortium (MSD)、 Prototype & Layout Consortium (P&L) & System IP Consortium (S&IP)Develop 16 inter-collegiate VLSI design courses(1 course per 5 Professors)& promote to 30 colleges。Plan & promote the VLSI design program for university students not majoring in electrical engineering or computer science. Plan & promote the VLSI related inter-disciplinary courses such as high-tech laws, science, technology and humanity, and so on. Hold 4 times VLSI design related competitions and forums, over 3000 participants.

    IDB:Soc Human Resource TrainingLong-term Class: 24 class,720 man/year.Short-term Class: 30 class,110 man/year.Set up trainee Certification Examination System.Total Trainee Amount in the right diagram : 3406127Amount

    136350Short-term49720Long-term

    FY93

    115642Short-term39015Long-term

    FY92

    ParticipantClassItemYear

    NSoC Human Resources Plan

  • 19NSoC Nov. 18, 2004

    NSoC Innovative Product PlanThree major SoC product lines

    Wireless, Processor, Optical ElectronicsDesign platform emphasis

    Build basic design, SIPs, integration, and design service infrastructure.

    Innovative Product GoalsUtilize IP Malls and Design Platform to implement chip-set and SoC.Extend to high end market and develop mainstream products.

  • 20NSoC Nov. 18, 2004

    VIA Technologies,Inc.

    ADD MICROTECHCORP.

    Novatek

    Genesys Logic

    AccFast Technology

    InfineonTechnologies

    WELTREND

    C-Media ElectronicsInc.

    ALI

    TrendchipTechnologies, Corp.

    IC Plus Corp.

    ExecutionUnit

    Interface architecture & specification between application processor (MAP) and WCDMA wireless modem (WCDMA SoC), and validationfor this integration system

    Road Runner

    Solid State Camcorder SoC

    Giga-Ethernet Controller with PCI Express

    Development of SHDSL Transceiver chip set

    Ipv4/v6 high-speed broadband network SoC

    Digital TV SoC for TFT/PDP Based Display

    High Defination and Deinterlacer-Integrated Video Processing SystemSingle Chip for Digital/Analog-Compatible TV

    Multi-functional DVD Rewritable ICs Development Plan

    Asymmetric Digital Subsciber Line II Plus Chipset Development

    Department of industrial

    Technology

    Gigabit NIC Single Chip Program

    ExecutionDivisionMajor Projects

    NSoC Innovative Product Plan

  • 21NSoC Nov. 18, 2004

    SoC for MPEG-4/21 Application and Next Generation Mobile Communications Research -- NCTU

    Embedded Bio-medical Diagnosis System-on-Chip Desig - CGU

    Integrated SoC Design for Realizing MPEG-4 Multimedia Information Appliances - NCKU

    IEEE802.11 a+b+g RF IC - Airoha Technology Corp.

    5GHz Wireless LAN RF (Radio Frequency) Transceiver and PA (Power Amplifier) Module - MuChip、Gatax Technology ZyFLEX Technologies, Inc. 、RoyalTek Company Ltd.、Service & Quality Technology CO.、ELAN Microelectronics Corp. 、Himax Technologies, Inc. 、iCreate Technologies Corp.、Media Reality Technologies.inc.

    Major Projects

    National Science Council

    IndustrialDevelopment

    Bureau

    ExecutionDivision

    NSoC Innovative Product Plan

  • 22NSoC Nov. 18, 2004

    NSoC – Comprehensive IP PlanEstablish key SIPs for SoC realizationVerify the feasibility, usability and reusability of SIP through Innovative Product Plan and Product VehiclesPromote Taiwan as a global IP mall.

  • 23NSoC Nov. 18, 2004

    DoITAcademic Reseach

    Private Cooperation

    Research Institutes

    ExecutionDivision

    IEEE 802.11a&802.11g Advanced Ip (ADC/DAC) Development Project –INNOCHIP32-bit Embedded Processor IP Development Project--SUNPLUS The development of Multimedia Codec Accelerator Silicon IP --VIVOTEKMultimedia SoC for Wireless Mobile Phone --quanta Development key technologies of modualized audio IP --Formosa development of 0.13um RFCMOS Design Platform and IP for RFIC Application - giga-solution Advanced high performance Video DSP SoC –uleadtek/SAC/ITEIP Verification throught Silicon Shuttle--UMCMultimedia SoC for Wireless Mobile Phone– quanta32-bit Low Power DSP Core-ITRI Multimedia Platform Generator,develop C-Base flow-ITRI WLANGPRS Dual-Mode RF Front End Receiver-ITRI Accomplish MB-OFDM UWB PHY Simulation & Analysis- Chung-Shan Institute of Science & Technology

    10Gbps VCO by 0.18um 1P6M CMOS-NCU 10Gbps Fiber IC by GaAs HBT-NCUAdvanced Network Security Processor –(NTHU)

    Major Projects

    NSoC Comprehensive IP Plan

  • 24NSoC Nov. 18, 2004

    National Science Council

    ExecutionDivision

    Innovative IP Design and SoC Implementation for Digital TV Receivers Complied with DVB-T Standards-- NSYSUA Unified, Low-Power RISC/DSP Processor with Configurable VLIW For Multimedia SOC Applications--CCU SoC Design of Low-Power Multi-Standard Multimedia Wireless LAN – NCHUSoC design for 10-G Ethernet--NTU The Study of SoC Design Technologies for OFDM-based SDR Baseband Processing-NCTU Design and Implementation of High-Performance Analog Integrated Circuits --NTUDesign Techniques for Ultra Low-power Programmable Processor Based SoCs –CCU

    Major Projects

    NSoC Comprehensive IP Plan

  • 25NSoC Nov. 18, 2004

    Infrastructure Project Build infrastructure for design and verification labs: 5

    Academic Integrated Project:Three categories: System, Platform, and IPs. 14 Groups and 88 Projects.

    Object Oriented Research ProjectPromote extreme low power design, high frequency and high performance analog circuits, processors and embedded software, nanometer EDA and Test. 4 groups and 31 Projects.

    Advanced SoC Research ProjectHigh level Integration technologys: 6 projects

    Advanced SoC Research Project – (NSC)

  • 26NSoC Nov. 18, 2004

    NSoC Advanced Platform Plan

    Behavior

    RTL, Synthesis,Capture, Floor planning

    Function, Performance, Power

    Physical Design, Interconnect Modeling(timing closure, signal integrity, …)

    Architecture (HW/SWpartitioning, co-design,hierarchical)

    SystemSpec

    DesignGeneration

    Verification

    main() {a0=a0+*r1++**r2;

    a0=a0+*r1;a0=a0+a1;

    if(gt) goto over;a0=a0-1;

    over:

    main() {int i, j, k;

    i=2;j=0;

    loop:k=j*i+23;

    j=4+j;

    Software

    Software

    DSP

    MCU

    Analog

    ASIC

    A turn-key solution for SoC Design - From software to SoC

    Std Cell & I/OLPSCDevicesMemoriesAnalogCoresTechnology

    Libraries

  • 27NSoC Nov. 18, 2004

    Customer’s Requirements

    NSoC Emerging Industry Development

    Data Center

    EDA Service

    Platform Service

    IP Collection

    SOC DesignServicesSOC DesignServices

    DesignDesign

    PCB Assembly

    Testing

    Package

    Mask

    Foundry

    ManufacturingService SoC Design Service

    IP Mall and Design Platform

  • 28NSoC Nov. 18, 2004

    Industrial Development

    Bureau

    Established the Nang-Kang SoC design district ,providing research units & company EDA tools.

    Set up Special Interest Groups (SIG): Digital Home SIG,TWZigBee SIG, Home Networking SIG, DSC SIG.

    Department ofindustrial

    Technology

    IP Mall -FARADY Co.’s has accumulated 459 IPs, 12 deals be done.Globalunichip Co.’s has accumulated 620 IPs, 30 deals be done.

    EDA Service Plan-SOTA 、Agilent、TSMC、SOCLE

    ExecutionDivisionMajor Projects

    NSoC Emerging Industry Development

  • 29NSoC Nov. 18, 2004

    SoC Design Service ParkNan KongNai HuHsin Teng

    Tau YuanHua YaLong Tang

    Hsin ChuTai Yan

    Tai Chung

    Lu ChuSea Side INDUSTRIAL DEVELOPMENT

    BUREAU MINISTRY OF ECONOMIC AFFAIRS

    Tai Nan

  • 30NSoC Nov. 18, 2004

    Achievement Statistics

    76712811144821644219Amount38442113620573158ForecastFY93 38277078277912711ObtainedFY92 ~FY93

    38442113620573158Amount

    002300000IDBFY93 16281363542511DoITFY93 2216523315148147NSCFY93

    Forecast

    38277078277912711Amount

    00200000IDBFY92 ~FY93 19223816864130DoITFY92 ~FY93

    1953062191502411NSCFY92 ~FY93

    OtherConferenc

    e Paper

    Journalpaper

    IEEE JSSCIC Design

    ISSCC Int’l

    Conference

    Other Technology

    TransferTechnologyPatent

    PapersExecution DivisionYear

  • 31NSoC Nov. 18, 2004

    Total Execution Plan Status (1/2)

    Innovative Product Plan:15Advanced Platform Plan:4Research Centers:10IDB-Leading New Product:20NSC-Integrated &Target-Oriented Plan: 24set,153ea

    Innovative Product Plan:11 Advanced Platform Plan:3Research Centers:7IDB-Leading New Product:10NSC-Environment Plan:5,Integrated&Target-Oriented Plan: 18set, 119 ea

    Integrate EDA Tool and Services

    Comprehensive IP Plan:10Comprehensive IP Plan:9Establish a Rich Store of Silicon IPs

    Establish IP MALL & transactionPlatform Service Plan:4

    IP MALL Project:2Platform Service Plan:4

    Provide Worldwide Customers with Easy Design and SoC Total Solutions

    FY93 TargetCurrent Status(FY92,93 Jan~Sept)

    Goal

  • 32NSoC Nov. 18, 2004

    Total Execution Plan Status (2/2)

    Industry : professional training Course 720 participation,on-job training: 1600 participationStudent : advanced class 3800 participation 3800

    Industry : professional training Course 497 participation,on-job training: 1363 participationStudent : advanced class 3359 participation

    Incubate SIP、EDA Tools、SoC、SiPhuman resources

    FY93 TargetCurrent Status(FY92,93 Jan~Sept)

    Goal

  • 33NSoC Nov. 18, 2004

    Main Achievements in 2004Technology DevelopmentEconomic ImpactSoC R&D Promotion

  • 34NSoC Nov. 18, 2004

    (A) Architecture DesignInstruction Set Architecture DesignMicro-Architecture DesignModule Design

    (B) ImplementationMicro-Architecture ImplementationModule ImplementationIntegrated VerificationChip Realization for 0.18um Process

    (C) SoC/IP Design and EDA EnvironmentEDA Environment SupportSoft IP Package for ProcessorSoC Integration with Peripheral IPsIntegrated Verification in SoC Level

    Technology Development (1/8)

    32-bit Embedded Processor IP

    32-bit Embedded Processor IP Development Project

    (Sunplus Technology)

  • 35NSoC Nov. 18, 2004

    32-bit Embedded Processor IP Development Project

    ModuleDesign

    Micro-Architecture

    Instruction Set Architecture

    Implementation

    Patents

    EDAIP Issues

    SoftwareTool Chain

    DebugVerification

    SystemIntegration(Sunplus Technology)

  • 36NSoC Nov. 18, 2004

    SoC R&D Platform SoC Research

    Embedded System

    Developm

    ent

    Processor Research

    Embedded Softw

    are Developm

    ent

    Instruction Set ArchitectureMicroarchitectureModule Design

    Reuse Methodology

    SoC Integration

    IP Package

    Bus Functional ModelVerification

    Algorithm Implementation

    Assem

    bler

    Operation System

    Com

    piler

    Integrated Develop Environm

    ent

    In-Circuit Em

    ulator

    Evaluation Board

    Instruction Set Simulator

    Applications

    Embedded System

    s

    Test Bench

    Circuit Design

    Hardware/Software Co-design

    EmbeddedProcessor

    (Sunplus Technology)

  • 37NSoC Nov. 18, 2004

    Gigabit NIC Single Chip Program (IC Plus Corporation)

    The 0.13~90nm CMOS Gigabit Ethernet NIC Single ChipThe Lowermost Power Consumption Compared With

    Other 0.18u CMOS Gigabit NIC ICsThe Smallest Die Size Compared With Other 0.18u CMOS

    Gigabit NIC ICs IEEE 802.3 Compliant 1000BASE-T, 100BASE-TX,

    10BASE-TComplete Software Drivers And Utilities SupportPatents

    SCA (Smart Cable Analyzing : Network Physical Layer With Smart Cable Analyzing Function And Application Device Thereof) POA (Power Off Alert : Network Physical Layer With Power Off Alerting Function And Alerting Method Thereof)

    Technology Development (2/8)

  • 38NSoC Nov. 18, 2004

    RSA

    AES01

    C-DMA&

    RNGAES02

    HMAC02

    HMAC01

    Advanced Network Security Processor-Layout View (NTHU)Technology Development (3/8)

  • 39NSoC Nov. 18, 2004

    Platform of Network Security Processor

    Cryptographic

    DM

    A C

    ontroller

    Secret Key Crypto-EngineAES

    Hash EngineHMAC MD5, HMAC SHA-1

    Public Key Crypto-EngineRSA/ECC

    Random NumberGenerator

    ARM922T

    SMI

    NIC

    PMU

    AH

    B

    InternalMemory System

    PLL

    CryptographicProcessor

    PacketProcessor

    TICSMI : Static Memory InterfaceTIC : Test Interface ControllerPMU : Power Management UnitNIC : Network Interface Controller

    (NTHU)

  • 40NSoC Nov. 18, 2004

    Advanced Unified DSP CoreBrand new VLIW instruction set architecture

    Combined compressed form, variouscondition, and rich bundle formats8 pipelining stages Friendly for real-time embedded

    systemsFast context switchLow interrupt latency

    Balancing four aspectsHigh programmabilityHigh configurabilityHigh general purpose computationHigh DSP computation

    Technology Development (4/8)

    ccu

  • 41NSoC Nov. 18, 2004

    System-Wide Power-Aware Design (5/8)

    C program

    Main( ) {Fun1();Fun2();…………

    }

    ArchitectureHardware Tuning• IP Selection• Core Library• Architecture Models

    •Microprocessor•Memory Architecture•Bus Structure

    •Encoding•Cache Organization•Peripherals

    Software Tuning• Power-aware Library• Profiling• Code Optimization• OS scheduling policies• inst. Scheduling• Freq. Scaling• Registers Allocation• ……

    IP1

    IPN

    Memory

    Cache

    Peripherals

    Identify Application Characteristics

    Select Primitive:• Power analysis • Partitioning• Hierarchy• Power / Performance• ……….

    Energy Monitor

    Target SoCApplication Analyzer O.S + Compiler + IPs

    RISC

    DSP

    Component-based Energy

    Instruction-based Energyccu

  • 42NSoC Nov. 18, 2004

    Platform Service Development for RF SoC Design(Agilent Technologies) Program Structure Divided into six sub projects :

    RF SOC Design Flow ServiceEstablish reference design flowIdentify service opportunities

    System Modeling ServicesAssess ADS Behavioral model capability for IP reuseDevelop ADS platform based behavioral modeling and verification services

    Package Modeling ServiceDemonstrate integration of package models into the ADS platformDevelop services for package models in ADS

    Test Preparation ServicePilot Service DemonstrationRF Capability Development

    HighlightsRF SoC Design Flow:

    Encapsulates RF IPCross function integrationProvides engineers mobility and high productivityVirtual vertical integration that allows concurrent design practicesHigh frequency infrastructure maturity model

    ServiceBehavioral modeling and verification service definition

    Technology Development (6/8)

  • 43NSoC Nov. 18, 2004

    The Construction of SIP Mall and SIP Collection Project-FaradayA. Project Goal

    Technology Development (7/8)

    SIP Mall E-Commerce PlatformIT Infrastructure Research and Development

    Adopt J2EE, Oracle, XML, and E-Commerce Security technologiesDesign architecture of e-commerce platform to meet industry demand

    Silicon IP ManagementBuild up an on-line SIP management systemPrepare a GUI interface for IP vendors to perform full-life-cycle IP management, including registration, update and phase-out

    SIP Transfer Protocol and Reuse StandardCollaborate with international organization like VISA and ITRI to establish IP reuse standardSet up IP reuse and qualification standard for IP transfer on SIP Mall website

    SIP Trading and Servicing MechanismCreate standard operating procedure for on-line SIP serviceEnable real-time on-line service for SIP customers and vendors

    SIP Mall Security InfrastructureImplement network security infrastructureImplement data encryption policyImplement firewall to prevent possible intrusion

    SIP Mall Operation and MaintenanceIntegrate all related e-commerce services in one single websiteDevelop and promote on-line SIP business

  • 44NSoC Nov. 18, 2004

    SoC Design Service Platform in 90nm and 130nm generation (TSMC)

    90 nm and130 nm Memory projectComplete 90 nm and130 nm OTP complier circuit and chip design Complete SP and DP SRAM compiler circuit designComplete 1TRAM circuit and chip design

    90 nmand130 nm I/O projectComplete90 nmand130 nm Standard I/O circuit and chip design Complete130 nm 3.125 Gbps SerDes circuit and chip design Complete130 nm PCI Express programming and circuit simulationComplete130 nm USB 2.0 circuit and chip design 90 nmand130 nm Standard Cell projectComplete90 nmand130 nm Standard Cell circuit and chip design 。

    90 nmand130 nm Analog IP projectComplete1.6 GHzand800 MHz PLL circuit and chip design 。Complete400 MHz Single Power and Dual Power PLL circuit and chip design Complete800 MHz de-skew and 1GHz Multi band PLLcircuit and chip designComplete250MHz, 10 bits, Video DAC circuit and chip design

    Technology Development (8/8)

  • 45NSoC Nov. 18, 2004

    Economic Impact

    5240035,084Total Amount

    1815024,600amount138-IDBFY93 Forecast1711224,600DoITFY93 Forecast

    3425010,484amount451-IDBFY92、933019910,484DoITFY92、93

    Private Circles Investment (hundred million)

    Industry Impact

    (hundred million)

    Tech. Transfer (thousand)

    ExecutionYear

  • 46NSoC Nov. 18, 2004

    SoC R&D Promotion(1/3)Define IP Qualification Guideline

    IP Qualification Alliance Established by 14 core members in Taiwan to set complete & implementable IP Integration & Qualification Std. (Apr. 8, 2003)IP Qualification Guidelines V 1.0 released (Nov. 30, 2003)IP Qualification Guidelines (VHDL Version)V 1.0 released (Oct.22, 2004)

    Promote Star IP Plan in academiaDevelop advanced IP for SoC Integration.Target advanced application domain.Through research institutes for seamless technology transfer。

  • 47NSoC Nov. 18, 2004

    STC set up ”SoC Technology Center”System on Chip Key Technology Development 4 Year Project Domestic Communication and Optoelectronics Infrastructure Construction Project

    Chung-Shan Institute of Science & Technology develop SoC technologyUWB System Platform and IP Development Project WCDMA WLL Development Project (under National Teccomm. Program)

    Universities Establish SoC CentersAdvanced Network Security Processor and the Related SOC Design and Test Technologies (NTHU)Key Components for Fixed Wireless Communications (NCU)Experimental Project for SoC Collection,Verification and Interface Integration (NCTU)Experimental Project for SoC Collection,Verification and Interface Integration (NCTU、NCU、NCKU、NTU)

    SoC R&D Promotion(2/3)

  • 48NSoC Nov. 18, 2004

    Universities Establish SoC CentersAdvanced Network Security Processor and the Related SOC Design and Test Technologies (NTHU)Key Components for Fixed Wireless Communications (NCU)Experimental Project for SoC Collection,Verification and Interface Integration (NCTU)Experimental Project for SoC Collection,Verification and Interface Integration (NCTU、NCU、NCKU、NTU)

    4G and B3G Research and DevelopmentOFDM, MIMO and Intelligent BS TechnologiesSystem and Architecture Design: NTPFPGA, Key Component essential IPR: NSOCParticipants: ITRI, CSIST, III, domestic industry

  • 49NSoC Nov. 18, 2004

    SoC R&D Promotion(3/3)Introduce Domestic Research Centers

    Viatech - VIA Advanced Technology Development CenterAdvantech - Embedded System R&D CenterQuanta - Quanta Research Institute

    Introduce International Research CentersIntel - Intel Innovation CenterBroadcom - Network SoC R&D CenterPericom - Advanced Mixed-Signal IC R&D CenterSynopsys - VDSM (Very-Deep Sub-Micron) EDA R&D

    Center

  • 50NSoC Nov. 18, 2004

    Si-Soft Research CenterTransition From Manufacturing Industry to Value

    added Design Service

  • 51NSoC Nov. 18, 2004

    New Business ModelFacilitate the Exchanges of Valuable IPs

    Function Enhancement / Cost Reduction

    System Houses Fabless Foundry

    Valuable Silicon IP Exchanges

    Enter into USA, Europe, Japan and China Markets

    Silicon IPs

    Government

  • 52NSoC Nov. 18, 2004

    New SoC Business Frontiers

    IP Mall Service

    SIPP

    EDA Service

    Company

    Data Center

    VC Service

    FoundryPackage, Test

    Office

    SoC

    Put all the SoC support under one roof.

    SoC Innovative Product Partnership (SIPP)

  • 53NSoC Nov. 18, 2004

    Design Service

    IC Channel

    Testing

    Foundry

    Fabless

    Package

    SystemEMS

    Data Center

    SoC Innovative Product Partnership (SIPP)

    IP Mall

    EDA Service

    SoC Platform

    Si-Soft Promotion Projects

    Global SoC Total Solution

    SoC Supply Chains

  • 54NSoC Nov. 18, 2004

    SoC technology and design have become a dominant focus in today's global ICs industryTaiwan Government ‘s Endorsement

    Si-Soft Initiative National SoC Program

    Taiwan SoC Design Service ParkNew SoC Business Model (SIPP)

    Summaries

  • 55NSoC Nov. 18, 2004

    Appendix

    Market AnalysisIP /SOC Market Overview and Outlook

    What is or should be D&R’s role in the IP businessSession 1A: IP Business modelSession 2A: Design PlatformSession 3A: Industrial Reuse PracticeSession 4A: ASIC Design PlatformSession 5A: Design MethodologySession 6A: Design MethodologySession 7A: Industrial IP Design practiceOpen Forum 1A: VerificationOpen Forum 1B: Reuse PracticeOpen Forum 2B: Design MethodologiesSession 1B: Best IP PrizeSession 2B: IP SOC VerificationSession 3B: Best IP PrizeSession 4B : VerificationSession 5B: Multi-Processor and Multi-Thread SOC

  • 56NSoC Nov. 18, 2004

    Si-Soft Initiative

    Thank you for your attention

    Your comments and suggestions are very much appreciated

    National SoC Program