12

3 4

PowerFLAT 5x6 VHV

AM15540v6

5678

1 2 3 4

Top View

D(5, 6, 7, 8)

G(4)

S(1, 2, 3)

FeaturesOrder code VDS RDS(on) max. ID

STL7LN65K5AG 650 V 1.15 Ω 5 A

• AEC-Q101 qualified • Industry’s lowest RDS(on) x area• Industry’s best FoM (figure of merit)• Ultra-low gate charge• 100% avalanche tested• Zener-protected

Applications• Switching applications

DescriptionThis very high voltage N-channel Power MOSFET is designed using MDmeshK5 technology based on an innovative proprietary vertical structure. The result isa dramatic reduction in on-resistance and ultra-low gate charge for applicationsrequiring superior power density and high efficiency.

Product status link

STL7LN65K5AG

Product summary

Order code STL7LN65K5AG

Marking 7LN65K5

Package PowerFLAT 5x6VHV

Packing Tape and reel

Automotive-grade N-channel 650 V, 0.95 Ω typ., 5 A, MDmesh K5 Power MOSFET in a PowerFLAT 5x6 VHV package

STL7LN65K5AG

Datasheet

DS13267 - Rev 2 - November 2020For further information contact your local STMicroelectronics sales office.

www.st.com

https://www.st.com/en/product/STL7LN65K5AG?ecmp=tt9470_gl_link_feb2019&rt=ds&id=DS13267

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ± 30 V

ID (1) Drain current (continuous) at TC = 25 °C 5 A

ID (1) Drain current (continuous) at TC = 100 °C 3.4 A

ID (2) Drain current (pulsed) 20 A

PTOT Total power dissipation at TC = 25 °C 79 W

dv/dt (3) Peak diode recovery voltage slope 4.5V/ns

dv/dt (4) MOSFET dv/dt ruggedness 50

Tstg Storage temperature range- 55 to 150 °C

TJ Operating junction temperature range

1. Limited by maximum junction temperature.2. Pulse width limited by safe operating area.3. ISD ≤ 5 A, di/dt 100 A/μs; VDS peak < V(BR)DSS,VDD= 520 V.

4. VDS ≤ 520 V.

Table 2. Thermal data

Symbol Parameter Value Unit

RthJA Thermal resistance, junction-to-case 1.58 °C/W

RthJB (1) Thermal resistance, junction-to-board 59 °C/W

1. When mounted on 1inch² FR-4 board, 2 oz Cu.

Table 3. Avalanche characteristics

Symbol Parameter Value Unit

IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.5 A

EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 200 mJ

STL7LN65K5AGElectrical ratings

DS13267 - Rev 2 page 2/16

2 Electrical characteristics

TC = 25 °C unless otherwise specified.

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 650 V

IDSS Zero gate voltage drain current

VGS = 0 V, VDS = 650 V 1 µA

VGS = 0 V, VDS = 650 V,TC = 125 °C (1)

50 µA

IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V ±10 µA

VGS(th) Gate threshold voltage VDS = VGS, ID =100 µA 3 4 5 V

RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2.5 A 0.95 1.15 Ω

1. Defined by design, not subject to production test.

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance

VDS= 100 V, f = 1 MHz, VGS = 0 V

- 270 - pF

Coss Output capacitance - 22 - pF

Crss Reverse transfer capacitance - 0.5 - pF

Co(er) (1)Equivalent capacitance energyrelated

VDS = 0 to 520 V, VGS = 0 V- 20 - nC

Co(tr) (2)Equivalent capacitance timerelated - 57 - nC

RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 7.5 - Ω

Qg Total gate chargeVDD = 520 V, ID = 5 A, VGS = 0to 10 V (see Figure 14. Test circuitfor gate charge behavior)

- 11.7 - nC

Qgs Gate-source charge - 2.7 - nC

Qgd Gate-drain charge - 7.3 - nC

1. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increasesfrom 0 to 80% VDSS

2. Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increasesfrom 0 to 80% VDSS

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 300 V, ID = 2.5 ARG = 4.7 Ω, VGS = 10 V(see Figure 13. Test circuit forresistive load switching timesand Figure 18. Switching timewaveform)

- 7.4 - ns

tr Rise time - 9.2 - ns

td(off) Turn-off delay time - 19.8 - ns

tf Fall time - 16.4 - ns

STL7LN65K5AGElectrical characteristics

DS13267 - Rev 2 page 3/16

Table 7. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 5 A

ISDM (1) Source-drain current (pulsed) - 20 A

VSD (2) Forward on voltage ISD= 5 A, VGS = 0 V - 1.6 V

trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs,VDD = 60 V (see Figure 15. Testcircuit for inductive load switchingand diode recovery times)

- 282 ns

Qrr Reverse recovery charge - 1.97 µC

IRRM Reverse recovery current - 14 A

trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs,VDD = 60 V, Tj = 150 °C(see Figure 15. Test circuit forinductive load switching and dioderecovery times)

- 415 ns

Qrr Reverse recovery charge - 2.70 µC

IRRM Reverse recovery current - 13 A

1. Pulse width is limited by safe operating area2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

Table 8. Gate-source Zener diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)GSO Gate-source breakdown voltage IGS = ±1 mA, ID = 0 A 30 - V

The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need foradditional external componentry.

STL7LN65K5AGElectrical characteristics

DS13267 - Rev 2 page 4/16

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area

GADG201120201305SOA

10 1

10 0

10 -1 10 -1 10 0 10 1 10 2 10 3

ID (A)

VDS (V)

tp = 100µs

tp = 1µs

tp = 10µs

tp = 1ms

tp = 10ms

Operation in this area is limited by R DS(on)

T j ≤150 °CT c = 25°C

single pulse

Figure 2. Maximum transient thermal impedance

GADG040320200927ZTH

10-6 10-5 10-4 10-3 10-2 tp (s)

ton

T

duty = ton / TRthJ-C = 1.58 °C/W

ZthJ-C(°C/W)

0.05

0.3

0.20.1

0.4

Single pulse

duty=0.5

10-1

10-2

100

Figure 3. Typical output characteristics

GIPG151220151129OCH

9

6

3

00 4 8 12 16

I D (A)

V DS (V)V GS = 6 V

V GS = 7 V

V GS = 8 V

V GS = 9 V

V GS = 11 VV GS = 10 V

Figure 4. Typical transfer characteristics

GIPG151220151128TCH

9

6

3

05 6 7 8 9 10

I D (A)

V GS (V)

V DS = 20 V

Figure 5. Typical gate charge characteristics

GADG270220201101QVG

600

500

400

300

200

100

0

12

10

8

6

4

2

00 2 4 6 8 10 12 14

VGS (V)

VDS (V)

Qg (nC)

Qgs Qgd

VDD = 520 VID = 5 A

Qg

Figure 6. Typical drain-source on-resistance

GIPG151220151128RID

1.2

1.0

0.8

0.60 1 2 3 4 5

R DS(on) (Ω)

I D (A)

V GS = 10 V

STL7LN65K5AGElectrical characteristics (curves)

DS13267 - Rev 2 page 5/16

Figure 7. Typical capacitance characteristics

GADG260220201245CVR

103

102

101

100

10-110 -1 10 0 10 1 10 2

C (pF)

VDS (V)

Ciss

Coss

Crss

Figure 8. Normalized gate threshold vs temperature

GIPG151220151134VTH

1.2

1.0

0.8

0.6

0.4

0.2-50 0 50 100

V GS(th) (norm.)

T j (°C)

I D = 100 µA

Figure 9. Normalized breakdown voltage vs temperature

GIPG151220151133BDV

1.12

1.08

1.04

1.00

0.96

0.92

0.88-50 0 50 100

V (BR)DSS (norm.)

T j (°C)

I D = 1 mA

Figure 10. Normalized on-resistance vs temperature

GADG260220201247RON

2.5

2.0

1.5

1.0

0.5

0.0-75 -25 25 75 125

RDS(on) (norm.)

VGS = 10 V

TJ (°C)

Figure 11. Typical reverse diode forward characteristics

GIPG151220151156SDF

1.0

0.9

0.8

0.7

0.6

0.50 1 2 3 4 5

V SD (V)

I SD (A)

T j = -50 °C

T j = 25 °C

T j = 150 °C

Figure 12. Maximum avalanche energy vs temperature

GIPG151220151157EAS

200

150

100

50

0-50 0 50 100

E AS (m J)

T J (°C)

I D = 1.5 AV DD = 50 VSingle pulse

STL7LN65K5AGElectrical characteristics (curves)

DS13267 - Rev 2 page 6/16

3 Test circuits

Figure 13. Test circuit for resistive load switching times

AM01468v1

VD

RG

RL

D.U.T.

2200μF VDD

3.3μF+

pulse width

VGS

Figure 14. Test circuit for gate charge behavior

AM01469v10

47 kΩ

2.7 kΩ

1 kΩ

IG= CONST 100 Ω D.U.T.

+pulse widthVGS

2200μF

VG

VDD

RL

Figure 15. Test circuit for inductive load switching anddiode recovery times

AM01470v1

AD

D.U.T.S

B

G

25 Ω

A A

B B

RG

GD

S

100 µH

µF3.3 1000

µF VDD

D.U.T.

+

_

+

fastdiode

Figure 16. Unclamped inductive load test circuit

AM01471v1

VD

ID

D.U.T.

L

VDD+

pulse width

Vi

3.3µF

2200µF

Figure 17. Unclamped inductive waveform

AM01472v1

V(BR)DSS

VDD VDD

VD

IDM

ID

Figure 18. Switching time waveform

AM01473v1

0

VGS 90%

VDS

90%

10%

90%

10%

10%

ton

td(on) tr

0

toff

td(off) tf

STL7LN65K5AGTest circuits

DS13267 - Rev 2 page 7/16

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,depending on their level of environmental compliance. ECOPACK specifications, grade definitions and productstatus are available at: www.st.com. ECOPACK is an ST trademark.

STL7LN65K5AGPackage information

DS13267 - Rev 2 page 8/16

https://www.st.com/ecopackhttp://www.st.com

4.1 PowerFLAT 5x6 VHV mechanical data

Figure 19. PowerFLAT 5x6 VHV package outline

Bottom view

Side view

Top view

1 2 3 4

Pin 1identification

8 7 6 5

8 7 6 5

1 2 3 4Pin 1identification

8368144_REV_3

STL7LN65K5AGPowerFLAT 5x6 VHV mechanical data

DS13267 - Rev 2 page 9/16

Table 9. PowerFLAT 5x6 VHV package mechanical data

Dim.mm

Min. Typ. Max.

A 0.80 1.00

A1 0.02 0.05

A2 0.25

b 0.30 0.50

D 5.00 5.20 5.40

E 5.95 6.15 6.35

D2 4.30 4.40 4.50

E2 2.40 2.50 2.60

e 1.27

L 0.50 0.55 0.60

K 2.60 2.70 2.80

STL7LN65K5AGPowerFLAT 5x6 VHV mechanical data

DS13267 - Rev 2 page 10/16

Figure 20. PowerFLAT 5x6 VHV recommended footprint (dimensions are in mm)

8368144_REV_3_footprint

STL7LN65K5AGPowerFLAT 5x6 VHV mechanical data

DS13267 - Rev 2 page 11/16

4.2 PowerFLAT 5x6 packing information

Figure 21. PowerFLAT 5x6 tape (dimensions are in mm)

(I) Measured from centreline of sprocket hole to centreline of pocket.

(II) Cumulative tolerance of 10 sprocket holes is ±0.20.

(III) Measured from centreline of sprocket hole to centreline of pocket

Base and bulk quantity 3000 pcsAll dimensions are in millimeters

8234350_Tape_rev_C

Figure 22. PowerFLAT 5x6 package orientation in carrier tape

Pin 1 identification

STL7LN65K5AGPowerFLAT 5x6 packing information

DS13267 - Rev 2 page 12/16

Figure 23. PowerFLAT 5x6 reel

STL7LN65K5AGPowerFLAT 5x6 packing information

DS13267 - Rev 2 page 13/16

Revision history

Table 10. Document revision history

Date Version Changes

04-Mar-2020 1 First release.

20-Nov-2020 2Updated Figure 1. Safe operating area.

Minor text changes.

STL7LN65K5AG

DS13267 - Rev 2 page 14/16

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1 PowerFLAT 5x6 VHV mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

STL7LN65K5AGContents

DS13267 - Rev 2 page 15/16

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2020 STMicroelectronics – All rights reserved

STL7LN65K5AG

DS13267 - Rev 2 page 16/16

http://www.st.com/trademarks

FeaturesApplicationsDescription1 Electrical ratings2 Electrical characteristics2.1 Electrical characteristics (curves)

3 Test circuits4 Package information4.1 PowerFLAT 5x6 VHV mechanical data4.2 PowerFLAT 5x6 packing information

Revision history