CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F =...

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CSE 370 Sample Final Exam Questions

Transcript of CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F =...

Page 1: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

CSE 370

Sample Final Exam Questions

Page 2: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

1) Logic Minimization

CDAB

00 01 11 10

00

01

11

10

F =  Σm(0,6,7,8,9,11,15) +  d(1,13)

Page 3: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

1) Logic Minimization

1 1

d d 1

1 1 1

1

CDAB

00 01 11 10

00

01

11

10

F =  Σm(0,6,7,8,9,11,15) +  d(1,13)

Page 4: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

1) Prime Implicants

1 1

d d 1

1 1 1

1

CDAB

00 01 11 10

00

01

11

10

Note: Prime Implicant = largest box covering a 1

Page 5: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

1) Essential PI’s

1 1

d d 1

1 1 1

1

CDAB

00 01 11 10

00

01

11

10

Note: Essential PI = PI’s that cover a 1 not covered by any other PI’s

Page 6: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

1) Logic Minimization

1 1

d d 1

1 1 1

1

CDAB

00 01 11 10

00

01

11

10

Prime Implicants: B’C’, AD, A’BC, BCD

Essential Prime Implicants: B’C’, AD, A’BC

Minimal Cover: F = B’C’ + AD + A’BC

Page 7: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

2a) Gates to Functions back into Gates

FG

H

Page 8: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

2a) Gates to Functions back into Gates

FG

H

Z = ~(H + G)

Z = ~H & ~G

Z = ~(~(C+D)) & ~(~(F+F))

Z = (C+D) & F

Z = (C+D) & ~(A+B)

Z = (C+D) & ~A & ~B

Z = A’B’C + A’B’D

Page 9: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

2b) Gates to Functions back into Gates

Z = A’B’C + A’B’DZ = A’B’C + A’B’D

Using deMorgan’s Law…

Z = ~(~(A’B’C) & ~(A’B’D))

CA’

B’

D

Page 10: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

2c) Gates to Functions back into Gates

NOR Circuit 3 gate delays @ 7ns 21ns total

NAND Circuit 2 gate delays @ 9ns 18ns total

Page 11: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

3a) Multiplexer Logic

Z = B’C + A’BD + AB’

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B C D Z

Page 12: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

3a) Multiplexer Logic

Z = B’C + A’BD + AB’

0 0 0 0

0 0 0 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B C D Z

Page 13: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

3a) Multiplexer Logic

Z = B’C + A’BD + AB’

0 0 0 0

0 0 0 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0

0 1 0 1 1

0 1 1 0

0 1 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B C D Z

Page 14: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

3a) Multiplexer Logic

Z = B’C + A’BD + AB’

0 0 0 0

0 0 0 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0

0 1 0 1 1

0 1 1 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B C D Z

Page 15: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

3a) Multiplexer Logic

Z = B’C + A’BD + AB’

0 0 0 0 0

0 0 0 1 0

0 0 1 0 1

0 0 1 1 1

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 0

A B C D Z

Page 16: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

3b) Multiplexer Logic0123456789101112131415

S3 S2 S1 S0

16:1 MUX

Z = B’C + A’BD + AB’

0011010111110000

A B C D

Page 17: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

3c) Multiplexer Logic

01234567

S2 S1 S0

8:1 MUX Z = B’C + A’BD + AB’

1

1

Z = B’C + A’BD + AB’

A B C

Z = B’C + A’BD + AB’

1DD

1

Z = B’C + A’BD + AB’

1DD11

Z = B’C + A’BD + AB’

01DD1100

Note: Requires no extra logic

Page 18: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

4) Decoder Logic

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

W = (A xor C) + B

A B C W

Page 19: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

4) Decoder Implementation

01234567

S2 S1 S0

3:8 DEC

A B C

W = (A xor C) + B

EN1

Page 20: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

5) Programmable LogicX Y

Note: 2 Common Prime Implicants can be used by X and Y

Z = A’BCD’ + ABC’D’

X = Z + A’B’CD + AB’C’D

Y = Z + A’B’C + AB’C’

Page 21: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

5) Programmable Logic

Z = A’BCD’ + ABC’D’

X = Z + A’B’CD + AB’C’D

Y = Z + A’B’C + AB’C’

Z = A’BCD’ + ABC’D’

X = Z + A’B’CD + AB’C’D

Y = Z + A’B’C + AB’C’

Page 22: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

6) Verilog to Circuit

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

clk

A B C

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

clk

A B C

CBA

Page 23: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

7) Circuit to Verilog

Page 24: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

7) Circuit to Verilog

module maxValue (DataOut, strobe, Data);

// Port Definitions

output reg [7:0] DataOut;

input strobe;

input [7:0] Data;

// Behavioral Statements for DataOut

// other required internal signals

endmodule

Page 25: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

7) Circuit to Verilog

// Behavioral Statements for DataOut

always @ (posedge clk) begin

if (regEnable) DataOut <= Data;

else DataOut <= DataOut;

end

Page 26: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

7) Circuit to Verilog

regEnable

strobeNegedge

prevStrobe[2]

prevStrobe[1]

prevStrobe[0]

Page 27: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

7) Circuit to Verilog

// other required internal signalswire regEnable, strobeNegedge;reg prevStrobe[2:0];

assign regEnable = (Data > DataOut) && strobeNegedgeassign strobeNegedge = prevStrobe[2] & ~prevStrobe[1];

always @ (posedge clk) prevStrobe = {prevStrobe[1:0],strobe};

Page 28: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

8) Carry Look-ahead Adder

Recall:

Sum = A xor B xor C

Cout = AB + BC + AC

Rewrite Cout:

Cout = AB + C (A + B)

Page 29: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

8) Carry Look-ahead Adder

0 0 0 0

0 1 1 1

1 0 1 1

1 1 0 1

A B PXOR POR

2 functions are only different if A and B are 1

Page 30: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

8) Carry Look-ahead Adder Need carry out if A and B are 1

carry is generated in this case don’t need propagate to cover this case these are then functionally equivalent

Recall: Sum = A xor B xor C P = A + B: have to calculate A xor B P = A xor B: reuse this to compute Sum P = A xor B uses less logic

Page 31: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

9) Verilog State Machine

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 0 0 1 0

0 0 1 1 0 1 0

0 1 0 0 0 1 1

0 1 0 1 1 0 0

0 1 1 0 0 1 0

0 1 1 1 1 0 0

1 0 0 0 1 1 0

1 0 0 1 1 1 0

1 0 1 0 1 0 1

1 0 1 1 1 0 0

1 1 0 0 0 0 0

1 1 0 1 1 1 0

1 1 1 0 0 0 0

1 1 1 1 1 1 1

A BS[1] NS[0]NS[1]S[0] out0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Page 32: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

9) Verilog State Machine

1

1

1

1

S[1:0]

AB 00 01 11 10

00

01

11

10

out

1

1 1 1

1 1 1

1

00 01 11 10

00

01

11

10

NS[1]

1 1

1 1

1 1

1 1

00 01 11 10

00

01

11

10

NS[0]S[1:0]

AB

S[1:0]

AB

NS[1]=S[0]B + S[1]S[0]’

NS[0] = S[1]’S[0]B’ + S[1]S[0]’A’ + S[1]S[0]B + S[1]’S[0]’A

out = S[1]’S[0]’A’B + S[1]’S[0]A’B’ + S[1]S[0]’AB’ + S[1]S[0]AB

Page 33: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

9) Verilog State Machine

Q

QSET

CLR

D

clk

Q

QSET

CLR

D

out

S[0]

S[1]

AB

A’B

A’B’

AB’

NS[1]

A

B S[0]

S[1]S[0]

NS[0]

S[1]’S[0]S[1]S[0]’S[1]S[0]S[1]’S[0]’

Q

QSET

CLR

D

clk

Q

QSET

CLR

D

out

S[0]

S[1]

A

B

Page 34: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

10) Design: Parallel to Serial Shift Register

Load parallel data Shift out serial data

Counter How many bits have shifted out

Controller Shift Enable Done Shifting

Page 35: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

10a) Design: Parallel to Serial

Shifter

dataIn

load

dataOut

Counter

reset

clk

count

char[7:0]

start

reset

clk

clk

Controller

clksdata

done

Datapath

start

reset

count

load

reset_cnt

done

Page 36: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

DONE

IDLE LOADED

SENDING

10b) Design: Parallel to Serial

reset

0,x / load=0,rst_cnt=1

done=0

1,x / load=1,rst_cnt=1

0,x / load=0,rst_cnt=0

1,x / load=1,rst_cnt=1

1,x / load=1,rst_cnt=1

0,4’hA / load=0,rst_cnt=1

0,count<4'hA / load=0,rst_cnt=0

0,x / load=0,rst_cnt=1

done=0

done=0done=1

1,x / load=1,rst_cnt=1

Inputs: start, countOutputs: load, rst_cnt, done

Can we collapse these to 1 state?

Page 37: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

10b) Design: Parallel to Serial

IDLE

SENDINGDONE

reset

0,x / load=0,rst_cnt=1

done=0 1,x / load=1,rst_cnt=1

0,4’hA / load=0,rst_cnt=1

1,x / load=1, rst_cnt=10,count<4'hA / load=0,

rst_cnt=0

0,x / load=0,rst_cnt=1

done=0done=1

1,x / load=1,rst_cnt=1

Inputs: start, countOutputs: load, rst_cnt, done

Page 38: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

10c) Design: Parallel to Serial

Shifter

dataIn[8:0]

load

dataOut[8:0]

Counter

reset

clk

count

clk sdata= dataOut[0]

done = state[1]

{char,1’b0}

start

clk

dataOut[8:0]

Register

nextState[1]

clk

state

Note: Shifter shifts in 1 in MSB

clk

count[3:0]

clk

state[1:0]

start + state[1] + state[1:0]==0

+ ((state==1)&&(count==4’hA)

~start && (state==1) && (count==4’hA)

nextState[0]start + ((state==1)&&(count<4’hA))

char[7:0]

start

reset

clk

Page 39: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

11) x370 CALL Instruction

CALL Requirements Load address into PC from instruction Store PC+1 into RD

Page 40: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

11) Implementation Load address into PC

inst[5:0] muxed to input of PC Load PC asserted

Store PC+1 into RD PC muxed to A input of ALU ALU inst set to INC ALU output muxed to reg write data Reg write address set to RD

Page 41: CSE 370 Sample Final Exam Questions. 1) Logic Minimization CD AB 00011110 00 01 11 10 F = Σm(0,6,7,8,9,11,15) + d(1,13)

Final Questions?